JPS63187915A - Reference voltage generating circuit - Google Patents
Reference voltage generating circuitInfo
- Publication number
- JPS63187915A JPS63187915A JP62020913A JP2091387A JPS63187915A JP S63187915 A JPS63187915 A JP S63187915A JP 62020913 A JP62020913 A JP 62020913A JP 2091387 A JP2091387 A JP 2091387A JP S63187915 A JPS63187915 A JP S63187915A
- Authority
- JP
- Japan
- Prior art keywords
- reference voltage
- ground potential
- potential
- circuit
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009826 distribution Methods 0.000 claims abstract description 4
- 238000001514 detection method Methods 0.000 claims description 4
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- Logic Circuits (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は基準電圧発生回路に関し、特に半導体集積回路
において電流切換型論理回路に必要な各種基準電圧を供
給するための基準電圧発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit for supplying various reference voltages required for current switching type logic circuits in semiconductor integrated circuits.
電流切換型論理回路は、高速論理動作用の代表的な論理
回路として集積回路化され、コンピュータ・電子機器等
の高速分野用の各種LSI等に広く使用されている。代
表的な回路構成例を第4図に示す。本回路は、接地電位
GNDを基準とした電源電圧VEEが供給され、入力端
子11 ・I2の入力信号に対し、2人力OR/N O
R論理動作を行い出力端子P、・R2から出力信号を得
る例であるが、電流切換型論理回路の特徴として各種の
基準電圧が必要となってくる。まず基準電圧VREPは
参照電圧とも呼ばれており、入力端子IN ・I2に印
加された高レベルまたは低レベルの論理レベルに対して
常にその中央の電位が供給され、入力端子工1 ・I2
の論理レベルに応じてトランジスタQ1〜Q3がオン・
オフ動作を行い、トランジスタQ4および抵抗R3によ
り構成された定電流回路の電流が抵抗R,またはR2に
流れ全体として論理動作を行うものである。また、基準
電圧VC52は、前述の定電流回路用の基準電圧として
トランジスタQ4のベースにバイアス電位を与えるもの
である。Current switching type logic circuits are integrated circuits as typical logic circuits for high-speed logic operation, and are widely used in various LSIs for high-speed fields such as computers and electronic equipment. A typical circuit configuration example is shown in FIG. This circuit is supplied with a power supply voltage VEE based on the ground potential GND, and performs two-man OR/N O for input signals at input terminals 11 and I2.
Although this is an example in which the R logic operation is performed and output signals are obtained from the output terminals P and R2, various reference voltages are required as a characteristic of the current switching type logic circuit. First, the reference voltage VREP is also called a reference voltage, and its center potential is always supplied to the high or low logic level applied to the input terminal IN/I2.
Transistors Q1 to Q3 are turned on and off depending on the logic level of
It performs an OFF operation, and the current of the constant current circuit constituted by the transistor Q4 and the resistor R3 flows through the resistor R or R2, and the entire circuit performs a logical operation. Further, the reference voltage VC52 provides a bias potential to the base of the transistor Q4 as a reference voltage for the constant current circuit described above.
通常、これらの基準電圧vREF−vcs2は集積回路
内部のすべての電流切換型論理回路に共通に使用される
ため、基板の周辺部に配置された少なくとも1個の基準
電圧発生回路ICからすべての電流切換型論理回路に供
給されており、これにより基板上における基準電圧発生
回路ICの占有面積の低減をも図っている。基準電圧■
REFは内部論理振幅の中央にある必要があり、これが
ずれると内部の雑音マージンが低下する。また、基準電
圧V。S□はやはり内部論理振幅を決定しており、論理
振幅は大きく設定すれば内部動作マージンの点で有利に
なるが、逆に動作速度などの性能面では悪化するため、
必要な動作マージンを確保しつつ最小の論理振幅に設定
する必要がある。Normally, these reference voltages vREF-vcs2 are commonly used by all current switching type logic circuits inside the integrated circuit, so all currents from at least one reference voltage generation circuit IC placed around the periphery of the board are The voltage is supplied to the switching type logic circuit, thereby reducing the area occupied by the reference voltage generation circuit IC on the board. Reference voltage■
REF must be in the middle of the internal logic amplitude; any deviation from this will degrade the internal noise margin. Also, the reference voltage V. S□ still determines the internal logic amplitude, and if the logic amplitude is set large, it will be advantageous in terms of internal operation margin, but on the contrary, it will deteriorate in terms of performance such as operation speed.
It is necessary to set the logic amplitude to the minimum while ensuring the necessary operating margin.
そのため従来の技術による基準電圧発生回路ICは、ト
ランジスタQ15・Q17と抵抗R15〜RI7で構成
され、トランジスタQ17のベースはあらかじめ準備さ
れた他の基準電圧■cs1により駆動されており、トラ
ンジスタQ+7のコレクタには抵抗RI5・R16の比
で決定される一定電圧か得られる。Therefore, the reference voltage generation circuit IC according to the conventional technology is composed of transistors Q15 and Q17 and resistors R15 to RI7, the base of transistor Q17 is driven by another reference voltage cs1 prepared in advance, and the collector of transistor Q+7 is driven by another reference voltage cs1 prepared in advance. A constant voltage determined by the ratio of resistors RI5 and R16 can be obtained.
さらにトランジスタQ15のベース・エミッタ間順方向
電圧分だけ電位シフトした一定電位が、Qlsのエミッ
タに得られて基準電圧VREFとして、電流切換型論理
回路に供給されるものである。Furthermore, a constant potential shifted by the forward voltage between the base and emitter of transistor Q15 is obtained at the emitter of Qls and is supplied to the current switching type logic circuit as reference voltage VREF.
基準電圧V。s2は、通常は他の基準電圧発生面路によ
り駆動されるので、ここでは省略されているが、やはり
一定の電位が供給される。基準電圧VREFの電位は入
力端子1. ・■2の電位の中央に常に位置する必要
があるため、抵抗R15の両端の電位差は通常R1〜R
2の両端の電位差、すなわち論理振幅の半分に設定され
ている。Reference voltage V. Since s2 is normally driven by another reference voltage generation plane, it is omitted here, but is still supplied with a constant potential. The potential of the reference voltage VREF is at the input terminal 1.・Since it must always be located in the center of the potential of 2, the potential difference between both ends of resistor R15 is usually R1 to
It is set to the potential difference between both ends of 2, that is, half the logic amplitude.
一般に、集積回路基板上の素子の特性は均一に出来てい
るので、本回路のような構成をとることができ、集積回
路製作プロセス上のばらつきがあっても基準電圧VRε
Fを内部論理レベルの中央に設定することが可能となっ
ている。In general, the characteristics of the elements on an integrated circuit board are uniform, so a configuration like this circuit can be used, and even if there are variations in the integrated circuit manufacturing process, the reference voltage VRε
It is possible to set F to the center of the internal logic level.
上述した従来の基準電圧発生回路ICはその接地端子の
電位と電流切換型論理回路の接地端子の電位とは等しい
ことを前提として設計されているため、それぞれの接地
端子の間に電位差がある場合には、それがそのまま基準
電圧の変動となり、内部動作マージンの低下を招くとい
う欠点がある。The conventional reference voltage generation circuit IC described above is designed on the premise that the potential of its ground terminal is equal to the potential of the ground terminal of the current switching type logic circuit, so if there is a potential difference between the respective ground terminals, However, this has the disadvantage that it directly causes fluctuations in the reference voltage, leading to a reduction in the internal operating margin.
特に近年のLS、1.VLSI等に於ける集積度の向上
は目覚しく、これに伴うチップサイズの拡大・消費電力
の増加によって基板内部に於ける接地電位の分布差は広
がる傾向にあるため、この問題はますます顕著になりつ
つある。Especially recent LS, 1. The degree of integration in VLSI, etc. has been increasing rapidly, and as the chip size and power consumption have increased, the difference in ground potential distribution inside the substrate tends to widen, so this problem is becoming more and more prominent. It's coming.
本発明は従来の基準電圧発生回路の問題点を解。The present invention solves the problems of conventional reference voltage generation circuits.
決し、LSI基板上の接地電位について、周辺部の接地
電位と中央部の最も低下し゛ていると思われる接地電位
との電位差を検出し、その電位差に応じて自動的に最適
な基準電圧を供給するという独創的内容を有するもので
ある。Regarding the ground potential on the LSI board, the system detects the potential difference between the ground potential at the periphery and the ground potential at the center, which is considered to be the lowest, and automatically supplies the optimal reference voltage according to that potential difference. It has original content.
本発明の基準電圧発生回路は、電流切換型論理回路に必
要な準備電圧を供給する基準電圧発生回路おいて、前記
電流切換型論理回路を搭載した集積回路基板上の接地電
位の分布を検出しその電位差に応じて前記電流切換型論
理回路の基準電圧を供給する接地電位検出手段を備えて
構成される。The reference voltage generation circuit of the present invention detects the distribution of ground potential on an integrated circuit board on which the current switching type logic circuit is mounted, in the reference voltage generation circuit that supplies a necessary preparation voltage to the current switching type logic circuit. The device is configured to include ground potential detection means for supplying a reference voltage for the current switching type logic circuit according to the potential difference.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1〜第3図は本発明を含む第一〜第三の実施例の構成
を示す回路図である。1 to 3 are circuit diagrams showing the configurations of first to third embodiments including the present invention.
第1図を見るに、トランジスタQ1〜Q4・抵抗R1〜
R3で構成される回路は代表的な電流切換型論理回路で
あり、接地電位GNDを基準とした電源電圧VERと、
論理回路の作動の中心値を示す参照電圧として基準電圧
VREFと、論理回路の作動の振幅に対応する基準電圧
VC8とが供給され、2人力のOR/NOR論理動作を
行っている。Looking at Figure 1, transistors Q1 to Q4 and resistors R1 to
The circuit composed of R3 is a typical current switching type logic circuit, and has a power supply voltage VER based on the ground potential GND,
A reference voltage VREF as a reference voltage indicating the center value of the operation of the logic circuit and a reference voltage VC8 corresponding to the amplitude of the operation of the logic circuit are supplied, and a two-manpower OR/NOR logic operation is performed.
本発明では、上述の電流切換型論理回路に電源電圧・基
準電圧を供給するに際し1.LSI上に搭載された電流
切換型論理回路の接地電位を例えば2箇所で検出して、
そのうち、最も電源電圧V。In the present invention, when supplying the power supply voltage and reference voltage to the above-mentioned current switching type logic circuit, 1. By detecting the ground potential of the current switching type logic circuit mounted on the LSI at two locations, for example,
Among them, the power supply voltage V is the highest.
に近い接地電位を基準として基準電圧V REF−V
cc。The reference voltage V REF-V is based on the ground potential close to
cc.
を供給するようにしたものである。特にLSIの周辺部
にいくつかの基準電圧発生回路が配置されているときは
、電圧降下の殆んど生じない周辺部と電圧降下が最も大
きくなると考えられるLSIの中心部との2箇所で電流
切換型論理回路の接地電位GND 1・GND2を検出
する。It is designed to supply In particular, when several reference voltage generation circuits are placed around the LSI, current flows at two locations: the periphery, where almost no voltage drop occurs, and the center of the LSI, where the voltage drop is expected to be the largest. Detects the ground potentials GND1 and GND2 of the switching type logic circuit.
次に各実施例についてその構成と作動とについて述べる
。Next, the configuration and operation of each embodiment will be described.
まず、第一の実施例について説明する。第1図を見るに
第一の実施例の基準電圧発生回路1は、接地電位検出手
段2と、トランジスタQ6〜Q8・抵抗R4〜R6から
なり検出された接地電位を処理する部分と、トランジス
タQsA−Q5a−Q+、と抵抗R7A−R7Bからな
る基準電圧を出力する部分とで構成されている。First, a first example will be described. Referring to FIG. 1, the reference voltage generating circuit 1 of the first embodiment includes a ground potential detection means 2, a portion for processing the detected ground potential consisting of transistors Q6 to Q8 and resistors R4 to R6, and a transistor QsA. -Q5a-Q+, and a part that outputs a reference voltage consisting of resistors R7A-R7B.
以下これの作動について述べる。まず接地電位G N
D 1・GND2が同電位と仮定すると、接地電位を比
較するトランジスタQ6 ・Q7のベース電位が全く等
しくなり、トランジスタQ4 ・Q8の電流を等しく、
また抵抗R4・R5の値を抵抗R+ −Rzの半分に
設定すると、基準電圧VBpは内部論理振幅の中央に設
定される。次にLSI内部の論理回路の接地電位GND
が、LSI内部の配線抵抗に起因して低下した場合を考
える。The operation of this will be described below. First, the ground potential G N
Assuming that D1 and GND2 are at the same potential, the base potentials of transistors Q6 and Q7 that compare the ground potentials will be completely equal, and the currents of transistors Q4 and Q8 will be equal.
Further, when the values of the resistors R4 and R5 are set to half of the resistor R+ -Rz, the reference voltage VBp is set to the center of the internal logic amplitude. Next, the ground potential GND of the logic circuit inside the LSI
Consider a case where the resistance decreases due to wiring resistance inside the LSI.
この場合、接地電位GND2をLSI内部の接地電圧G
NDに追従して変化するような点に設定すると、接地電
位GNDの低下量に従って接地電位GND2が下がるの
で、これに比例してトランジスタQ6のベース電位がト
ランジスタQ7のベースに比較して下がり、トランジス
タQ7のコレクタ電流の増加すなわち抵抗R5の両端電
圧が増大し、接地電位GNDの低下に応じて基準電圧V
REFの電位を低下せしめる。従って接地電位GNDの
低下にもかかわらず、常に基準電圧VREFが論理振幅
の中央となるよう自動的に補正され°る。一方トランジ
スタQ6のコレクタ電流は逆に減少するため抵抗R4の
両端電位は減少し基準電′圧VC5の電位が増加して、
論理振幅を増加せしめ、基準電圧VREPの低下に起因
するノイズマージンの減少を補う方向に作用する。In this case, the ground potential GND2 is set to the ground voltage G inside the LSI.
If the ground potential GND2 is set to a point that changes according to the ground potential GND, the base potential of the transistor Q6 decreases in proportion to the amount of decrease in the ground potential GND, and the base potential of the transistor Q6 decreases in proportion to the base potential of the transistor Q7. The collector current of Q7 increases, that is, the voltage across resistor R5 increases, and as the ground potential GND decreases, the reference voltage V
The potential of REF is lowered. Therefore, despite the drop in ground potential GND, reference voltage VREF is automatically corrected so as to always be at the center of the logic amplitude. On the other hand, since the collector current of the transistor Q6 decreases, the potential across the resistor R4 decreases, and the potential of the reference voltage VC5 increases.
It increases the logic amplitude and acts in the direction of compensating for the decrease in noise margin caused by the decrease in the reference voltage VREP.
従って当該LSI内部の論理回路の接地電位GNDの低
下に応じて自動的に最適な基準電圧VREF ・VO2
が発生されるため、従来回路では得られない安定な動作
と、十分なノイズマージンが確保される。Therefore, as the ground potential GND of the logic circuit inside the LSI decreases, the optimum reference voltage VREF/VO2 is automatically adjusted.
is generated, ensuring stable operation and sufficient noise margin that cannot be obtained with conventional circuits.
次に第二の実施例について説明する。Next, a second embodiment will be described.
第二の実施例は、第2図を見るに第1図に示す第一の実
施例と比較して基準電圧VBHpの制御のみに着目して
最適化を図った例である。この場合、内部論理振幅に関
しては基準電圧VC52によって定まる一定の値となる
が、制御方法および基準電圧発生回路の構成が簡単にな
るという長所がある。しかし、その反面基準電圧VC3
に関しては基準電位GNDの低下が反映しない短所を有
する。As shown in FIG. 2, the second embodiment is an example in which optimization is focused only on the control of the reference voltage VBHp, compared to the first embodiment shown in FIG. In this case, although the internal logic amplitude is a constant value determined by the reference voltage VC52, it has the advantage that the control method and the configuration of the reference voltage generation circuit are simplified. However, on the other hand, the reference voltage VC3
Regarding this, it has the disadvantage that a decrease in the reference potential GND is not reflected.
次に第三の実施例について説明する。第三の実施例は、
第3図を見るに第1図に示す第一の実施例と比較してV
O2の制御のみに着目して最適化を図った例である。こ
の場合、制御方法および基準電圧発生回路の構成が簡単
になるという長所があるが、基準電圧VREFIは一定
の値となって、これには基準電位GNDの低下が反映し
ない短所を有する。Next, a third embodiment will be described. The third example is
Looking at FIG. 3, compared to the first embodiment shown in FIG.
This is an example of optimization focusing only on O2 control. In this case, there is an advantage that the control method and the configuration of the reference voltage generation circuit are simplified, but there is a disadvantage that the reference voltage VREFI is a constant value and does not reflect the decrease in the reference potential GND.
なお、上記の説明は接地電位について行ったが、他の電
源についても本発明を適用することが可能である。また
、共通の下地ウェハーを使用し配線工程のみで異なる品
種に対応する設計を行ったゲートアレイ等では、使用ゲ
ート数に応じて接地電位に大きな差があるため、本発明
による基準電圧発生回路の適用は特に有効である。Note that although the above explanation has been made regarding the ground potential, the present invention can also be applied to other power sources. In addition, in gate arrays and the like that use a common base wafer and are designed to accommodate different types only in the wiring process, there is a large difference in ground potential depending on the number of gates used. The application is particularly effective.
以上説明したように本発明は、電流切換型論理回路用の
基準電圧発生回路において、基準回路が配置されたLS
I基板周辺部の接地電位と基板中央部の最も電位が低下
した接地電位との電位差を検出し、その電位差に応じて
論理回路部の動作に最適な基準電圧を発生する基準電圧
発生回路が提供されることに°より、基板内部の接地電
位差の大小にかかわらず常に安定な動作マージンを有す
る論理LSIを構成できるという効果がある。As explained above, the present invention provides a reference voltage generation circuit for a current switching type logic circuit, in which a reference circuit is arranged.
Provides a reference voltage generation circuit that detects the potential difference between the ground potential at the periphery of the I-board and the ground potential at the center of the board, where the potential has dropped the most, and generates the optimal reference voltage for the operation of the logic circuit section according to the potential difference. By doing so, it is possible to construct a logic LSI that always has a stable operating margin regardless of the magnitude of the ground potential difference inside the substrate.
の構成を示す回路図、第4図は従来の技術による基準電
圧発生回路を含む回路図。FIG. 4 is a circuit diagram including a reference voltage generating circuit according to the prior art.
1・IA・IB・IC・・・基準電圧発生回路、2・・
・接地電位検出手段、GND −GND 1・GND2
・・・接地電位、VIE・・・電源電圧、VREF ’
VREFI・■o5・Vosl・■cs2・・・基準
電圧、1.−I2・・・入力端子、P、−P2・・・出
力端子。1.IA.IB.IC...Reference voltage generation circuit, 2..
・Ground potential detection means, GND -GND 1/GND2
...Ground potential, VIE...Power supply voltage, VREF'
VREFI・■o5・Vosl・■cs2...Reference voltage, 1. -I2...input terminal, P, -P2...output terminal.
Qリ トQ list
Claims (1)
圧発生回路おいて、前記電流切換型論理回路を搭載した
集積回路基板上の接地電位の分布を検出しその電位差に
応じて前記電流切換型論理回路の基準電圧を供給する接
地電位検出手段を備えてなることを特徴とする基準電圧
発生回路。In a reference voltage generation circuit that supplies a reference voltage necessary for a current switching type logic circuit, the distribution of the ground potential on an integrated circuit board on which the current switching type logic circuit is mounted is detected, and the current switching type A reference voltage generation circuit comprising ground potential detection means for supplying a reference voltage to a logic circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62020913A JPS63187915A (en) | 1987-01-30 | 1987-01-30 | Reference voltage generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62020913A JPS63187915A (en) | 1987-01-30 | 1987-01-30 | Reference voltage generating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63187915A true JPS63187915A (en) | 1988-08-03 |
Family
ID=12040462
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62020913A Pending JPS63187915A (en) | 1987-01-30 | 1987-01-30 | Reference voltage generating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63187915A (en) |
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1987
- 1987-01-30 JP JP62020913A patent/JPS63187915A/en active Pending
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