JPS63187835A - Decentralized time division multiplexing system - Google Patents

Abstract

PURPOSE:To reduce jitter and delay and to simplify the constitution of a slave node by providing a means extracting a clock component from a data recovered and relayed by a main node and a reception/transmission means to the slave node, and providing a means re-editing a transmission frame of the slave node, and sending the result to the main node in a loop form LAN. CONSTITUTION:A timing extraction means C of each slave node branches and inputs a recovered relay data from the main node to extract a clock component. A reception input means D fetches a data addressed to its own node from the said data. A transmission output means E sends a transmission signal in a time slot of its own node synchronously with the timing extracted by the means C. A frame transmission means F of the main node re-edits the transmission frame in each incoming slave node transmission signal and sends the result synchronously with the clock of the circulated recovered relay data. As the result, the system jitter in the transmission signal is reduced and the delay in the system is decreased. Moreover, the switching control of the transmission/ reception timing in each slave node or the like is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an improvement in a distributed time division multiplexing system forming a loop local area network.

(Prior Art) Conventionally, this type of system has a master node 3 connected to a digital line 1 via an II terminal 2, and a system connected to the master node 3 via a local line 4, as shown in FIG. It is composed of a plurality of slave nodes 5 connected in a loop. Among these, first, the master node 3
The time division multiplexed data received by In! is regenerated and relayed and sent to the local line 4. After resynchronizing the transmission data that has arrived from each slave node 5 via the terminal device f2, the transmission data is sent to the digital circuit 111 via the terminal device f2. On the other hand, the data transmitting/receiving section of each slave node 5 is configured as shown in FIG.

That is, the regenerative relay data sent from the master node 3 via the local circuit 814 is amplified by the reception amplifier 51, the clock is extracted by the timing extraction circuit 52, and then the serial
Introduced into parallel conversion shift register (S/P) 53,
Here, serial data is converted into parallel data in synchronization with the extraction clock, and this parallel data is introduced into the node body as a reception signal. Further, the transmission signal output from the node main body is converted from parallel data to serial data by a parallel/serial conversion shift register (P/5) 54 in synchronization with the extraction clock, and then introduced into a switching circuit (SW) 55. This switching circuit 55
By appropriately switching the timing 1lJt [1 circuit 56 according to the switching instruction, the above transmission data and the above S/P5
3 and the received data shifted and output from 881 (
BitSeQuenCeIndependent)
After encoding, the signal is amplified by a transmission amplifier 58 and sent to the private line 4. Note that 6 is a communication terminal device such as a facsimile@direct connected to the slave node 5.

With such a configuration, data arriving via the digital line 1 can be distributed to the corresponding slave nodes 5, and data sent from each slave node 5 can be time-division multiplexed and sent to the digital line 1. Can be sent.

However, such conventional systems have the following problems.

■ Since each slave node 5 regenerates a clock from the regenerative relay data and sends out a transmission signal in synchronization with this regenerated clock, the jitter at each slave node 5 accumulates and becomes large system jitter. When master node 2 attempts to send out the above transmission signal in synchronization with the clock regenerated from digital line 1, a large-capacity elastic buffer is used to absorb the system jitter? Is required.

■ Since the regenerative relay data that has arrived via the private line 4 at each slave node 5 is stored once in the S/P 53 and then sent to the next slave node 5 or master node 2, there is a delay at each slave node 5. occurs, increasing the delay of the entire system.

- It is necessary for each slave node to have all the circuits shown in FIG. 5, which makes the circuit complicated and expensive.

(Problems to be Solved by the Invention) As described above, the conventional system has large system jitter and delay, and has a large configuration. However, the present invention focuses on this problem and provides a distributed timer system that reduces system jitter and delay, reduces the burden on the master node, and simplifies the configuration of each slave node. It attempts to provide a division multiplexing system.

[Structure of the Invention] (Means for Solving Problems) The present invention, as shown in FIG. It consists of an uplink line B that reaches the master node via
timing extraction means C for branching inputting the regenerative relay data sent from the master node to the downlink A, and extracting a clock component; A reception input means that takes in the corresponding data as a reception signal,
a transmission output means E for transmitting a transmission signal to the uplink B in the time slot of its own node in synchronization with the timing extracted by the timing extraction means C; A means F@ is provided for reorganizing the transmission frame of the arriving transmission signal from each slave node in synchronization with the clock of the regenerative relay data that has made a round through the downlink A, and sending it out to the digital line.

(Function) As a result, the regenerative relay data sent from the master node to the private line will go around without passing through each slave node, so each slave node will receive the transmission signal using the same clock sent from the master node. Therefore, the system jitter of the transmitted signal can be significantly reduced. In addition, the delay that occurs in the regenerative relay data is only the transmission delay of the downlink A, thereby making the system delay extremely small. Furthermore, since switching control of transmission/reception timing, etc., is not required in each slave node, the circuit configuration of the slave node is simplified and inexpensive.

<Embodiment> FIG. 2 shows the configuration of a distributed time division multiplexing system in an embodiment of the present invention.

In this figure, the same parts as those in FIG. 4 are given the same reference numerals and detailed explanations will be omitted.

This system has, as a private line, a down line 41 that goes from the master node 30 to each slave node 50 and returns to the mask node 3Q, and an up line 42 that runs through each slave node 50 to the master node 3o. , each slave node 50 is multi-drop connected to these downlinks 41 and uplinks 42.

Incidentally, the data transmitting/receiving section of each slave node 50 is configured as shown in FIG. 3. In other words, the regenerative relay data that arrives from the master node 30 on the downlink 41 is transmitted down! ! The signal is branched from 41 and introduced into a receiving amplifier 51, and after being amplified by this receiving amplifier 51, a timing extraction circuit 52 extracts a clock. Based on the extracted clock, the timing control circuit 56 generates a timing signal representing the time slot of the own node, and according to this timing signal, the serial/parallel conversion shift register (S/P) 53 selects the time slot of the own node among the regenerated relay data. The data is converted from serial data to parallel data and introduced into the slave node body as a received signal.

On the other hand, the transmission signal output from the slave node main body is shifted into the parallel/serial conversion shift register (P/5) 54 in synchronization with the extraction clock in the time slot of the own node specified by the timing control circuit 56. , this P/S 54 converts parallel data into serial data. Then, the transmission signal converted into serial data is amplified by the transmission amplifier 58 and then sent to the uplink 42.

Incidentally, at this time, the transmission amplifier 58 is connected to the timing control circuit 5.
6, the slave node is set to a high impedance state in timeslots other than its own time slot, thereby preventing interference with the transmission operations of other slave nodes.

On the other hand, the master node 30 has frame receiving means and frame transmitting means. First of all, the frame receiving means digitally reproduces received data that has arrived via the digital line 1 and is received by the terminating device 2, and sends it to the downlink 41 as reproduced relay data. In addition, the frame transmission means is
Transmission signals arriving from each slave node 50 via the uplink 42 are input in synchronization with the clock of the regenerative relay data that has made a round via the downlink 41, thereby forming a transmission frame and transmitting it digitally via the termination bag M2. Send to line 1.

With such a configuration, when regenerative relay data is sent from the master node 3° to the downlink 41, this regenerative relay data is branched at the connection point of each slave node 5° and introduced to each slave node 50. Ru. Then, each slave node 50 receives data corresponding to its own time slot as a received signal in synchronization with the clock extracted from the regenerative relay data. On the other hand, the transmission signal generated by each slave node 50 is transmitted upstream 142 in synchronization with a clock extracted from regenerative relay data according to a time slot set in advance for each node.
sent to. These transmission signals are input to the master node 30 in synchronization with the clock of the regenerative relay data that has made a round on the downlink 41, and are sent out to the digital line 1 as a transmission frame.

That is, in this embodiment, the regenerative relay data sent from the master node 30 does not pass through each slave node 50 via the downlink 41;
0, it will go around as it is without being replayed and relayed. Therefore, the delay that the regenerative relay data undergoes during transmission is only the transmission delay of the downlink 41, and as a result, the system delay becomes extremely small. Furthermore, each slave node 50 extracts a clock from the regenerative relay data sent from the master node 3°, that is, from the regenerative relay data that has not been affected by each slave node 50, and synchronizes with this clock. Since data is received and transmitted, no jitter is accumulated and the system jitter is extremely small. Furthermore, in this embodiment, each slave node 50 sends only a transmission signal, so a conventional switching circuit or the like is not required, and as a result, the circuit configuration of each slave node 50 can be simplified. Can be done.

In addition, since the regenerated relay data goes around without passing through each slave node 50, even if a failure occurs in an intermediate slave node and transmission cannot be performed, other slave nodes can continue sending and receiving data. This makes it possible to reduce the occurrence of system downtime.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and includes, for example, the configuration of the timing extraction means, reception input means, and transmission output means of the slave node, the configuration of the frame reception means and frame transmission means of the master node, and the configuration of the frame reception means and frame transmission means of the slave node. The number etc. can also be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, a private line is divided into a down line from the master node to the master node via each slave node, and an up line from the master node to the master node via only each slave node. and timing extraction means for branching and inputting the regenerative relay data sent from the master node to the downlink line from the downlink line to extract a clock component, and the regenerative relay data inputted in the branching line. A reception input means takes in data corresponding to the time slot of the own node as a received signal, and a transmission signal is sent to the uplink in the time slot of the own node in synchronization with the timing extracted by the timing extraction means. A transmission output means is provided, and the master node reorganizes the transmission frame in synchronization with the clock of the regenerative relay data that has made a round of the transmission signal from each slave node that has arrived via the uplink via the downlink, and transfers it to the digital line. By providing a means for sending, it is possible to provide a distributed time division multiplexing system that can reduce system jitter and delay, reduce the burden on the master node, and simplify the configuration of each slave node.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing the configuration of a distributed time division multiplexing system according to the present invention, FIG. 2 is a schematic configuration diagram of a distributed time division multiplexing system according to an embodiment of the present invention, and FIG. A circuit block diagram showing the configuration of the data transmission/reception unit of the slave node in the system. Figure 4 is a schematic configuration diagram of a conventional distributed time division multiplexing system. Figure 5 shows the configuration of the data transmission/reception unit of the slave node in the system. It is a circuit block diagram showing. A... Downlink, B... Uplink, C... Timing extraction means, D... Reception input means, E... Transmission output means, F... Frame transmission means, 1... Digital line, 2... Terminal device, 30... Master node, 4
DESCRIPTION OF SYMBOLS 1... Downlink, 42... Uplink, 50... Slave node, 51... Receiving amplifier, 52... Timing extraction circuit, 53... Serial/parallel conversion shift register (S/P ), 54... Parallel/serial conversion shift register (P/S), 56... Timing control circuit, 58... Transmission amplifier.

Claims (1)

[Claims] In a distributed time division multiplexing system consisting of a master node connected to a digital line and a plurality of slave nodes connected to the master node in a loop via a local line, the local line is connected from the master node to each slave node. It consists of a downlink that returns to the master node via a slave node, and an uplink that goes only through each slave node to the master node, and the regenerative relay data transmitted from the master node to the downlink is transmitted to each slave node. timing extracting means for inputting a branched signal from the downlink to extract a clock component; a receiving input means for inputting as a received signal data corresponding to the time slot of its own node from among the regenerated relay data inputted for the branched input; a transmission output means for transmitting the data to the uplink in its own node's time slot in synchronization with the timing extracted by the timing extraction means, and each slave node that has arrived at the master node via the uplink. 1. A distributed time division multiplexing system comprising means for rearranging a transmission frame and sending it out to the digital line in synchronization with a clock of regenerative relay data that has passed through a downlink.