JPS63187494A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease the flat area of a memory cell by using two bit lines in contact with the memory cell and one bit line split into two not is contact with each and providing a stray capacitance balance means balancing the stray capacitance of the bit lines. CONSTITUTION:Two bit lines 9a, 9b in contact with a memory cell at an area 10 by 2-bit in the direction of a word line 2 of the memory cell array and bit lines 8a, 8b not in contact with the memory cell exist. A capacitance 12 having the same capacitance as the stray capacitance of the bit line 8a is connected in parallel with the connection terminal of the bit line 9a in contact with the memory cell in two input terminals of a sense amplifier 3a. Then a capacitor 11 having the same capacitance as the stray capacitance of the bit line 9a in contact with the memory call is connected in parallel with the memory cell to the connection terminal of the bit lie 8a split into two and not contact with the memory cell to balance the stray capacitance. Thus, noise immunity is provided and the pitch of the sense amplifiers is a pitch for 2-bit of the memory cell, then the memory cell area is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application J] The present invention relates to a semiconductor memory device, and particularly to a memory cell array configuration of a semiconductor device.

(Prior Art) FIGS. 4 and 5 are configuration diagrams showing an example of a memory cell array of a conventional T two-conductor memory device.
FIG. 5 is a block diagram of a memory cell array having a folded bit line configuration disclosed in Japanese Patent Application Laid-Open No. 51-74535. FIG. 5 is a plan view of the memory cell shown in FIG. 4.

In the figure, 1 is the bit line, la, lb, lc, ld.

Ie, If, Ig, lh are each bit line, 2 is a word line,
2a, 2b, 2c, 2d, 2e, 2f.

2g, 2h are each word line, 3 is a sense amplifier, 3a, 3
b, 3c, and 3d are respective sense amplifiers, 4 is a channel portion of a transfer gate, 5 is a contact hole, 6 is a memory cell region for one bit, and 7 is a capacitor for information charge #iM.

Next, the operation of this conventional semiconductor memory device will be explained with reference to FIGS. 4 and 5.

The information charge N product capacitor 7 of the memory cell is charged to a power supply potential or a ground potential, and stores information "1" or "0" depending on which potential it is charged to.

When extracting the information stored in this memory cell,
First, the pin 11 is charged to half the power supply potential. Next, depending on the address signal, for example, only the word line 2b is changed to a high potential.

The channel portion 4 of the transfer gate becomes conductive, and the capacitor 7 for storing information charges in the memory cell is connected to the bit lines 1b, ld, if, and Ih. At this time, bit lines 1b, ld, if.

Of Ih, the potential of the bit line connected to the capacitor charged to the power supply potential changes to a higher potential than half of the potential of the power supply, and the potential of the bit line connected to the capacitor charged to the ground potential changes to Electric 'f! The potential is lower than half of the X potential, but the bit line! a, lc.

The potentials of le and Ig remain half of the potential of #.

Therefore, after selecting word line 2b, bit lines lb, ld,
Whether the potential of if, lh has risen or fallen from half of the power supply potential is determined by the bit lines 1a, lc whose potential is half the power supply potential.
, le, Ig, and sense amplifiers 3a, 3b, 3c, 3d
This result can be used to determine the information stored in the memory cell.

Further, for example, when the word line 2C is selected, the potentials of the bit lines 1a, lc, le, and Ig change from half of the power supply potential, and the potentials of the bit lines 1a, lc, le, and Ig change from half of the power supply potential.

Since the potentials of ld, if, and Ig are kept at half of the power supply potential, the potentials of bit lines 1a, lc, is, and Ig are controlled by sense amplifiers 3a, 3b, 3c, and 3d to
, ld, If, and lh, it is possible to know whether the power supply potential has increased or decreased from the t minute of the power supply potential after word line selection, and similarly to the above, it is possible to determine whether the memory cell has stored data. You can know the information.

They are also concentric when other word lines are selected. In such a folded bit line configuration, for example, two bit lines 1a input to the sense amplifier 3a.

lb extends in the same direction from the sense amplifier 3a, close to the right, so the two bit lines la and 1b are
Since the coupling noise received from the substrate and the cell plate (both not shown) is in phase, there is an advantage that the sense amplifier 3a is less likely to malfunction due to noise. The same is true for other sense amplifiers. Furthermore, since the pitch of each sense amplifier is equal to the pitch of two bits of the memory cell 6, there is an advantage that the design rules for the sense amplifier 3 are relaxed.

However, in such a conventional semiconductor memory device with a folded bit line configuration, as shown in FIG. 5, it is necessary to provide two word lines 2 in a memory cell area 6 for one bit. In order to reduce the planar area and achieve high integration, high resolution is required in photolithography, which has the drawback of being difficult to reduce the planar area.

(Problems to be Solved by the Invention) As described above, in the conventional example, when trying to reduce the surface area of a memory cell, high resolution is required for photolithography, and in order to reduce the planar area, The problem is that it is difficult.

This invention was made in order to solve the problems of the conventional example as described above, and the pitch of the sense amplifier of the conventional example is the pitch of 2 bits of the memory cell, and it is rough? It is an object of the present invention to obtain a semiconductor memory device in which the planar area of memory cells is small while retaining the advantages of a folded bit line structure that is strong against f.

[Means for solving problems]

Therefore, in the present invention, in a semiconductor memory device having a memory cell array and a sense amplifier, in an area for two bits of a memory cell, two bit lines that contact the memory cell and two divided bit lines that do not contact the memory cell are provided. a memory cell array having one bit line arranged in rows and columns, and a sense amplifier arranged on both sides of the memory cell array, the bit being in contact with the memory cell; One of the two divided bit lines that does not contact the memory cell is input to the sense amplifier disposed on one side of the memory cell array, and one of the two bit lines that is not in contact with the memory cell is connected to the other bit line that is in contact with the memory cell. , the other of the two divided bit lines not in contact with the memory cell is input to the sense amplifier disposed on the other side of the memory cell array, and the two 0η lines input to the sense amplifier
The above object is achieved by providing a stray capacitance balancing means for balancing the floating capacitance of the bit line.

(Function) In the present invention, the t-conductor/memory device that makes up the memory cell array and the sense amplifier 41 has two bit lines in an area corresponding to two bits of the memory cell, one in contact with the memory cell and one not in contact with the memory cell. One of the two bit lines that contacts the memory cell, one of the divided bit lines that does not contact the memory cell, and two bit lines that contact the memory cell. The other of the bit lines and the other of the bit lines that do not contact the divided memory cells are inputted as complementary bit lines to the sense amplifiers on both sides of the memory cell array, respectively, so that the folded bit of the conventional example is The memory stored in the memory cell is read by a concentric operation as in the case of the line configuration.

〔Example〕

Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 is an explanatory diagram of the structure of a memory cell array of a conductive memory device according to embodiments of the present invention, and FIG. 2 is an explanatory diagram of the structure of memory cells constituting the memory cell array of FIG. Figure <ay is a plan view of a memory cell having three bit lines in a memory cell area for two bits, the second
Figure (b) is a perspective view of Figure 2 (a) seen from the arrow;
Figure (C) is a sectional view of Figure 1 taken in the x-x' direction.

FIG. 3 is an explanatory diagram of the configuration of a memory cell array of a semiconductor memory device according to another embodiment of the present invention, FIG. 4 is an explanatory diagram of the configuration of a conventional semiconductor memory device, and FIG. 5 is a configuration explanatory diagram of a memory cell array of a fourth IA. FIG. 2 is a structural explanatory diagram of a memory cell.

In FIG. 1, 2 is a word line, 3 is a sense amplifier, 4 is a channel part of a transfer gate, 5 is a contact hole, and 6
is a memory cell area for one bit, 8 is a bit line that does not contact a memory cell, 8a to 8h is each bit line that does not contact a memory cell, 9 is a bit line that is in contact with a memory cell, 9a to 9h is a contact with a memory cell Each bit line 10 is a memory cell array in which memory cells for 2 bits are arranged in parallel! ! is the same as bit line 9
12 is a capacitor with the same capacitance as the bit line 8. In Figure 2, 13 is the first layer of polysilicon, 14 is an n-type diffusion layer, 15 is a capacitor insulation sample, and 16 is a flat surface. 16a is a sidewall isolation oxide film, 16b is a trench bottom isolation oxide film, and 17 is a trench isolation region. In FIG. 3, 3a to 3t are sense amplifiers, and 8a to 8p are memory cells. The bit lines 9a to 9p that do not make contact are the bit lines that make contact with the memory cells, and the bit lines 8, 9, . . . 9 in FIG. The - section of capacity 11.12 is omitted.

In each figure, the same or equivalent components as in the prior art described above are represented by the same reference numerals, and redundant explanation will be omitted.

As shown in the explanatory diagram of the memory cell array configuration in FIG. 1, the memory cell array of this embodiment has two bits 1Q9a and 9b in contact with the memory cell and two bits 1Q9a and 9b in contact with the memory cell in an area corresponding to two bits of the memory cell. Memory cells each having one bit line 8a, 8b divided into two are arranged in a matrix, and sense amplifiers 3 are arranged on both sides of the memory cells.
The bit line 8a, which is divided into two, with one bit line fi9a in contact with the memory cell and the other bit line 8a not in contact with the memory cell, is connected to the sense amplifier 3a disposed in one side of the memory cell array 10. The other bit line 8 which is input and contacts the memory cell, and the other bit line 8 which is not in contact with the memory cell, is configured to input to the sense amplifier 3f disposed on the other side of the b memory cell array 10. There is.

The memory cell 6 in FIG. 2 consists of an n-type diffusion layer 14 on the side surface of the groove dug in the substrate in FIG. , and the channel portion 4 of the transfer gate, it operates as an ITrlc memory cell.

As shown in FIG. 2(a), this memory cell 6 only needs to have an area for three bit lines to pass through the memory cell area for two bits.

As mentioned above, the word line 2 of the memory cell array in FIG.
2 bits in contact with the memory cell in the area 10 corresponding to 2 bits in the direction of ! ! i19a.

9b and two bit lines 8a and 8b that do not contact the memory cells.

Therefore, bit line 9a and bit line 8a, and bit line 8b and bit line 9b serve as complementary bit lines and sense amplifiers 3a on both sides of the memory cell array.

3f, the information stored in the memory cells can be read out concentrically with the conventional folded bit line configuration shown in FIG.

Next, a stray capacitance ζl balancing means for balancing the stray capacitances of the two bit lines 9a and 88 input to the sense amplifier 3a, for example, will be described.

Since the two bit lines 9a and 8a have different lengths, the stray capacitances of the bit lines are different. Therefore, in order to balance the two bit lines 9a and 88, of the two input terminals of the sense amplifier 3a, the connection terminal of the bit line 9a that contacts the memory cell is divided into two that do not contact the memory cell. A human-sized capacitance 12, which is the same as the stray capacitance of bit 1Is8a, is connected in parallel, and the connection terminal of the divided bit line 8a, which is not in contact with the memory cell, has the same size as the stray capacitance of the bit line 9a, which is in contact with the memory cell. By connecting the capacitors 11 in parallel, the stray capacitance can be balanced.

Furthermore, instead of the surface capacitance 11.12, the memory cell array can be divided into a plurality of blocks and the bit lines of unselected blocks can be used, as shown in FIG. For example, the bit lines 8b and 9j are connected to one input terminal of the sense amplifier 3e, and the bit lines 9b and 8j are connected to the other input terminal, so that the load capacitance of the sense amplifier 3e is well balanced.

As described above, according to this embodiment, in the folded bit line configuration of the conventional example described above, it was necessary to pass two wires through the memory cell area for one bit, but it is possible to It only requires 1.5 wires to be passed through the bit line configuration, has noise resistance similar to the folded bit line configuration, and the pitch of the sense amplifier is the same as the pitch of 2 bits of the memory cell.
The memory cell area can be reduced, and the chip area of the semiconductor memory device can be reduced.

〔Effect of the invention〕

As explained below, according to the present invention, in a semiconductor memory device having a memory cell array and a sense amplifier, two bit lines contacting the memory cell and two bit lines contacting the memory cell are provided in a region corresponding to two bits of the memory cell. It consists of a memory cell array in which memory cells are arranged in rows and columns, and sense amplifiers are arranged on both sides of the memory cell array.
and one of the bit lines in contact with the memory cell;
One of the two divided bit lines that does not make contact with the memory cell is input to a sense amplifier arranged on one side of the memory cell array, and the other bit line that makes contact with the memory cell,
The other half of the divided bit line that does not contact the memory cell is input to the sense amplifier arranged on the other side of the memory cell array, and one stage of stray capacitance balance is used to balance the stray capacitance of the two bit lines input to the sense amplifier. Because of this, the memory cell area can be reduced while maintaining noise resistance, and the chip area of the semiconductor memory device can be reduced.

[Brief explanation of the drawing]

1 is an explanatory diagram of the structure of a memory cell array of a semiconductor memory device according to an embodiment of the present invention; FIG. 2 is an explanatory diagram of the structure of memory cells constituting the memory cell array of FIG. 1; (a) shows 3 bits in the memory cell area for 2 bits.
2(b) is a perspective view of FIG. 2(a) seen from the arrow, and FIG. 2(c) is a plan view of the memory cell that drives the bit line of the book. It is a sectional view partially cut away in the force direction. FIG. 3 is an explanatory diagram of the configuration of a memory cell array r of a single conductor memory device according to another embodiment of the present invention, FIG. 4 is an explanatory diagram of the configuration of a memory cell array of a conventional semiconductor memory device, and FIG. 4 is a structural explanatory diagram of memory cells constituting the memory cell array r of FIG. 4. FIG. 2...-word lines 2a to 2d... each word line 3... sense amplifiers 3a to 3... each sense amplifier 4-------- of the trough gate. Channel section 5--
---Contact hole

Claims (3)

[Claims] (1) In a semiconductor memory device having a memory cell array and sense-up, in the area for 2 bits of the memory cell,
A memory cell array in which the memory cells are arranged in a matrix, the memory cells having two bit lines in contact with the memory cells and one bit line divided into two not in contact with the memory cells, and both sides of the memory cell array. One of the bit lines in contact with the memory cell and one of the two divided bit lines not in contact with the memory cell are connected to the sense amplifier disposed in one of the memory cell arrays. The other of the bit lines input to the sense amplifier and in contact with the memory cell, and the other of the two divided bit lines not in contact with the memory cell are input to the sense amplifier disposed in the other side of the memory cell array, A semiconductor memory device comprising a stray capacitance balancing means for balancing stray capacitances of the two bit lines input to the sense amplifier. (2) The stray capacitance balancing means connects the stray capacitance of the two-part bit line that does not contact the memory cell to the connection terminal of the bit line that contacts the memory cell among the two input terminals of the sense amplifier. The means connects capacitors of the same size, and connects a capacitor of the same size as a stray capacitance of the bit line that contacts the memory cell to a connection terminal of the two-part bit line that does not contact the memory cell. A semiconductor memory device according to claim 1, characterized in that: (3) The stray capacitance balancing means is a means for dividing the memory cell array into a plurality of blocks and utilizing the bit lines of unselected blocks. Semiconductor storage device.