JPS63186597A - Driving circuit for stepping motor - Google Patents

Abstract

PURPOSE:To realize a mini-step drive by varying the duty ratio of pulse signals for phases at a predetermined period. CONSTITUTION:A first clock generator 5 applies a clock signal CLKH of relatively high frequency to a first counter 6, and a counter 6 applies its count CNTH as the lower bits of an address signal to an ROM 7. A second clock generator 8 applies a clock signal CLKL of relatively lower frequency corresponding to the rotating speed of a stepping motor to a second counter 9, and the counter 9 applies its count CNTL as the higher bits of the address signal to the ROM 7. The duty ratios of phase pulse signals D1-D4 from the ROM 7 are varied at a predetermined period, and varied at a resolution of the same degree as that in which the average level is obtained as data of several bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a stepping motor drive circuit, and is particularly concerned with a stepping motor drive circuit capable of controlling rotation with high resolution using a particularly simple configuration.

(Prior Art) A conventional four-phase stepping motor drive circuit employing a mini-step drive method is shown in FIG. 4. In this circuit, a clock signal CLK outputted from a clock generation circuit 1 is counted by a counter 2, and the count (direct CNT is stored in a ROM (read o
nly memory) 3:i output address data.

ROM 3 stores 1 Aikawa data D in a memory area corresponding to 4n (n = 0.1.2-”) address data.
Store φ1 and similarly, 4n +1.4n +2゜4n
Data for 2 phases, 3 phases, and 4 phases Dφ2. is stored in the memory area corresponding to the +3 address data. Dφ3. Dφ4 is stored, and the 1st to 4th phase data Dφ1 to Dφ4 are sequentially switched in accordance with the increment (or decrement) of the force C count value and output to the latch circuits 11 to 41.

Each of the latch circuits 11 to 41 is supplied with latch command signals LATI to LΔT4 from the timing control circuit 4 which is supplied with a clock signal 0LK and a count value CNT.
Each of the latch circuits 11 to 41 latches 1-phase to 4-phase data Dφ1 to Dφ4, respectively. The data Dφ1 to Dφ latched in the latch circuits 11 to 41 in this way
4 is converted into analog signals Δφ1 to Δφ4 in the corresponding digital/analog conversion circuits 12 to 42 and applied to the corresponding current drivers 13 to 43, and the coils of each phase (
(not shown).

Here, each phase open data Dφ stored in ROM3
1 to Dφ4 are 1/2 period T/ as shown in FIG.
2, and the next 1/2 period T
/2 has a waveform that takes a zero level, and has a phase difference of 1/4 cycle between data Dφ1 to Dφ4 of each phase open.

Thus, according to this conventional circuit, the stepping motor can be operated more smoothly than when outputting rectangular wave data.
That is, compared to the normal two-phase excitation method, the example shown in FIG. 5 can rotate with eight times the resolution.

(Problem to be solved by the invention) However, in this conventional circuit, latch circuits and digital/analog conversion circuits are required for the number of phases, and when the number of phases is increased, the overall drawing becomes larger and more complicated. was.

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide a stepping motor drive circuit with a simple configuration that can realize mini-step drive.

[Structure of the invention]

(Means for Solving the Problem) In order to solve this problem, the present invention provides a driver that drives a multi-phase stepping motor with each phase open, a duty ratio that changes at a predetermined period, and a driver that drives a multi-phase stepping motor at a predetermined rate. and drive signal generating means for supplying pulse signals for each phase with a phase difference of 41 to the corresponding drivers.

(Function) By changing the duty ratio of each phase open pulse signal D1 to D4 at a predetermined period, the average level can be changed with the same resolution as that obtained with several bits of data, and mini-step drive can be realized.

In this case, since the drive signals handled are 1-pit pulse signals D1 to D4, the configuration is simplified compared to a conventional circuit that can realize mini-step drive.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In FIG. 1, a first clock generation circuit 5 provides a clock signal CL K ]-1 of a relatively high frequency (for example, 100 (KHz)) to a first counter 6, and the counter 6 receives its count value CN. T l-1 is given as an address signal for lower bits (Δ0 to A4) to ROM7. Further, the second clock generation circuit 8 supplies a clock signal CLKL of a relatively low frequency (for example, 10 to 500 (H2)) corresponding to the rotational speed of a stepping motor (not shown) to the second counter 9, and 9 sets the count value CNTL to the upper bit (A5
~△+0) as an address signal.

The ROM 7 has an address (A.

Data D1 to D4 are stored in the memory area corresponding to ~A+o).
is stored, and the incoming address signal ADD (CN
TL, CNTH) data D1 to D4 according to
For 1 phase, 2 phase, and 3 phase.

The current is applied to four-phase current drivers 14, 15, 16, and 17 to supply each phase current to the stepping motor.

The counter 9 is reset at predetermined intervals by a reset circuit 10 which outputs a reset signal R8T at the timing when the rotor of the motor completes one revolution in response to the count 1 shift CNTL.

In addition, as the current driver 14.15.16.17,
It has a conversion means for converting pulses having a required duty ratio, which will be described later, constituting the data D1 to D4 supplied from the ROM 7, into an analog voltage signal of a level corresponding to the duty ratio. An example of this configuration is a configuration that controls current to a stepping motor. In this case, the conversion means includes, for example, a clock signal CL whose cut-off frequency is a high frequency.
It can be configured with a filter that is lower than KH and higher than the low frequency clock signal CLKL.

The ROM 7 changes the pulse width at a predetermined period as the address signal 8ADD changes, and the change in the average level corresponds to the fifth pulse width.
Output data D1 to D4 exhibiting similar changes as shown in FIGS. (A) to (D) are stored.

For example, upper bits A5 to A+o of address signal ADD
In the period T+ (Figure 3) where is roooooo-OJ,
During one cycle of lower bit Δo=A5, data D1 is “1”.
”, data D1 to D4 such that D4 becomes “O” are stored in other data D2.

In other words, data D1 is 100% in terms of duty ratio.
and 0% data D2 to D4 are stored.

Therefore, during the period T+ in which the upper bits A5 to AIo are rooooooOJ, the lower bit Ao"-A4 goes through several tens of cycles (for example, 70 cycles), but the duty ratio does not change during that time.
They become 100% and 0%.

Counter 9 increments and upper bits A5 to AI
When O becomes rooooool J, this period T2 (
In Fig. 3), data D+ is the lower bits AO to A.
It is stored so that it becomes "O" only when 4 is rooooOJ, and becomes "1" in other cases. Therefore, during one cycle of the lower bits Δ0 to A4, it becomes "0" for only 1/32 of the period, and the duty ratio becomes 31/32. On the other hand, data D2 is the lower bit △o''-A
Since 4 becomes "1" only when [00000J], the duty ratio becomes 1/32. In other words, upper bit A5~
Data D1 in jJJ interval T2 where A1o takes rooooolJ (lower bit Ao = A4 is repeated several tens of times)
The average level of data D2 decreases by 1/32, whereas the average level of data D2 increases by 1/32. Note that the average level of data D3 and D4 is also O at this point.

Furthermore, the counter 9 increments and the upper bit A
5~When AIo becomes rooooloJ, this period T3
In the data D1, the data D1 is stored so that it becomes "0" only when the lower bits AO to A4 are rooooOJ and roooolJ, and becomes "1" at other times. On the other hand, data D2 is lower bit A
It is stored so that it becomes "1" only when O to A4 are rooooOJ and roooolJ. Therefore, the duty ratio of data D1 is 30/32, the duty ratio of data D2 is 2/32, data D1 further reduces the average level by 1/32, and data D2 reduces the average level by 1/32 (1( add more.

Thereafter, the average level can be changed in the same manner as shown in FIG. 5 by similarly storing data D+ to D4 so as to take the duty ratio corresponding to the upper bits A5 to Ago. Note that the lower bits Ao to Δ4 define the minimum unit of change in the average level.

Therefore, according to the above embodiment, the ROM 7 outputs only 1-bit data D1 to D4, but its pulse width (i.e., duty ratio, average level) is changed depending on the rotor position. Therefore, the rotation can be controlled with a resolution (25) corresponding to the number of lower bits (5).

Furthermore, since the digital/analog conversion circuit and latch circuit required in conventional circuits are not required, the configuration can be significantly simplified.

In the above-described embodiments, the motor has four phases, but the present invention can also be applied to a motor having multiple phases. In addition, as a storage means, the RO shown in the embodiment is used.
Random access m
emory) etc. can also be used. Furthermore, the present invention can be applied to various stepping motors such as PM type, VR type, and hybrid type. Further, in the above-described embodiments, a stepping motor driven by a constant current is shown, but the present invention can also be applied to a stepping motor driven by a constant voltage. Furthermore, the configuration of the generating circuit is not limited to one using a ROM as long as it can generate a pulse signal as shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, since the pulse width of data is modulated and supplied to the driver in stages, it is possible to obtain a stepping motor drive circuit capable of mini-step driving with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the storage contents of the ROM 7, FIG. 3 is a timing chart of each part of the embodiment, and FIG. 4 is a block diagram showing the conventional technology. FIG. 5 is a route map for explaining the contents stored in the ROM 3. 5.8... Clock generation circuit, 6, 9... Counter, 7... ROM, 10... Reset circuit, 14-1
7...Current driver.

Claims (2)

[Claims] (1) A driver for each phase that drives a multiphase stepping motor, and a drive signal that supplies a pulse signal for each phase to the corresponding driver whose duty ratio changes at a predetermined period and has a predetermined phase difference from each other. 1. A stepping motor drive circuit comprising: generating means. (2) The driver converts the pulse signal supplied from the drive signal generating means into an analog voltage signal with a level corresponding to its duty ratio, and drives the polyphase stepping motor using this analog voltage signal. A stepping motor drive circuit according to claim 1.