JPS63186295A - Driving circuit for display panel - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display drive circuit for a display panel such as a liquid crystal television that displays gradation.

[Conventional technology]

In order to display not only characters and simple figures but also complex and beautiful images on the display panel mentioned above, it is necessary to change the black and white and color brightness of each pixel. It is selected in about 16 stages. In many display panels, this brightness control is done by keeping the drive voltage constant and controlling the amount of time during which that voltage is applied during the display time of each pixel, rather than by changing the drive voltage for each pixel. FIG. 3 shows a typical conventional drive circuit of the so-called drive time variable control type, in which it is convenient to change the drive time.

At the top of the figure, a small portion of the display panel 100 and several hunting pixels 101 are schematically shown.
The pixels are distributed quadratically and are driven via vertical and horizontal drive lines in a known manner. The drive signal DSL is applied to the vertical drive line.
, DS2, etc. are provided temporally shifted from each other, and the lateral drive lines 81 . H2 etc. are also sequentially switched and selected. 0 The pixel at the intersection of the selected horizontal drive line and the vertical drive line to which the drive signal is applied performs a display operation.
For each drive line in the vertical direction, circuit blocks 11, 12, etc., shown surrounded by dashed lines in the figure, are provided, and each generates drive signals DSL and DS2. This circuit block consists of a shift register 1, a latch circuit 2, and a latch circuit 2 from the bottom of the figure. ANDOR circuit 3. It includes five types of circuits: a voltage conversion circuit 4 and an output circuit 5, and a counter 6 and a decoder circuit 7 are provided in common to the plurality of circuit blocks.

The illustrated circuit is for 16-gradation display, and the gradation for each vertical drive line is specified by 4-bit gradation specification data SD having a value of 0 to 15, so the shift register 1 has 16 gradations. It has a stage configuration, and designated data SD given to the first stage on the left side is sequentially sent to the shift register in each circuit block by a shift pulse SP and stored there. The output commands of drive signals DSL and DS2 for each circuit block 11 and 12 are display command pulses SSI and S
S2 is sequentially given to the four launch circuits 2 of the same parallel configuration in each circuit block, and each latch in the latch circuit 2 receives this, and then outputs the Oll in the corresponding film of the shift register 1.
After reading and latching the bit data of
give to On the other hand, the counter 6 also has a four-stage configuration and the above-mentioned display command 551. Common display command SS in synchronization with SS2 etc.
7 clock pulses are counted immediately after being reset by this. The decoder circuit 7 receives outputs from the four stages of the counter 6, decodes them, converts the four weights into data WDO to -D3, and supplies the data to the AND-OR circuit 3. Figure 4 (al shows the previous display command SS, the same figure (co)
~(c3) show the waveforms of the data signals for these weights.

As can be seen from the figure, weighting is applied to the data signal WDO~[13
has weights of 1, 2, and 4.8 depending on the respective pulse widths.

The AND/OR circuit 3 further ORs the four AND outputs obtained by performing an AND between the corresponding focus data of the specified data S00 to SD3 and the weighted data WDO to -D3 to generate the drive signal 1)S. Then, the drive signal O when the given specified data SD has a value of 5 (・1 + 4)
The waveform of S is shown in FIG. 4 +dl. As can be seen from the figure, this drive signal DS has a waveform in which the data signal WDO with a weight of 1 and the data signal WD2 with a weight of 4 are superimposed. As can be seen from this example, the AND-OR circuit 3 converts the designated data 5I11 into a drive signal port S having a total pulse width proportional to its value.

Of course, this drive signal has a TTL level voltage, but
Since this is insufficient to drive the pixels of the display panel, the voltage of the drive signal DS is amplified several times or more by the voltage conversion circuit 4, and then boosted through the output circuit 5 including an output transistor. Since the 0 pixel 101 etc. output from the circuit block 11 etc. as the drive signal D81 etc. is driven for a time corresponding to the total pulse width of this drive signal DS1, its display brightness is the same as the specified data SD. It will be proportional to the value.

[Problem that the invention seeks to solve]

Figure 4 + (As shown in 11, the value of the specified data SD is 5.
When , two pulses are included in the drive signal DS, and similarly, two pulses are included in the drive signal when the specified data values are 9.10.13 and 15. come. However, when the specified data has a value other than the above,
The number of pulses in the drive signal O3 will be 1. However, when the number of pulses in the drive signal is 1 or 2, even if the pulse width plan, that is, the pixel drive time is as specified, the actual brightness of the pixel display is not necessarily the same. It has become clear that the specified data values are no longer true. The reason for this is that there is a slight time delay in the operation of the voltage conversion circuit 4 and output circuit 5 each time the pulse in the drive signal rises or falls, and the waveform of the output voltage becomes dull. This is thought to be due to the fact that there is a considerable time lag in the blinking of the display relative to the drive signal. As a result, if the number of pulses in the drive signal, that is, the number of rises and falls of the drive signal, differs, the actual display brightness above the pixel will not be proportional to the total time it is driven. . Such problems in display fidelity become more prominent as the area of the display panel becomes larger, the number of pixels included therein increases, and the drive time per pixel becomes shorter.

SUMMARY OF THE INVENTION An object of the present invention is to solve this problem and provide a display panel drive circuit that can display each pixel faithfully to its brightness specification data.

[Means for solving problems]

According to the present invention, the above object is to receive designation data that designates the display brightness of each pixel in the display panel as a multi-bit digital value and output a drive signal having a pulse width corresponding to the designation data. A reference data generation circuit generates reference data that monotonically changes over time with the same number of bits as the specified data to a drive circuit that outputs the same number of bits as the specified data based on a display command, and a reference data generation circuit that compares the specified data and reference data and detects a match when the two match. A coincidence detection circuit that emits a signal and a state switching circuit that is set to one state by a display command and switched to the other state by a coincidence detection signal are provided, and the state output signal of the state switching circuit is made to issue as a drive signal. This is achieved by

[Effect]

As can be seen from the above configuration, the present invention does not use conventional weighting data, but instead uses reference data that monotonically changes over time. Since this reference data need only be data of the same bits as the specified data that simply increases or decreases with time, its generation circuit can be constructed of, for example, an amplifier counter or a down counter. The coincidence detection circuit finds a point in time when the given specified data and this time-varying reference data match and issues a coincidence detection signal.This causes a state switching circuit, such as a frimbflop circuit, to switch states, e.g. Set. When this state switching circuit previously received a display command, it was set to one state (1, for example, the recent state), so the drive signal is caused to rise or fall at the set point above. . Of course, the fall or rise of the corresponding drive signal is synchronized with the start or end of the display time. As long as the reference data is data that simply increases or decreases over time, it matches the specified data only once in each display time, so the drive signal rises or falls only once in the display time. It's fleeting. Therefore, in the case of the present invention, the drive signal always includes one pulse, and its rise and fall occur only once. This eliminates the conventional problem in which the number of pulses in the drive signal varies depending on the value of specified data given, and the above-mentioned problem is solved.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure is a circuit diagram for exciting a display panel drive circuit according to the present invention, and FIG. 2 is a waveform diagram of main signals corresponding thereto. The same parts in FIG. 1 as in the previous FIG. 3 are given the same reference numerals.

In this embodiment as well, the number of gradation display stages is 16, and therefore the designation data so specifying this gradation is 4-bit data having a value of 0 to 15, and as in the conventional case, 0 to 4 in the diagram of shift register 1 with 4 stages
It is assumed that the information is stored in each crotch meat indicated by 3. The latch circuit 2 receives the display command ss as a latch command and latches each focus data in the shift register 1.
In this embodiment, the complementary signal of the designated data SD is given from the latch circuit 2 to the coincidence detection circuit 3o shown above.In FIG. 0, each bit is shown as SDO to SD3.

On the other hand, the reference data generating circuit 20 in this embodiment is composed of a simple up counter 6 having four stages, and immediately after being reset by the display command SS, the counter 6 starts counting clock pulses CP.

Reference data RD output from this reference data generation circuit 20
The outputs of each stage of the counter 6 are output as they are as each bit data RDO to R[13 of the reference data without going through a decoder circuit as in the conventional case, and are applied to the coincidence detection circuit 30. The upper part of Fig. 2 shows this pattern, and Fig. 2(a) shows the display command SS, and Fig. 2(bl) shows the clock pulse CP given to the counter 6. In this embodiment, there are 15 pulses P within the mutual interval of the display command SS which is repeatedly given to the counter 6 as a kind of reset pulse.
Includes O to P14.

Reference data is shown in (co) to (e3) of the same figure! +00~R
[13(7) As can be seen from Figure 0 where the waveform is shown, the reference data RD consisting of these four focus data is
From the value 0 when the counter 6 is reset by the display command SS, it increases monotonically in response to the clock pulse CP and reaches the value 14 immediately before the next display command SS is given.

An exclusive or gate 3 is included in the coincidence detection circuit 30.
These exclusive OR gates each receive each bit of complementary designated data SDO to SD3 and each bit of reference data RDO to RD3, and the values of both bits are When there is a match, print that output as “
0'', the OR gate 32 shown above receives the outputs of these four exclusive OR gates 31,
The output is set to "0" only when all of these four outputs are "0". In other words, the four exclusive OR gates 31 and one OR gate 32 are complementary to the reference data RDO to RD3. The match between the specified data 5DO-3D3 is detected, and when both data completely match, the output of the OR gate 32 becomes "0". It receives a strobe pulse for coincidence detection created by inverting the rOJ.
When a value is taken, the above-mentioned matching detection operation by the OR gate 32 is performed.

The state switching circuit 40 shown above that receives the output of this coincidence detection circuit is one flip-flop circuit consisting of two NAND games) 41 and 42, and the display command S
When S is issued, the Nant gate 42 receives "0" which is inverted by the inverter 9 and is reset. Therefore, at the start of this operation, the Nantes gate 41
The drive signal DS taken from the output of the other side is "0", but the reference data ROO~RD3 increases from the 0 value and fails with the complementary designated data surface "~SD3", and the OR gate 32 of the coincidence detection circuit 30 The output of “0” synchronizes with the strobe pulse.
'', the flip-flop circuit receives this at the Nant gate 41 and is set to ``1'', so that the drive signal DS rises from ``0'' to ``1'' in response.

This situation is shown in FIGS. 2(dO) to (d15).

These represent the waveforms of the drive signals when the value of the designated data SD is O to 15, respectively. Now, if 5 is specified as the value of this specified data SD, the bit data 500 to SD3 will be expressed as rl0IOJ with the least significant bit on the left side, corresponding to FIG. is its complementary bit data 5DO-
We are given r 0101 J which is 3D3. Therefore, the drive signal DS in this case is as shown in (d5) in FIG.
Similarly, as shown in 3), when r 0101 J is reached, it rises from "0" to rlJ. In this way, the drive signal [15] that rises when the reference data RD coincides with the complementary specified data i all rises when the next display command SS is issued and the flip-flop circuit as the state switching circuit 40 is reset. Go down. Therefore, in the drive signal DS in the above example, bits RDO to RD3 of the reference data are r 0
101J, that is, the drive signal Ds in the present invention has a pulse width corresponding to a 5-clock pulse period from when the value of the reference data RD is 10 until the value becomes 14. A pulse width is given that is proportional to the value given as SD.

Note that when the value of O is specified as the specified data SD, the value of the complementary specified data SD becomes 15, and the reference data RD only occurs between 0 and 14, so the one-loss detection circuit 30 detects one loss. Therefore, the drive signal DS in this case is always "0" as shown in FIG.
This is the reason why it is not necessary to generate a value of 15 for . Furthermore, when 15 is given as the designated data SDO value, the corresponding drive signal DS should be made to rise as shown in FIG. 2 (d15) from the time the display command SS is issued. In the example, since the flip-flop circuit serving as the state switching circuit is reset by the complementary signal of the display command SS, the drive signal does not rise in synchronization with the display command SS.

The OR gate 33 provided in the coincidence detection circuit 30 compensates for this point, so that when the specified data SDO value is 15, the bits SDO to SD3 of the complementary specified data are all "0".
It outputs "0" as its output and supplies it to the Nant gate 41 of the flip-flop circuit only when the output is "0", so that the flip-flop circuit is sent regardless of the reference data ROO, and the drive signal O5 becomes as shown in FIG. d15
), it is always rlJ throughout the driving time.

Of course, if the time point at which the flip-flop circuit of the state switching circuit 30 is reset is slightly earlier than the time point at which the counter 6 as the reference data generation circuit is reset, the above Nant gate 33 can be provided in the coincidence detection circuit 30. The point is not necessarily. Furthermore, in the embodiment shown in FIG. 1, the display command SS for resetting the counter 6, the launch command for the latch circuit 2, and the display command SS as a reset command for the flip-flop circuit of the state switching circuit 40 are the same, but the latter is It should be understood that this command should originally be given to each circuit block 10, 11, etc. separately and sequentially, but for the convenience of explaining this embodiment, it is the same as the common display command that should be given to the reference data generation circuit 20. In practical circuits, the strobe pulse as a coincidence detection command to the OR gate 32 in the coincidence detection circuit 30 is not given in the form of a complementary signal of the clock pulse CP, but rather in the form of a different signal No. 18, although it is synchronized with the clock pulse. It is better to

In addition to the embodiments described above, the circuit of the present invention can be implemented in various modified forms.For example, as can be easily seen, the types of gates in the coincidence detection circuit and the state switching circuit are not limited to the embodiments, and the types and The combination should be selected as appropriate.

Of course, the specified data supplied to the coincidence detection circuit does not necessarily have to be in the form of a complementary signal as in the embodiment, and the specified data can be passed to the coincidence detection circuit in its original form depending on the form of the reference data generated in the reference data generation circuit. You may give it to

〔Effect of the invention〕

As explained above, the present invention includes a reference data generation circuit that generates reference data that monotonically changes over time and has the same number of bits as specified data to a display panel drive circuit based on a display command, and a reference data generation circuit that generates reference data that monotonically changes over time and has the same number of bits as specified data, and a A coincidence detection circuit that compares the two and issues a coincidence detection signal when they match, and a state switching circuit that is set to one state by a display command and switched to the other state by the coincidence detection signal are provided, and the state output of the state switching circuit is provided. Since the signal is emitted as a drive signal, there is only one point in time during the drive time for each pixel when the value of the reference data emitted from the reference data generation circuit matches the value of the given specified data. Since the drive signal always contains a single pulse, there are fewer complex effects than before, such as time delays in the operation of the voltage conversion circuit and output circuit, and display delays in the pixels, and the drive signal can be controlled by specified data. The display panel can provide a display that is more faithful to the gradation or brightness. In addition, since the number of pulses included in the drive signal is reduced compared to the conventional one, the voltage conversion circuit or output port in the circuit block is affected by the rapid rise of the pulse.

The amount of noise mainly generated from the road is reduced, and the probability of image display disturbance due to mutual interference between drive circuits is also reduced accordingly. Moreover, since the fall or rise of one pulse in the drive signal can always be synchronized with the end or start of each drive time, the influence of the above mutual interference can be reduced. Furthermore, since switching loss in the voltage conversion circuit and output circuit is reduced by reducing the number of pulses in the drive signal, power consumption can be lowered than in conventional drive circuits.

The effects of the present invention become more pronounced as the area of the display panel becomes larger, the number of pixels therein increases, and the driving time per pixel becomes shorter. It is possible to display a beautiful and clear image on the display panel with less turbulence.

[Brief explanation of the drawing]

Figures 1 and 2 relate to the present invention; Figure 1 is a circuit diagram showing an embodiment of a display panel drive circuit according to the present invention, and Figure 2 is a waveform diagram of main signals in the circuit. . Third
4 and 4 relate to the prior art, FIG. 3 is a block circuit diagram of a typical example of a conventional display panel drive circuit, and FIG. 4 is a waveform diagram of its main signals. , 2: Launch circuit, 3: AND-OR circuit, 4: 1 positive conversion circuit, 5: Output circuit, 6: Counter, 7: Decoder circuit, 8.9: Inverter, 10,1
1,12: ! Circuit block for one pixel including I drive circuit, 20: Reference data generation circuit or counter, 30
; Match detection circuit, 31: Exclusive or gate,
32.33 NOR gate, 40: State switching circuit or flip-flop circuit, 41, 42: NAN. Gate, 100: Display panel, 1018 pixels, CP:
Clock pulse, DS: Drive signal from drive circuit, 05
0°051.052: Drive signal from circuit block, 8
1. f(2: horizontal drive line for display panel, RD:
Reference data, RDO~l? 03F Bit data No. 753 in reference data, SD: Specified data, 500 to SD3:
Complementary bit data signal in specified data, SP: Shift pulse for shift register, SS: Display command, SSI
, Display command for SS2+ circuit block, -DO~1
103: Weighting is each bit data signal in the data. ,”2 Patent Attorney Nori Yamaguchi ＼21.; Te, -
Njino / A-poor big 4? Figure 1 Figure 2

Claims (1)

[Claims] 1) A drive circuit that receives specification data specifying display brightness for each pixel in a display panel using a multi-bit digital value and outputs a drive signal having a pulse width corresponding to the specified data. , a reference data generation circuit that generates reference data that monotonically changes over time and has the same number of bits as the specified data based on a display command, and a matching circuit that compares the specified data and reference data and issues a match detection signal when the two match. It is characterized by comprising a detection circuit and a state switching circuit that is set to one state by a display command and switched to the other state by a coincidence detection signal, and a state output signal of the state switching circuit is emitted as a drive signal. Display panel drive circuit. 2) A display panel drive circuit according to claim 1, wherein the reference data generation circuit is a counter circuit. 3) A display panel drive circuit according to claim 1, wherein the coincidence detection operation of the coincidence detection circuit is performed every time the reference data from the reference data generation circuit changes. . 4) A display panel drive circuit according to claim 1, wherein the state switching circuit is a flip-flop circuit. 5) A display panel drive circuit according to claim 1, wherein the drive signal is voltage-converted and then applied to the pixel.