JPS63185331U - - Google Patents
Info
- Publication number
- JPS63185331U JPS63185331U JP7706087U JP7706087U JPS63185331U JP S63185331 U JPS63185331 U JP S63185331U JP 7706087 U JP7706087 U JP 7706087U JP 7706087 U JP7706087 U JP 7706087U JP S63185331 U JPS63185331 U JP S63185331U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- clock signal
- detection
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 2
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Description
第１図は本考案の実施例に係る信号検出回路の
ブロツク図、第２図は第１図の回路各部分におけ
信号波形を示した図である。
１……受信回路、２……結合コンデンサ、３…
…ラインレシーバ、４……クロツク抽出回路、５
……整流回路、６……増幅回路、７……コンパレ
ータ、８……基準電圧電源、９……ＡＮＤゲート
。
FIG. 1 is a block diagram of a signal detection circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing signal waveforms in each part of the circuit of FIG. 1... Receiving circuit, 2... Coupling capacitor, 3...
...Line receiver, 4...Clock extraction circuit, 5
... rectifier circuit, 6 ... amplifier circuit, 7 ... comparator, 8 ... reference voltage power supply, 9 ... AND gate.
Claims (1)
抽出するクロツク信号抽出回路と、前記クロツク
信号を整流する整流回路と、その整流信号を所定
の電圧まで増幅して出力する増幅回路と、前記増
幅回路の出力が基準設定電圧値より大きい時は検
出信号“１”レベルの信号を発生し、また前記増
幅回路の出力が基準設定電圧値よりも小さい時は
検出信号“０”レベルの信号を発生する判別回路
とを有することを特徴とする信号検出回路。 a clock signal extraction circuit that extracts a clock signal from a signal input from a communication line; a rectifier circuit that rectifies the clock signal; an amplifier circuit that amplifies the rectified signal to a predetermined voltage and outputs the amplified signal; When the output is larger than the reference setting voltage value, a detection signal of the "1" level is generated, and when the output of the amplifier circuit is smaller than the reference setting voltage value, a detection signal of the "0" level is generated. A signal detection circuit comprising a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7706087U JPS63185331U (en) | 1987-05-22 | 1987-05-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7706087U JPS63185331U (en) | 1987-05-22 | 1987-05-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63185331U true JPS63185331U (en) | 1988-11-29 |
Family
ID=30924715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7706087U Pending JPS63185331U (en) | 1987-05-22 | 1987-05-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63185331U (en) |
-
1987
- 1987-05-22 JP JP7706087U patent/JPS63185331U/ja active Pending
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