JPS63185235U - - Google Patents
Info
- Publication number
- JPS63185235U JPS63185235U JP7645487U JP7645487U JPS63185235U JP S63185235 U JPS63185235 U JP S63185235U JP 7645487 U JP7645487 U JP 7645487U JP 7645487 U JP7645487 U JP 7645487U JP S63185235 U JPS63185235 U JP S63185235U
- Authority
- JP
- Japan
- Prior art keywords
- area
- integrated circuit
- semiconductor integrated
- utility
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000007689 inspection Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7645487U JPS63185235U (de) | 1987-05-21 | 1987-05-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7645487U JPS63185235U (de) | 1987-05-21 | 1987-05-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63185235U true JPS63185235U (de) | 1988-11-29 |
Family
ID=30923545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7645487U Pending JPS63185235U (de) | 1987-05-21 | 1987-05-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63185235U (de) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001338955A (ja) * | 2000-05-29 | 2001-12-07 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
-
1987
- 1987-05-21 JP JP7645487U patent/JPS63185235U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001338955A (ja) * | 2000-05-29 | 2001-12-07 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |