JPS63184474A - Picture processing unit - Google Patents

Abstract

PURPOSE:To improve the picture processing speed by storing information obtained by a representative gradation extraction means and a detailed information detection means into a picture memory. CONSTITUTION:After each picture and mask information are stored in memories 109-111, when the synthesized display is applied and a level of a signal line 351 is 0, the picture data selected by the mask information in a picture flag memory 111 is outputted on a display device via a signal line 117 to form a superimposed picture. When the level of the signal line 351 is 1, the mean value of the gradation of the pictures A, B is outputted to the signal line 117 and the pictures A, B are transmitted and displayed with synthesis. If contour is too remarkable, the signal line 351 is controlled so as to select a mean value picture at the contour.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus having at least a function of displaying an input image.

[Prior Art] Conventionally, in order to interactively manipulate image data, this type of device has separate memories for storing images to be displayed on a display device and memories for storing actual image data for printing. was common.

This is because actual image data used for recording such as printing generally has a larger number of pixels and gradations than display image data, and image data for display needs to be accessed at high speed. It is. This is the recognition that the final goal of normal image processing is to print out with high clarity and high resolution, and that the processing in between, that is, image editing while looking at the display screen, is an intermediate process to achieve that final goal. It arises from. Furthermore, the cost can be kept lower than by increasing the accuracy of the display device itself.

[Problems to be Solved by the Invention] However, if the high-speed memory is configured to hold not only display image data but also image data used for print recording, editing processing of actual images can be executed at high speed. , it becomes expensive. In addition, image data for display is held in high-speed memory,
If the recorded image data is held in a large-capacity external memory, editing processing of the actual image becomes slow. Even if recorded image data is stored in a large-capacity, high-speed external memory, editing processing (accessing data in the image memory for display) on the display screen and data in the memory for recorded images will also be required. Editing processes such as corrections must be performed accordingly, which is time-consuming.

In this case, since the processing is performed twice, there is a limit to the improvement in processing speed.

The present invention has been made in view of such prior art, and it is an object of the present invention to provide an image processing device that can improve memory efficiency and perform editing processing at high speed.

[Means for solving the problem] In order to solve this problem, the present invention has the following configuration.

That is, an image memory for storing a display image, an input means for manually inputting an image in multiple gradations, and a representative gradation value for extracting the representative gradation value of the entire n×m pixel block in the input image data. an extracting means, a detailed information detecting means for detecting detailed information of the pixel block, a storing means for storing information on the representative gradation value and the detailed information as one display pixel data in the image memory; display means for displaying only the representative gradation value in the display pixel data; and decoding into the size of the pixel block from the representative gradation value and detailed information in the display pixel data stored by the storage means. [Operation] In the configuration of the present invention, a means for storing information obtained by inputting an n×m pixel block manually by the input means using the representative gradation value extraction means and the detailed information detection means in the image memory; The information is then stored, displayed by a display means, and decoded by a decoding means.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In this embodiment, a case where the present invention is applied to a color image processing apparatus will be explained.

[Explanation of Configuration Diagram (Fig. 1) Fig. 1 is a block diagram of the image processing apparatus in this embodiment.

In the figure, 101 is a control processing device that controls the entire device, and performs processing according to a program stored in 102. 103 is a keyboard, and 104 is a mouse, which is one of the pointing devices, and these are connected to the control processing unit 101. 105 is an image reading device that reads an image, and the read image data is compressed and encoded by a compression encoder 106 (hereinafter, this compression encoded image data will be simply referred to as encoded data). ). Note that details of this compression encoder 106 will be described later. Reference numeral 108 denotes an expansion decoder that decodes the encoded data, and the decoded image data is used by the printing device 107 to form a permanent visible image (print output image). Also 109,
An image memory 110 stores encoded data generated by the compression encoder 106 via a system bus 118. 112 is an image memory 109;
This is a compositing unit that synthesizes arbitrary areas within 110 and outputs it to the display device 113. The area to be synthesized is the image flag memory 1.
This is determined by the flag data stored in 11.

[Description of Compression Encoding (FIG. 4)] The compression encoder 106 will be explained below using FIG. 4.

In the figure, 400 is a pixel block read by the image reading device 105, which is 4×4 pixels in this embodiment. Each pixel has color components R (red), G (green), B (
There are 256 gradations (8 bits) for each (blue). Therefore, the pixel block 400 manually generated via the bus 451 is composed of data of a total of 384 bits (=8×16×3).

Now, the pixel blocks 400 sequentially output from the image reading device 105 are processed by the representative color extraction unit 40 in the compression encoder 106.
1 via bus 451, pixel block 400
The color information that best represents the overall image is extracted. Although this embodiment will be described as taking the average value of the gradations for each color component (R, G, B) of each pixel, the present invention is not limited to this. For example, it may be determined based on the color distribution (standard deviation) of each pixel. in any case,
The representative color of the pixel block 400 is determined and output as representative color information 404a of the encoded data 404 via the bus 453. Note that when the compression encoder 401 determines the representative color, it outputs a value (threshold value) for each color component to the bus 452.

Now, the pixel block 400 is similarly stored in the buffer memory 40.
2 is also entered once. Note that this buffer memory 402
can store multiple pixel blocks.

Then, when the representative color is extracted by the representative color extraction unit 401 and the threshold value is input to the binarizer 403 via the bus 452,
The pixel block corresponding to the threshold value is also stored in the buffer memory 40.
2 is manually input to a binarizer 403 and binarized. The binarized 4×4 blocks for each color component are output as detailed information 404b of encoded data 404.

Furthermore, the pixel block 400 stored in the buffer memory 402 is input to the variance value calculation unit 405 via the bus 455, and the input pixel block 400 and each color component outputted from the representative color extraction unit 401 onto the bus 452 are The variance value σ8. σ. +('B is calculated. For example, the variance value aR of °'R (red) °° is as shown in the following equation.

In the formula, n is the number of pixels (16), and AR is R for each pixel.
The average value of the (red) component, R, indicates the gradation level of each pixel.

Further, the same calculation can be performed for other G (edge) and B (blue). The variance OR+(ff G +σ) for each color component obtained in this way is the bus 456
This information is output as distributed information 404c of the encoded data 404 through the encoded data 404, and constitutes the encoded data 404 together with the representative color information 404a and detailed information 404b described above.

At this time, the detail information 404b is binary information of each color component of the pixel block 400, so it is composed of a total of 48 bits (:=16X3), and the variance value information 40
Assuming that 4C is represented by 8 bits for each color component,
Encoded data 404 includes representative color information 404a (8x3 bits), detailed information 404b (16x3), and variance information 4.
04c (a×3 bits), which is a total of 96 bits, and its size is compressed to 1/4 of the 384 bits of the pixel block 400.

[Description of operation of the apparatus (FIGS. 2 and 3)] The encoded data 404 formed through the above processing is displayed on a display device in the same way as normal image data. That is, when displaying on a display device, only representative color information is displayed as image data. Therefore, the number of display dots on the display screen can be set to 1/16 of the number of pixels read by the image reading device 105.

What will be described below is an example in which image processing is performed using data compressed and encoded in this manner.

Now, the compressed and encoded image A (hereinafter simply referred to as image A) shown in FIG. 2(a) is stored in the image memory 110, and the compressed and encoded image shown in FIG. 2(b) is stored in the image memory 110. It is assumed that image B (hereinafter simply referred to as image B) is stored in image memory 109. The process up to forming compressed and encoded image C (hereinafter simply referred to as image C) shown in FIG. 2(C) using these images A and B will be explained. The operator inputs appropriate commands using the keyboard 103 or the mouse 104 to rotate and reduce only the image B in the image memory 109. In the next step, the bitmap information representing contour information for image B processed in this manner is converted into mask information (information of "1" or "0") and stored in the image flag memory 111. In this case, the outline information of image B is formed by scanning the image memory 109 and transmitting flag data to the image memory 111.
However, for example, the boundary may be specified by tracing the outline using the mouse 104.

Now, as described above, each image and mask information are stored in the memory 109.
~111, the combined display of images A and B will begin.

FIG. 3 is a diagram showing the internal configuration of the combining section 112.

In the figure, 301 and 304 are signal selectors that select either one of the manually input signals, and the signal selector 301
is the mask information of the image flag memory 111 (signal line 114
One of images A and B is selected based on the information sent to the user. 302 is a signal adder,
This is to add the gradations of images A and B. The added data is halved (averaged) by a halving circuit 303. The output of this 1/2 circuit is connected to one input side of the signal selector 304.

Therefore, for example, when the level of the signal line 351 is 0'°, the image data selected by the mask information in the image flag memory 111 is outputted to the display device via the signal line 117. The displayed image at this time becomes image C in which images A and B are superimposed, as shown in FIG. 2(c).

Furthermore, when the signal line 3510 level is 1°, the average gradation of images A and B is output to the signal line 154, and images A and B are eventually transmitted and displayed as a composite. become.

Note that with the above configuration, the contours may stand out when images are combined. Such cutting is accomplished by controlling the signal line 351 so that the average value image is selected at the contour location. That is, with the above configuration, image A
, the composite display ratio of B is 100:0 → 50:50 → 0:
This means that it can be controlled in three stages, 100%.

Further, when the image desired by the operator is displayed, the image memory 10 is actually stored based on the synthesized and displayed image C.
Image B in 9 and image A in image memory 110 are combined and stored in image memory 110. At this time, not only representative color information 404a in each encoded data but also detailed information 404
b. The distributed information 404c is also processed as a synthesis target. As a result, image C will be formed in image memory 110.

[Explanation of decompression decoding (FIG. 5)] Now, in order to finally print out image C, the encoded data of image C stored in image memory 110 is sequentially transferred to decompression decoder 108. and decrypt it.

In the decompression decoder 108, encoded data 4 input manually
The representative color information 404a, detail information 404b, and variance information 404c in 04 are decoded into a 4×4 pixel block with gradations.

In reality, for a pixel in which each color component in the detailed information 404b is binarized to 1°°, its representative color information 404b is
The average gradation level for each color component stored in a (A
R, A a, A a), the variance value (OR1σ
. , Oa). Further, for pixels that have been binarized and become 0°, decoding processing is performed by setting the value to a value obtained by subtracting the variance value from the average gradation level.

For example, for the color component 'R (red) °°, the pixel XR, which is binarized to °゛1°°, is X, mA R+
a, *... (2) The pixel xR which has been binarized and becomes "0°" is given by X R-A R-OR... (2).

FIG. 5 shows a simple transition of binarization processing and decoding processing for color component "°R°".

In the figure, 50 is the color component "R" read by the image reading device 105.
” pixel block. Furthermore, the numerical value in each pixel indicates the gradation value of the color component “R”.

51 is the average value of the gradation of the pixels in the pixel block 50 (
This is a binarized block that has been binarized with AR~53). Note that this average value is calculated by the representative color extraction unit 401 as described above. Further, from the calculated average value of each color component and the pixel block, the variance value calculation unit 405 calculates the variance for each color component using the variance calculation formula (2) shown above. Moreover, the dispersion value Q R in this case (FIG. 5) is 419. 52 is a decoded pixel block when the binarized block 51 is decoded.

Now, when decoding this binarized block to the decoded pixel block 52, from the above-mentioned equations (1) and (2), the binarized block 5
The gradation value of the pixel at °゛1°゛ within 1 is “72 (
−AR10R−53+19)”, and the pixel that is “0°” becomes “34 (=AR−σR)°”, and a decoded pixel block 52 that approximates the pixel block 50 is formed.

By the way, during normal printing, conversion processing into YMC (yellow, magenta, cyan), etc. is performed and output to the printing device 107, but this processing is assumed to be a conventional conversion processing, and will not be explained in this embodiment. Omitted.

[Explanation of other composite display (Figure 6)] In the above embodiment, when performing composite display, a case was explained in which the composite display of image A and image B is displayed at three levels of ratio, but further development is possible. An example of this will be explained based on FIG.

In the figure, 111a is an image flag memory, and this time it is assumed that each image memory 109, 110 is configured with 4 bits per pixel. By using these 4 bits, the composite display ratio of image A and image B is to be displayed in multiple stages (16 stages with 4 bits). Also, 60
．． 61 is a 4-bit value sent from the image flag memory 111a via the bus 63 to the bus 115°1.
This is a multiplier that multiplies the gradation value of the image data output on the 16 in 16 steps between 0.0 times and 1.0 times. Further, 62 is an adder that adds the signals from the respective multipliers 60 and 61, and the added result is displayed on the display device 1.
13 on signal line 117.

Let us now assume that (F)+a is on the bus 63, that is, all four bits are at high level. At this time, the multiplier 60
outputs the gradation level of the image data on the bus 115 to the adder 62 by 1.0 times, that is, without changing it. On the other hand, multiplier 6
Since the data from the image flag memory to 1 is inverted (that is, (0) + 6) and input, the gradation level of the image data on bus 116 is 0.0 times, that is, the output to adder 62 is " o”. The adder 62 simply adds the gradations of the manually input image data and outputs it to the display device 113 via the signal line 117, but in this case, only the image on the bus 115 is output to the display device 113. That's why it happens.

As can be seen from the above explanation, the image flag memory 111
By using the data from a, it is possible to display the gradation ratio of the image data output on the bus 115 and 116 in multiple stages.
By compositing the gradations near the contours of two images in multiple stages, the unnatural feeling of the contours caused by the compositing of two images is eliminated.

Furthermore, it also becomes possible to perform smooth image synthesis by switching from one image to another.

[Explanation of another block diagram (FIG. 7)] FIG. 7 is a further development of the block diagram of FIG. 1.

In the figure, the difference from the configuration in Figure 1 is the image memory 109.11.
0 and the image flag memory 111 are not directly connected to the system bus 118 but are connected through the processing unit 701.

In the configuration shown in FIG. 1, it is difficult to access memories 109 to 111 simultaneously, and processing by control processing device 101 takes time. Therefore, here, the control processing device 101 is distributed and divided into a control device 702 and a processing device 701. According to this configuration, in addition to improving efficiency by parallelizing access (reading/writing) to each memory,
Since the usage efficiency of the system bus 118 is reduced, the control unit 702 can also perform other processing, and the processing speed of the entire system increases.

As explained above, according to this embodiment, color image data is compressed to a fraction of its original size and displayed on the display screen, processed, and output as a high-resolution image when printed. becomes possible.

Furthermore, since image editing is done by changing only the representative color information, the processing speed of image processing is improved.

Furthermore, the composition ratio of two images can be set in multiple stages, making it possible to eliminate the unnatural feeling of the contours of the images to be composited, and image composition that smoothly switches from one image to the other. enabled display.

Furthermore, since the display image and the output image for printing etc. are not separated, there is no need to perform double processing on each memory, and the configuration can be configured with less memory, reducing costs. Become.

In this embodiment, it has been explained that the combination ratio of two images is set in multiple stages, but these two images may be subjected to logical operations such as logical sum or logical product.

Further, the pixel block is not limited to a size of 4×4, but can generally be realized with n×m pixels.

Furthermore, in the case of a device that processes images of only one color (for example, black), it can be easily realized by focusing on one of the color components that make up the color image described in this embodiment. It is.

[Effects of the Invention] As explained above, according to the present invention, image data is compressed to a fraction of its original size and displayed on the display screen for image processing, and when printed, a high-resolution image is obtained. In addition, since image editing is done by changing only the representative gradation information, the processing speed of image processing is improved.

Furthermore, memory can be used efficiently and images can be edited at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the image processing apparatus in this embodiment. FIGS. 2(a) and 2(b) are diagrams showing images to be combined. FIG. 2(c) is a diagram showing images after combination. Figure 3 is an internal configuration diagram of the synthesis unit shown in Figure 1, Figure 4 is an internal configuration diagram of the compression encoder shown in Figure 1, and Figure 5 explains the process until compression-encoded data is decompressed and decoded. 1 and 6 are diagrams for explaining another combining section, and FIG. 7 is a block diagram of another image processing apparatus according to the present embodiment. In the figure, 101...control processing unit, 102...memory, 103...keyboard, 1.04...mouse, 1
05... Image reading device, 106... Compression encoder,
107... Printing device, 108... Decompression decoder, 1
09°110... Image memory, 111, 1lla...
- Image flag memory, 112, 112a... synthesis unit,
113...Display device, 114-117...Signal line,
118...System bus, 301, 304...Signal selector, 302...Signal adder, 303...1/2
Circuit, 400... Pixel block, 401... Representative color extractor, 402... Buffer memory, 403...2
(t[1%, 404... encoded data, 404
a...Representative color information, 404b...Detail information, 60.
61... Multiplier, 62... Adder, 701... Processing device, 702... Control device. Three'11°, 1N t'

Claims (6)

[Claims] (1) An image memory for storing a display image, an input means for inputting the image in multiple gradations, and a representative gradation for extracting the representative gradation value of the entire n×m pixel block in the input image data. a value extracting means, a detailed information detecting means for detecting detailed information of the pixel block, a storing means for storing information on the representative gradation value and the detailed information as one display pixel data in the image memory; display means for displaying only the representative tone value in the display pixel data, and decoding into the size of the pixel block from the representative tone value and detailed information in the display pixel data stored by the storage means; An image processing apparatus comprising: a decoding means for decoding. (2) The image processing apparatus according to claim 1, wherein the input means is an image reading device. (3) The image processing apparatus according to claim 1, wherein the representative tone value extraction means extracts an average value of tone of each pixel in the pixel block. (4) The detailed information detection means includes a binarization means that binarizes the pixel block from the representative gradation value, and detects the variance of the pixel corresponding to the binarized data from the representative gradation value. 2. The image processing apparatus according to claim 1, further comprising dispersion detection means. (5) The image processing apparatus according to claim 1, wherein the image information compounded by the compounding means is outputted to a printing device. (6) When the image input by the input means is a color image, the representative gradation value extraction means and the detailed information detection means process the image for each color component. Processing equipment.