JPS63183686A - Digit line balance level correcting method - Google Patents

Abstract

PURPOSE:To balance a sense margin, and also, to prevent a digit line from receiving noise of other digit lines by short-circuiting a pair of digit lines at the time of precharge, and also, connecting an external capacity. CONSTITUTION:A precharge signal phiP1 becomes L, a word line WL rises and a sense operation starts, and H or L of a digit line is decided. In this active period, a reset signal phiP2 becomes H, and the level of a nodal point N21 is pulled down. Subsequently, when a precharge operation is started, the signal phiP2 and the word line WL fall, and thereafter, the signal phiP1 becomes H. As a result, the digit lines DL, the inverse of DL are short-circuited by a transistor TR Q21, and by capacity division, the levels of the lines DL, the inverse of DL become 1/2VCC theoretically. Simultaneously, the lines DL, the inverse of DL are connected to an external capacity C21 by TRs Q22, Q23, and since the capacity division to this capacity C21 is also added, the level of the lines DL, the inverse of DL drops down a little from exact 1/2VCC, and becomes a corrected 1/2VCC level. Also, said line does not become a noise source.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an MO using a 1/2Vcc precharge method.
The present invention relates to a digit line balance level correction method in an S memory device.

[Conventional technology]

In a MOS memory device that uses the QVcc precharge method, the QVcc precharge level is set slightly lower than the correct 1/2 Vcc level, considering the leakage of the level on the "II" side of the memory cell and the influence of alpha rays. It is better to balance the sense margin for "■" and "L".

Conventionally, a method as shown in FIG. 3 has been used for this correction. In this method, dummy word line WLI,
DWL2 is provided, and digit line D1. .

A capacity is inserted between the DL and the DL.

FIG. 4 is a diagram of its operating waveforms. The case where the F cell is -II'' will be described below. First, the precharge signal φ2 becomes ``pi'', and then the word line WL rises. Accompanying this, the dummy word line DWLI, which is capacitively connected to the digit line DL on the opposite side of the digit line OL to which the memory cell is connected, falls.

Then, due to the coupling, the level of the digit line DL on the "pi" side is slightly lowered from 1/2 Vcc. This correction improves the sense margin on the degraded cell "II" side.

(Problems to be Solved by the Invention) The conventional digit line balance level correction method described above adds a dummy word line and introduces capacitive coupling between the dummy word line and the digit line. This effectively strengthens the coupling between the digit lines through the digit line, which has the disadvantage that the digit line of interest is strongly affected by noise from other digit lines during the sensing operation.

[Means for solving problems]

The digit line balance level correction method of the present invention short-circuits the digit line pair and connects an external capacitor during the precharge period, and corrects the 1/2 Vcc level by capacitance division.

[For production]

Since the digit line pair is short-circuited by the transistor, the digit line is not affected by noise from other digit lines.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a MOS memory device to which the digit line balance level correction method of the present invention is applied.

Digit lines DL and OL have digit lines DL and [lL
Transistors Q 221 and Q 23 are connected to connect the digit lines DL and DL to the external capacitors Q21 and Q23, respectively, and a digit line balancing transistor Q21 is connected between the digit lines DL and DL, and these transistors Q21.
A precharge signal φP1 which becomes "11" during precharging is applied to the gates of Q22 and Q23. In addition, a transistor Q24 is connected in parallel to the external capacitor C21 for resetting the memory by extracting the charge stored in the capacitor AC2+ during the active period of the memory. A reset signal φP2 of 11'' is applied.

FIG. 2 is an operation waveform diagram when the cell is "H". The precharge signal φPI goes "L", the word line WL rises, the sensing operation starts, and the digit line "■"
1. “Shi” is settled. During this active period, the reset signal φP2 becomes "11" and the level of the node N21 is lowered. Next, when the precharge operation starts, the reset signal φp2 and the word line Wt fall, and then the precharge signal φPI becomes "11". Then, the digit lines OL, OL are short-circuited by the transistor Q71, and the level of the digit lines DL, DL becomes 1/2 Vcc in principle due to capacitance division, but at the same time, the digit lines DL, DL are short-circuited by the transistor Q22. Q13
The digit line D
The levels of L and (2) are slightly lower than the correct HVcc and become corrected HVcc levels.

(Effects of the Invention) As explained above, the present invention provides Prichi! - By connecting the digit line to an external capacitor and correcting the %VCC balance level at the time of cell °11" and "L"
This has the effect of not only being able to balance the sense margins of the sensors but also not becoming a noise source during sensing operations.

・

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a MOS memory device to which the digit line balance level correction method of the present invention is applied, FIG. 2 is a waveform diagram showing the operation of the embodiment of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing the conventional example, and a waveform diagram showing the operation of the conventional example shown in FIG. φ, , −so m** *** precharge signal,
φP 2 F""""" Reset signal, W L -
--------- Word line, OL, DL----- Digit line, Q z8. Q
22, Q23, Q24 = ・”-transistor, C21”””””””capacitance, N21””””””-node.

Claims (1)

[Claims] In a 1,1/2 Vcc precharge type MOS memory device, the digit line pair is short-circuited and connected to an external capacitor during the precharge period, and the capacitance is divided to 1/2 Vcc.
A digit line balance level correction method for correcting the 2Vcc level. 2. The digit line balance level correction method according to claim 1, wherein the charge stored in the external capacitor is discharged during the active period.