JPS63181468A - Mis field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent the change in the characteristics such as the reduction in a current drive force by a hot carrier phenomenon, the fluctuation in a threshold voltage, etc., and to obtain a highperformance and fine MISFET by a structure wherein a part of a gate insulating layer is constituted by an insulating layer composed of a different material. CONSTITUTION:On a p-Si substrate 1 where field SiO2 layers 2 have been formed, an SiN layer 3 150 Angstrom thick as a first insulating layer and then an SiO2 layer 4' 4000 Angstrom thick are grown in succession by a vapor growth method; these layers are patterned in such a way that the remaining length is shorter than the length of a gate. Then, an SiO2 layer 3' 150 Angstrom thick as a second insulating layer is formed on the substrate by thermal oxidation; a poly Si layer is grown on the whole surface of the substrate by a CVD method; a poly Si sidewall 5 is formed by an anisotropic etching method which is predominant in the vertical direction. Accordingly, a part near a drain is composed of SiO2 instead of SiN; the injection amount of hot carrier is reduced; it is possible to obtain a MISFET whose characteristics hardly fluctuate and whose current drive force is big.

Description

[Detailed Description of the Invention] [Summary] In an HIS field effect transistor (FET), the gate insulating layer is made extremely thin in order to increase the speed and reduce the power supply voltage.
In order to suppress the hot carrier phenomenon caused by charged particles accelerated in the MisFET channel, a structure is proposed in which part of the gate insulating layer is an insulating layer made of a different material to prevent deterioration of transistor characteristics. do.

[Industrial application field]

The present invention is a gate Is with a structure that suppresses the hot carrier phenomenon.
Regarding FET.

In recent years, there has been a strong demand for higher speed and higher integration of semiconductor integrated circuits, and therefore individual MiS FETs need to be further miniaturized.

[Conventional technology]

When miniaturizing IS FETs, if only the lateral dimension is miniaturized, the current driving force increases, but at the same time, so-called short channel effects such as a decrease in threshold voltage, a decrease in carrier mobility, and the generation of hot carriers occur. will occur.

In order to prevent this short channel effect, it is necessary to reduce the vertical dimension of the MisFET, that is, the gate insulating layer, but this further increases the amount of characteristic deterioration due to the generation of hot carriers.

In order to suppress characteristic deterioration due to hot carriers, it is necessary that a portion of the gate insulating layer on the drain side has sufficiently high hot carrier resistance.

LDD is a conventional technology for suppressing hot carriers.
(Lightly Doped Drain) structure.

Figure 3 shows a MIS FET with an LDD structure, explaining a conventional example.
FIG.

In the figure, ■ is a p-type silicon (p-St) substrate, 2 is an isolation insulating layer that defines a transistor formation region and is a field silicon dioxide (SiOz) layer, IA and IB are n-type source and drain regions, and IC1ID is a field silicon dioxide (SiOz) layer. n-type regions 33 connected to the source and drain regions and formed on the gate side, respectively;
4 is a gate insulating layer made of a Si layer; 4 is a gate electrode made of a polycrystalline silicon (polySi) layer; 35 is a side wall made of an insulating layer; 8 is an insulating layer made of SiO2 layer or phosphosilicate glass (PSG).
IJ, 9.10 are source and drain electrodes.

Such an LDD structure suppresses the generation of hot carriers by relaxing the electric field near the drain by the n-type region IC, 10.

[Problem that the invention seeks to solve]

However, the effective channel length La in the LDD structure
ff is shorter than that of the conventional structure by the n-type region, and the resistance bone in the n-type region becomes a parasitic resistance, resulting in M
The current driving power of IS PET is reduced.

Furthermore, there is still no established theory regarding the optimum values required for the characteristics of the n-type region specifications of the LDD structure, and the manufacturing process conditions are also complicated.

[Means for solving problems]

The solution to the above problem includes a source region and a drain region provided on a semiconductor substrate, and a gate insulating layer and a gate electrode sequentially formed on the semiconductor substrate between both regions, and the gate insulating layer is a second insulating layer formed adjacent to one side or both sides of the first insulating layer and having a larger barrier height to the semiconductor substrate than the first insulating layer; This is achieved by effect transistors.

[Effect]

It is known that hot carriers are generated mainly near the drain electrode, and in actual circuits, MisFETs are treated as symmetrical.

Therefore, the present invention improves hot carrier resistance by replacing an appropriate length inward from both ends of the gate insulating layer consisting of the first insulating layer under the gate electrode with a second insulating layer having a large barrier height with respect to the substrate. It is something that increases.

In this structure, even if hot carriers are generated due to the electric field between the source and drain, if the amount of hot carriers injected into the second insulating layer is smaller than when only the first insulating layer is used, the current driving force can be reduced. Phenomena such as drop or threshold voltage fluctuation do not occur.

In this case, the first insulating layer only needs to have a large dielectric constant and be sufficiently thin in order to obtain a large current driving force.

Further, the second insulating layer is required to have a high barrier height and a large barrier potential with respect to the semiconductor substrate, and not to remain in the layer even after hot carrier injection.

As an example, a silicon nitride (SiN) layer can be used as the first insulating layer, and a SiO□ layer can be used as the second insulating layer.

The forbidden band width is about 9 eV for SiO□ and about 7 eV for SiN.
V, therefore St (the forbidden band width is 1.1 eV
) is also larger for SiO□.

The dielectric constant is ~7 for SiN and 3.8 for SiO□, so the current driving force is thicker for SiN (and
□ generates fewer trap levels during film formation than SiN, and reduces the phenomenon in which real carriers are trapped here and change the threshold voltage.

Therefore, a part of the vicinity of the drain is made of SiO instead of SiN.
If it is set to □, the amount of hot carriers injected will be reduced, and a MIS NET with little characteristic fluctuation and large current driving power can be obtained.

Embodiment C] FIG. 1 is a sectional view of an old SFET for explaining the present invention.

In the figure, 1 is a p-3i substrate, 2 is a field SiO
□ layer, LA, IB are n1 type source and drain regions,
3 is the first insulating layer of the gate insulating layer, which is a SiN layer; 3' is the second insulating layer of the gate insulating layer, which is a 5iOz layer; 4 is the gate electrode, which is a poly-Si layer; 5 is the poly-Si sidewall; 9 is an insulating layer, which is a SiO□ layer or a PSG layer, and 9.10 is a source and drain electrode.

Next, an example of the manufacturing process of the MIS FET of the present invention will be explained.

FIGS. 2(1) to 2(8) are cross-sectional views illustrating the manufacturing process of the present invention in order of process.

In Figure 2 (11), by the vapor phase growth (CVD) method,
On the p-Si substrate 1 on which the field 5io2752 was formed, a SiN layer 3 with a thickness of 150 μm as a first color edge layer, followed by a 5 iOz * 4′ with a thickness of 4000 μm were sequentially grown. Buttering is done by leaving it shorter than the gate length.

In FIG. 2(2), a 150-layer SiO□ layer 3' is deposited on the substrate as a second insulating layer by thermal oxidation.

In Fig. 2 (3), a poly-Si layer with a thickness of 4,000 wafers is grown on the entire surface of the substrate by the CVD method, and the poly-Si layer is etched using anisotropic etching with a predominance in the vertical direction by the reactive ion etching (1'11E) method. A side wall 5 of Si is formed.

Next, 5i07. exposed on the substrate surface. ffi3'
is used as a through oxide film, and arsenic ions (As") are implanted using the entire SiO□ layer 4'4'5 as a mask to form n"' type source and drain regions IA and IB.

In FIG. 2 (4), a layer 6 of 4000 nm thick is grown on the entire surface of the substrate by the CVD method, and then a thick layer of 1/cyst or SOG (spin-on glass) 7 is deposited to flatten the substrate. .

In FIG. 2(5), planarization etching is performed using RIB to expose the surface of the 5iOz layer 4'.

In Fig. 2 (6), SiO□ was formed by hydrofluoric acid etching.
The entire layer 4' is 4', and poly 5iJ54 with a thickness of 4,000 wafers is grown on the entire surface of the substrate by the CVD method.

In FIG. 2(7), planarization etching is performed by RIH to expose the surface of the SiO□ layer 6.

In FIG. 2(8), the 5iOz layer 6 is removed.

The subsequent steps are 5i0 by CVD method as shown in FIG.
A second layer 8 is grown over the entire surface of the substrate, and openings are formed over the source and train regions IA and IB of this layer to form source and drain electrodes 9.
．． 10 is formed to complete the wafer process.

In the embodiment, the SiN layer 3 of the first insulating layer and the SiO□[3' of the second insulating layer are made to have the same thickness, but they may have different thicknesses.

Further, in the embodiments, the old S FET as an individual device has been described, but it goes without saying that the gist of the present invention does not change for an integrated circuit in which this is integrated.

〔Effect of the invention〕

As explained in detail above, according to the present invention, changes in characteristics such as a decrease in current driving power and fluctuations in threshold voltage due to hot carrier phenomena are prevented, and high performance and fine MIS FETs can be realized.
is obtained.

Furthermore, by using the MIS PET of the present invention,
A high-speed, highly integrated circuit can be obtained.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the old S FET explaining the present invention, Figure 2
Figures (1) to (8) are cross-sectional views explaining the manufacturing process of the present invention step by step, and Figure 3 is a cross-sectional view of an old SFET with an LDD structure, explaining a conventional example. In the figure, 1 is a p-5i substrate, LA and IB are n3 type source and drain regions, 2 is a field insulating layer, which is an SiO□ layer, 3 is a first insulating layer, which is an SiN layer, and 3' is a second insulating layer. 4 is a gate electrode and is a poly-Si layer, 4' is a 5iOz layer, 5 is a side wall of poly-Si, 6 is a Si02 layer, and 7 is a resist or SOG. 8 is an insulating layer with 5totJ! J, 9.10 are source and drain electrodes Figure j

Claims (1)

[Scope of Claims] A source region and a drain region provided on a semiconductor substrate, a gate insulating layer and a gate electrode sequentially formed on the semiconductor substrate between both regions, the gate insulating layer being a first an insulating layer, and a second insulating layer formed adjacent to one side or both sides of the first insulating layer and having a higher barrier height with respect to the semiconductor substrate than the first insulating layer. MIS type field effect transistor.