JPS63181348A - Layout design equipment for lsi - Google Patents

Abstract

PURPOSE:To make layout design possible in a short time and with high efficiency, by using a hierarchical layout system in which a processing is performed in the order of rough layout, block layout and chip layout. CONSTITUTION:In the stage of rough layout, the relative arrangement of each function block and the temporary wiring path between the blocks are determined, under the consideration of electrical and thermal influences at the time of LSI operation, while the forms of function blocks are not yet decided. When the block layout is finished, the forms of all function blocks are decided. In the process of chip layout based on the above result, some discrepancies against the relative arrangement of the function blocks initially decided occur, but the temporary wiring path at the time of rough layout can be reproduced by chip layout decision means. Therefor, the initial wiring path can be obtained, in which electrical and thermal influences are taken into account. Thereby, a consistent automatic design is enabled, which completes a total mask pattern from the stage of temporary form evaluation of blocks, and the layout design of LSI can be done in a short time and with high efficiency.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention is an LSI method for obtaining mask patterns for LSI manufacturing.
The present invention relates to an SI layout design device, and particularly to a layout design device using a hierarchical layout method.

(Prior Art) A hierarchical layout method is known as one method of LSI layout design. This is, for example, JP-A-50-1
As described in Publication No. 6017, each functional block (hereinafter referred to as
After determining the detailed layout and final shape (these are referred to as block layouts) within a block, the relative placement of each block and tentative wiring routes between blocks are determined as a rough layout based on this block layout. Finally, the wiring space between blocks is evaluated to determine the final arrangement of each block and the final wiring route between the blocks as a chip layout.

On the other hand, when it is necessary to decide the arrangement of blocks, wiring routes between blocks, and wiring shapes in consideration of electrical and thermal effects during LSI operation, such as in analog ICs, the temporary shape of the blocks is used in the block layout. At the stage of estimating the rough layout, the relative placement of the blocks, wiring routes between blocks, and wiring shapes are also estimated, and the detailed layout within the block is kept to a temporary shape as much as possible, so that the rough layout results are directly reflected in the chip layout. ing. For this reason, it is very difficult to automate the rough layout, and there are significant restrictions regarding the shape of the blocks, so we either rely on manual design or process the process using an element-level expansion method without using the hierarchical layout method.

However, the reality is that as the scale of LSIs increases, both methods are becoming unmanageable in terms of design time and cost.

(Problems to be Solved by the Invention) As described above, with the conventional technology, as LSIs become larger in scale, it is difficult to design the layout of LSIs in a short period of time, taking into account the electrical and thermal effects during operation. The problem was that it was difficult.

An object of the present invention is to provide an LSI layout design device that can take into account electrical and thermal effects during LSI operation and can obtain desired mask patterns in a short design period and at low cost even for large-scale LSIs. With the goal.

[Structure of the Invention] (Means for Solving the Problems) The present invention employs a hierarchical layout method in which rough layout, block layout, and chip layout are processed in this order. A layout specification storage unit that stores information on intra-block layout conditions, inter-block layout conditions, and block area; and a rough layout determining unit that determines rough placement and rough wiring on the LSI chip from the information stored in the layout specification storage unit. a rough layout information storage unit that stores information on the rough layout and rough wiring determined by the rough layout determining means; a block layout determining means for determining the detailed layout of the functional block, a determined shape of each functional block, and a determined input/output terminal position; a block layout information storage section for storing information determined by the block layout determining means; and a block layout information storage for storing information determined by the block layout determining means. chip layout determining means for determining the final arrangement of each functional block on the LSI chip and the final wiring routes between the blocks as a final layout of the entire LSI chip from the information stored in the layout specification storage section and the rough layout information storage section; a chip layout information storage unit that stores the chip layout information determined by the chip layout determination means; and a chip layout information storage unit that stores the chip layout information determined by the chip layout determination unit; The present invention is characterized by comprising means for synthesizing mask patterns.

(Function) In the rough layout, the shape of the functional blocks remains undetermined, and the rough placement and rough wiring, that is, the relative placement of each functional block and the temporary arrangement between the blocks, is done in consideration of the electrical and thermal effects during LSI operation. The wiring routes are determined, and the shapes of all functional blocks are determined upon completion of this block layout. When performing a chip layout based on this, deviations from the initially determined relative placement of functional blocks may occur, but since the chip layout determining means can reproduce the tentative wiring routes during the rough layout, it is possible to A wiring route can be obtained that takes into account the influence. As a result, it is possible to achieve consistent automation from the stage of estimating the board shape of the block to completing the mask pattern for the entire chip. Even when designing a large-scale LSI layout, the mask pattern can be created efficiently and in a short time, and therefore at low cost. Created at cost.

(Embodiment) FIG. 1 is a block diagram showing the configuration of an LSI design device according to an embodiment of the present invention.

Further, FIG. 2 is an explanatory diagram of a hierarchical layout method used in the same embodiment, and FIG. 3 is a flowchart showing a layout design procedure in the same embodiment.

In this embodiment, as shown in FIG. 2, a rough layout is first performed, then a block layout is performed, and then a chip layout is performed.

In FIG. 1, a layout specification storage unit 1 stores intra-block layout conditions (intra-block placement/wiring requirements, intra-block placement/wiring constraints, etc.) for each functional block of the LSI,
Information on inter-block layout conditions (inter-block placement/routing requirements, inter-block placement/routing constraints, etc.) and approximate value of block occupied area (hereinafter simply referred to as block area) is stored in advance as a layout specification, and is also a library. 2 stores block information such as the layout within the block of functional blocks whose layout has been designed.

The rough layout determining means 3 reads the block shape information from the library 2 for a functional block that uses an existing needle block, and reads the area of the block and the block shape from the layout specification storage unit 1 for a newly designed functional block. By reading information on inter-block wiring requirements and inter-block placement/wiring constraints, which are factors that determine relative placement, rough placement on the LSI chip (block pattern shape, relative placement, temporary position of input/output terminals, etc.) ) and rough wiring (tentative wiring route between blocks).

The block area is calculated in advance using an empirical formula by evaluating the number of elements, cells, and wiring or nets constituting the block in the preprocessing stage of the layout design procedure shown in FIG. 3.

That is, the rough layout determining means 3 sets the existing needle blocks to a fixed shape, generates the specified shape for newly designed blocks whose shape is specified as an inter-block arrangement constraint, and sets the shape to a fixed shape, and sets the shape to the fixed shape for the other blocks. For now, a square shape corresponding to the block area will be generated, but the shape will be variable. Then, relative placement of blocks is determined taking into consideration inter-block wiring requirements and inter-block placement constraints, and at this time, the placement is determined so that the chip size is minimized by changing the shape of the variable-shaped block. As a result, the plate shape on the chip is determined even for blocks with variable shapes.

Next, based on this relative placement, inter-block wiring requirements, and inter-block wiring constraints, the human output terminal positions of the new design block are tentatively determined, and the input/output terminals of the already designed blocks are also added.
Inter-block tentative wiring routes between the input and output terminals of all these blocks are determined. This inter-block tentative wiring route is not a fixed route on the chip, but indicates approximately where the wiring will pass. Conventionally, such wiring paths have been stored as a series of channels, which are wiring areas in which blocks face each other. However, in the layout design method according to the present invention, since the shape of the block is a temporary shape at the time of rough layout, the structure of the channel may have changed at the stage of chip layout after block layout processing. Even if a tentative wiring route is determined in consideration of inter-block wiring constraints in the rough layout, it will not be possible to reproduce it at the chip layout stage. Therefore, in this embodiment, the temporary wiring route between blocks is not a series of channels, but a series of pairs of the identification name of the block that the wiring route passes by and the identification name of the vicinity of that block. Remember. This storage method will be explained in detail later.

In this way, L determined by the rough layout determining means 3
Rough placement and rough wiring information on the SI chip, i.e. temporary block shape information (pre-designed blocks and newly designed blocks with a specified shape are fixed shapes), input/output terminal board position information (pre-designed blocks are fixed positions), blocks The relative placement information and the information on the temporary wiring routes between blocks are written into the rough layout information storage section 4.

On the other hand, the block layout determining means 5 determines the detailed layout within the block, the determined shape of the block, and the determined positions of the input/output terminals for the newly designed block. In other words, from the layout specification storage unit 1, the intra-block arrangement/
Information on wiring requirements and intra-block placement/wiring constraints, as well as temporary block shape information and input/output terminal board position information from the rough layout information storage section 4 are sent to the block layout determining means 5.
The arrangement of elements or cells within the block and wiring routes are determined from this information. In this case, the block is still in the preliminary shape stage, and for blocks whose shape has not been specified, the shape after determining the detailed layout may differ from the tentative shape. It shifts.

In this way, the detailed layout within the block determined by the block layout determining means 5, information on the determined shape of the block, and information on the determined positions of the input/output terminals are written into the block layout information storage section 6. At this point, the shapes and input/output terminal positions of all required blocks have been determined, and the intra-block layout has been prepared.

Next, in the chip layout determining means 7, the layout information storage section 1. Library 2. Rough layout information storage section 4
Based on the information stored in the block layout information storage section 6, a detailed inter-block layout at the chip level is determined. At this time, there is no need to refer to the detailed layout within the block. That is, information on inter-block wiring requirements and inter-block placement/wiring constraints is stored in the layout specification storage unit 1, and information on the shape of already designed blocks and input/output terminal positions is stored in the rough layout information storage unit 4 from the library 2.
The block relative placement information and inter-block temporary wiring route information are read from the block layout information storage section 6, and the information about the confirmed shape of the newly designed block and the confirmed input/output terminal positions are read into the chip layout determining means 7. First, each block whose shape has been determined is placed at a corresponding position based on block relative placement information and inter-block placement constraints.

At this time, since the temporary block shape stored in the rough layout information storage section 4 and this final shape are generally different, it is not always possible to arrange the blocks according to the relative block arrangement information, and deviations occur. Next, a temporary wiring route between blocks is traced based on this placement situation. Here, since the inter-block tentative wiring route was based on the initial block relative placement information,
Although it is not possible to directly apply the route to this placement situation, by sequentially tracing the edges of the blocks that the route passes through, which is a memory representation of the tentative routing route, the tentative routing route determined in consideration of various constraints can be used as a new It can be reproduced depending on the placement situation. Once all wiring routes have been determined, the wiring space is evaluated for each channel, and where there is a shortage of space, the layout is corrected by moving blocks by the amount of the shortage to secure the wiring space. After that, a defined wiring route between blocks is obtained along each path, and at the same time, a defined shape of the entire chip is obtained. In this way, the final layout at the inter-block level determined by the chip layout determining means 7 is written into the chip layout information storage section 8.

Finally, the entire chip mask pattern synthesis means 9 generates the detailed layout of the already designed blocks in the library 2, the detailed layout of the newly designed blocks in the block layout information storage section 6, and the blocks in the chip layout information storage section 8. A detailed mask pattern for the entire chip is synthesized based on the detailed layout, and pattern data 10 is obtained.

Next, a method of storing information on tentative wiring routes between blocks (routing routes of rough wiring) in the rough layout storage section 4 and a method of using this information in the chip layout determining means 7 will be explained.

As mentioned above, the temporary wiring route between blocks is stored as a series of pairs of the identification name of the block that the route passes by and the identification name of the peripheral part of that block, so the peripheral part of each block can be identified. It is necessary to. FIG. 5 shows a specific example of a method for identifying the peripheral edge of a block, in which identification names are given to the positions indicated by black dots, that is, to each vertex of the rectangular shape of the block and to the center point of the top, bottom, left, and right sides.

FIG. 6 is a diagram for explaining an example of a method for storing the tentative wiring route determined by the rough layout determining means 3 in the rough layout information storage unit 4 using a pair of a block identification name and a block peripheral area identification name. , when the temporary wiring route goes around a corner of a block (indicated by diagonal lines) as shown in (a) of the same figure, the block identification name of the block and the block peripheral identification name of the vertex corresponding to that corner correspond to each other. let me,
Set a series of pairs of two identifiers such as (BLCK, bottom right). In addition, if the temporary wiring route goes straight through a three-way intersection as shown in Figure (b), the block identification name of the block facing the temporary wiring route along the straight direction and the name Match the identification names of the center points of the sides, and (B
Set a -sequence such as LCK, philtrum). Furthermore, if the temporary wiring route goes straight through a four-way intersection as shown in (c) of the same figure, the block identification names of the four blocks facing the four-way intersection and the identification names of the vertices are added to the route. Match the pairs of two along the line, 1 (BLCKI, bottom right) OR (BLC
K2. lower left) AND ((BLCK3, upper right) OR(
Set a series like BLCK4, upper left)). The series set in this way is set in the rough layout information storage unit 4 with the start and end points of the tentative wiring route as the input/output terminal board positions.
is stored as temporary wiring route information. FIG. 7 shows a concrete example of the temporary wiring route status and its stored contents.

For the tentative wiring routes stored in this manner, the chip layout determining means 7 sequentially searches for routes by tracing the peripheral edges of the stored blocks in the order in which they are stored, with the start and end points of the route as fixed input/output terminal positions. This is used to determine the final wiring route. A normal wiring algorithm can be used as a route search algorithm.

[Effects of the Invention] According to the present invention, a hierarchical layout method is used in which rough layout, block layout, and chip layout are processed in this order, and a block is created in which electrical effects and thermal effects during LSI operation are first considered in the rough layout. After block layout, the inter-block placement/wiring results can be reproduced in the chip layout without depending on the intra-block placement/wiring and block shape. Therefore, it is possible to design the layout of a large-scale analog LSI in which electrical and thermal effects between blocks are particularly problematic, in a short time and efficiently. In addition, even if a block of a different size than before is placed on the chip because some blocks are modified in design or replaced with already designed blocks, the relative placement between blocks and the temporary As for wiring route information, the same data as before can be used as is, which has the effect of simplifying design modification work and reducing design costs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an LSI layout design device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a hierarchical layout method used in the embodiment, and FIG. 3 is an illustration of the same embodiment. FIG. 4 is a flowchart showing the layout design procedure in the hierarchical layout method, and FIG. FIG. 6 is a diagram illustrating a specific example of the block identification method in the same embodiment, and FIG. FIG. 7 is a diagram showing a concrete example of the temporary wiring route situation and its stored contents in the same embodiment. 1... Layout specification storage unit, 2 library, 3...
- rough layout determining means, 4... rough layout information storage section, 5... block layout determining means, 6.
. . . Block layout information storage unit, 7 . . Chip layout determining means, 8 . . Chip layout information storage unit, 9 .
...Final mask pattern. Applicant's agent Patent attorney Takehiko Suzue Figure 2 (a) (b) Figure 4

Claims (3)

[Claims] (1) A layout specification storage section that stores information on the intra-block layout conditions, inter-block layout conditions, and block area of each functional block of the circuit constituting the LSI;
a rough layout determining means for determining rough placement and rough wiring on a chip; a rough layout information storage section for storing information on the rough placement and rough wiring determined by the rough layout determining means; block layout determining means for determining a detailed layout in each functional block, a determined shape of each functional block, and a determined position of an input/output terminal from information stored in the layout specification storage unit; and information determined by the block layout determining means. a block layout information storage section that stores the information stored in the block layout information storage section, the layout specification storage section, and the rough layout information storage section; A chip layout determining unit that determines a route as a final layout of the entire LSI chip; a chip layout information storage unit that stores chip layout information determined by the chip layout determining unit; and the chip layout information storage unit and the block layout information. Based on the information stored in the storage unit, the LSI
1. An LSI layout design device comprising means for synthesizing mask patterns of manufacturing masks. (2) The rough layout information storage unit stores, as wiring route information for rough wiring between blocks, a series of pairs of the identification name of the block through which each wiring route passes and the identification name of the peripheral part of the block. An LSI layout design device according to claim 1, characterized in that: (3) The rough layout information storage unit stores, as wiring route information for rough wiring between blocks, a series of pairs of the identification name of the block through which each wiring route passes and the identification name of the peripheral part of the block. The LSI layout according to claim 1, wherein the chip layout determining means determines a definite wiring route between blocks on an LSI chip based on wiring route information of rough wiring. Design equipment.