JPS63181317A - Alignment mark - Google Patents

Alignment mark

Info

Publication number
JPS63181317A
JPS63181317A JP62011381A JP1138187A JPS63181317A JP S63181317 A JPS63181317 A JP S63181317A JP 62011381 A JP62011381 A JP 62011381A JP 1138187 A JP1138187 A JP 1138187A JP S63181317 A JPS63181317 A JP S63181317A
Authority
JP
Japan
Prior art keywords
alignment
substrate
alignment mark
trenches
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62011381A
Other languages
Japanese (ja)
Inventor
Hidehiro Tono
秀博 東野
Norio Moriyama
森山 徳生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62011381A priority Critical patent/JPS63181317A/en
Publication of JPS63181317A publication Critical patent/JPS63181317A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To enable the alignment to be performed with a high precision by forming grooves in a substrate, and filling the surrounding thereof with a material of a different refractive index. CONSTITUTION:In a substrate 16, there are provided trenches 15 and buried layers 11 filling the trenches 15, and the buried layers 11 are formed so as to have a height same as that of the surrounding part of the trenches 15 and have a refractive index different from that of the substrate 16 forming the surrounding of the trenches 15. For example, it the substrate 16 is Si, the buried layers 11 are silicon dioxide SiO2 or silicon nitride Si3N4, and the refractive indices of these layers 16, 11 are 3.55 for Si, 1.47 for SiO2 and 1.8 2.0 for Si3N4. And a resist film 13 is formed on these buried layers 11 and the substrate 16, and in this condition the alignment with a photomask is performed. With this, the precision of the alignment can be maintained high.

Description

【発明の詳細な説明】 (産業上の利用分野〕 本発明は、半導体装置の製造プロセスのフォトリソグラ
フィー工程でフォトマスクとウェハーとのアラインメン
j〜(位置合せ)のために用いられるウェハー上に形成
されたアラインメントマークに関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for forming a photomask on a wafer used for alignment between a photomask and a wafer in a photolithography process of a semiconductor device manufacturing process. Regarding alignment marks.

〔従来の技術〕[Conventional technology]

従来のアラインメントマークの一例を第2図に示す。こ
のアラインメントマークは、単色光源を照明に用いる場
合に適したもので、図示のように基板6上に段差形成膜
1が配され、その上にレジスト3が塗布されている。こ
の結果、レジスト3の表面にも段差部5が形成されてい
る。
An example of a conventional alignment mark is shown in FIG. This alignment mark is suitable when a monochromatic light source is used for illumination, and as shown in the figure, a step forming film 1 is arranged on a substrate 6, and a resist 3 is applied thereon. As a result, a step portion 5 is also formed on the surface of the resist 3.

矢印4で示す方向に走査を行なって反射光を信号化する
と、段差部5で信号に強度の変化が生じるため、これを
微分することにより、パルス状の信号を得て、アライン
メントマークの位置を検出することとしている。
When scanning is performed in the direction shown by the arrow 4 and the reflected light is converted into a signal, the intensity of the signal changes at the stepped portion 5. By differentiating this, a pulse-like signal is obtained and the position of the alignment mark can be determined. We are planning to detect it.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のようなアラインメントマークでは、第3図に示す
ように、段差部のレジスト膜厚a、bが左右で異ったり
、また第4図に示すように段差部の斜面角α、βが左右
で異ったりして、このため、検出信号が第5図に′示す
ようになり、本来のアラインメントマークの中心位置S
1と信号処理による検出位置S2との間に誤差dが生じ
、アラインメントの精度が低下するという問題点がめっ
た。
In the above alignment mark, as shown in Fig. 3, the resist film thicknesses a and b at the step portion are different on the left and right sides, and as shown in Fig. 4, the slope angles α and β of the step portion are different on the left and right sides. As a result, the detection signal becomes as shown in Fig. 5, and the original center position S of the alignment mark is
1 and the detected position S2 by signal processing, which caused a problem that the accuracy of alignment decreased.

本発明の目的は、アラインメントの精度を高く維持する
ことができるアラインメントマークを提供することを目
的とする。
An object of the present invention is to provide an alignment mark that can maintain high alignment accuracy.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のアラインメントマークは、ウェハー表面に形成
されたトレンチと、該トレンチを埋める埋込み層とを有
し、該埋込み層は上記トレンチの周囲の層と異なる反射
率を有するものである。
The alignment mark of the present invention includes a trench formed on a wafer surface and a buried layer that fills the trench, and the buried layer has a reflectance different from the layers surrounding the trench.

〔作用〕[Effect]

上記のようなアラインメントマークを用いると、ウェハ
ー上を走査したとき、トレンチの埋込み層上とその周囲
の部分とでは光の反射率が異なるため、反射光に基く信
号を用いれば、アラインメントマークの位置を知ること
ができる。本発明のアラインメントマークには段差形成
膜を用いていないので、レジストの膜厚の差異や段差形
成膜の斜面角の差異によってアラインメントマーク検出
の精度が低下するといった問題がない。
When an alignment mark like the one described above is used, when the wafer is scanned, the reflectance of light differs between the buried layer of the trench and the surrounding area, so if a signal based on the reflected light is used, the position of the alignment mark can be determined. can be known. Since the alignment mark of the present invention does not use a step-forming film, there is no problem that the accuracy of alignment mark detection is reduced due to differences in the thickness of the resist or differences in the slope angle of the step-forming film.

〔実施例〕〔Example〕

第1図(a)は本発明一実施例のアラインメントマーク
の平面図、第1図(b)はその断面図でおる。
FIG. 1(a) is a plan view of an alignment mark according to an embodiment of the present invention, and FIG. 1(b) is a sectional view thereof.

図示のようにこのアラインメン1〜マークは、基板16
に設けられたトレンチ(溝)15と、1〜レンヂ15を
埋めた埋込み層11とを有する。埋込み層11はトレン
チ15の周囲の部分と同じ高さを有するように形成され
る。埋込み層11は、トレンチ15の周囲を形成する層
例えば基板16とは異なる反射率例えばより低い反射率
を有する。
As shown in the figure, the alignment marks 1 to 1 are on the substrate 16.
It has a trench 15 provided in the range 1 to 15, and a buried layer 11 filling the ranges 1 to 15. Buried layer 11 is formed to have the same height as the surrounding portion of trench 15 . The buried layer 11 has a different reflectivity, for example a lower reflectivity, than the layer forming the periphery of the trench 15, for example the substrate 16.

例えば、基板16がシリコン(S i )で必る場合、
埋込み層11はシリコン酸化物(Si02>またはシリ
コン窒化物(Si3N4)である。これらの層の屈折率
はS:が3.55、S i 02が1.47、Si3N
4が1.8〜2.0でおる。
For example, if the substrate 16 is made of silicon (S i ),
The buried layer 11 is silicon oxide (Si02) or silicon nitride (Si3N4).The refractive index of these layers is S: 3.55, Si02 1.47, and Si3N.
4 is between 1.8 and 2.0.

図示の例では、埋込み層11および基板16の上にレジ
スト膜13が形成され、この状態で、フォトマスクとの
アラインメン1〜が行なわれる。
In the illustrated example, a resist film 13 is formed on the buried layer 11 and the substrate 16, and in this state alignments 1 to 1 with a photomask are performed.

第1図(a)において、矢印14で示す方向に走査を行
なうと、走査線に沿う反射率の変化は第1図(C)の如
くで、反射光の強さは反射率に比例する。従って、走査
に伴って1qられる信号を微分すると、第1図(d)に
示すように埋込み層11とそれに隣接する部分との界面
部分でパルス状に立上る信号が得られる。
In FIG. 1(a), when scanning is performed in the direction indicated by arrow 14, the reflectance changes along the scanning line as shown in FIG. 1(c), and the intensity of reflected light is proportional to the reflectance. Therefore, by differentiating the signal 1q caused by scanning, a signal that rises in a pulse-like manner at the interface between the buried layer 11 and its adjacent portion is obtained, as shown in FIG. 1(d).

埋込み層11がそれに隣接する部分と同じ高さに形成さ
れているので、その上に形成されたレジスト13の膜厚
は略一定となる。従って、従来のように膜厚の差による
アラインメントの誤差は生じない。また、従来のように
段差形成膜を用いないので、その斜面角の差異によるア
ラインメン1〜の誤差も生じない。
Since the buried layer 11 is formed at the same height as the portion adjacent to it, the thickness of the resist 13 formed thereon is approximately constant. Therefore, alignment errors due to differences in film thickness do not occur as in the prior art. Further, since a step forming film is not used as in the conventional method, errors in alignment 1 to 1 due to differences in slope angles do not occur.

第6図は本発明の他の実施例を示したものである。この
実施例では、埋込み物質11が溝の中だけなって、全面
に薄く膜状に形成されている。このようにすると、薄膜
状の部分11aでは多重干渉が起こり、溝の部分とでは
総合的な反射率が異なる。従って、この場合にも、溝の
部分をアラインメントマークとして用いることができる
FIG. 6 shows another embodiment of the invention. In this embodiment, the buried material 11 is formed only in the groove and is formed as a thin film over the entire surface. If this is done, multiple interference will occur in the thin film portion 11a, and the overall reflectance will be different from that in the groove portion. Therefore, in this case as well, the groove portion can be used as an alignment mark.

第7図は本発明のざらに他の実施例を示したものである
。この実施例では、溝を埋込んだ後、その上にBPSG
の如き絶縁膜17が形成されている。このようにしても
、第6図の実施例と同様の効果がおる。
FIG. 7 roughly shows another embodiment of the present invention. In this example, after filling the trench, the BPSG
An insulating film 17 as shown in FIG. Even in this case, the same effect as the embodiment shown in FIG. 6 can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、基板に溝を形成し、その
周囲では屈折率の異なる物質で埋めることとしたので、
アラインメントマーク部に段差が生じない。従って、段
差部にお【プるレジストの膜厚の差や従来のように段差
形成膜の斜面角の差異によって、アラインメン1〜の誤
差が生じることがなくアラインメン1〜を高精度で行な
うことができる。
As described above, according to the present invention, a groove is formed in the substrate and the surrounding area is filled with a material having a different refractive index.
No step occurs in the alignment mark section. Therefore, alignment 1~ can be performed with high precision without causing errors in alignment 1~ due to differences in the film thickness of the resist applied to the step portion or differences in the slope angle of the step forming film as in the conventional method. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す図、 第2図は従来のアラインメントマークの一例を示す平面
図および断面図、 第3図および第4図は第2図のアラインメントマークに
おけるアラインメントの誤差を生ずる原因となるレジス
ト膜厚差および段差形成膜の斜面角の差異を示す断面図
、 第5図は第3図や第4図の場合に生ずる信号波形を示す
図、 第6図および第7図は本発明の他の実施例を示す断面図
でおる。 11・・・埋込み層、15・・・溝、16・・・基板。 特許出願人  沖電気工業株式会社 代理人弁理士   鈴  木  敏  明・(争台 蝉 15:IL (C) (ct) l:段i形FX膿 2:マスクのル 3:Lシスト 4:走1J聚方間 5:珪差仔 6:基板 従来の了2インメントマーク 茶2冨 トンスト94戸不−玖 牟3 因 44ffi角O子一致 羊4凪 沖灸巳rA五 羊5日
Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a plan view and a sectional view showing an example of a conventional alignment mark, and Figs. 3 and 4 are alignment errors in the alignment mark of Fig. 2. 5 is a cross-sectional view showing the difference in the resist film thickness and the difference in the slope angle of the step forming film, which cause the difference in thickness. FIG. 5 is a diagram showing the signal waveform generated in the case of FIGS. 3 and 4. The figure is a sectional view showing another embodiment of the present invention. 11... Buried layer, 15... Groove, 16... Substrate. Patent applicant: Oki Electric Industry Co., Ltd. Patent attorney: Toshiaki Suzuki (Soudaisemi 15: IL (C) (ct) l: Stage I-type FX Pus 2: Mask Le 3: L Cyst 4: Sori 1J Jukata 5: Keisatsu 6: Board Conventional Ryo 2 Inment Mark Tea 2 Tomiton Strike 94 Doors Fu-Kamu 3 In 44ffi Corner O Lamb Match Sheep 4 Nagi Oki Moxibustion rA Go Sheep 5th

Claims (1)

【特許請求の範囲】  半導体装置の製造プロセスのフォトリソグラフィー工
程でフォトマスクとウェハーとのアラインメントのため
に用いられる、ウェハー上に形成されたアラインメント
マークにおいて、 ウェハー表面に形成されたトレンチと、 該トレンチを埋める埋込み層とを有し、 該埋込み層は上記トレンチの周囲の層と異なる反射率を
有する ことを特徴とするアラインメントマーク。
[Claims] An alignment mark formed on a wafer and used for alignment between a photomask and a wafer in a photolithography step of a semiconductor device manufacturing process, comprising: a trench formed on a surface of the wafer; and the trench. and a buried layer filling the trench, the buried layer having a reflectance different from that of layers surrounding the trench.
JP62011381A 1987-01-22 1987-01-22 Alignment mark Pending JPS63181317A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62011381A JPS63181317A (en) 1987-01-22 1987-01-22 Alignment mark

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62011381A JPS63181317A (en) 1987-01-22 1987-01-22 Alignment mark

Publications (1)

Publication Number Publication Date
JPS63181317A true JPS63181317A (en) 1988-07-26

Family

ID=11776434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62011381A Pending JPS63181317A (en) 1987-01-22 1987-01-22 Alignment mark

Country Status (1)

Country Link
JP (1) JPS63181317A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5733801A (en) * 1993-12-21 1998-03-31 Kabushiki Kaisha Toshiba Method of making a semiconductor device with alignment marks

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5733801A (en) * 1993-12-21 1998-03-31 Kabushiki Kaisha Toshiba Method of making a semiconductor device with alignment marks

Similar Documents

Publication Publication Date Title
US20050242448A1 (en) Overlay key, method of manufacturing the same and method of measuring an overlay degree using the same
JPH0210716A (en) Method of forming alignment mark and semiconductor having alignment mark
JPS6245028A (en) Formation of positioning mark on wafer
US6313542B1 (en) Method and apparatus for detecting edges under an opaque layer
JPH0663758B2 (en) Pattern measurement method
JPS63181317A (en) Alignment mark
JP2000097648A (en) Device and method for measuring difference in level
JP3044040B1 (en) Material Layer Thickness and Chemical-A Method for Determining the End of Mechanical Polishing
JPH0653552A (en) Formation of optical characteristics measuring groove
JP2000252339A (en) Method for measuring depth of groove of semiconductor device
JPH06324475A (en) Reticle
JPH08321533A (en) Inspection method of position deviation of alignment mark
US6750554B2 (en) Mark configuration, wafer with at least one mark configuration and method for the fabrication of at least one mark configuration
JP3111996B2 (en) Method for manufacturing semiconductor device
JPS63124412A (en) Semiconductor device
KR20020002653A (en) Alignment mark for exposure process
KR19980077550A (en) Manufacturing method of alignment key of semiconductor device
KR100342875B1 (en) Method for forming a overlay vernier
JPH03142820A (en) Manufacture of semiconductor device
JPH0569940U (en) Semiconductor device
JPH0779073B2 (en) Wafer alignment mark
JP2000304690A (en) Optical measuring device
JPH01118704A (en) Pattern for measuring size
KR20010066143A (en) Method for measuring trench depth of semiconductor device
JPH0644547B2 (en) Method for manufacturing semiconductor device