JPS63181164A - Disk servo device - Google Patents

Abstract

PURPOSE:To attain the optimum control of disk drive by applying a digital data processing to a phase difference and speed obtained by the rotation of the disk and synthesizing the phase difference data and speed data at an optional ratio so as to obtain an optimum servo data. CONSTITUTION:A phase difference detection means (phase difference counter 38) detects a phase difference between a synchronizing signal and a reference synchronizing signal, and a 1st digital filter 46 obtains the phase difference data of the required frequency component and gain from the said phase difference data. A speed detection means (speed counters 34, 40) detects, digital speed data from speed information, a 2nd digital filter 48 obtain speed data with the required frequency component and gain. A data conversion means (level shift circuits 50, 52 and adder circuit 54) sets and synthesizes the mixed ratio digitally to each obtain data to obtain a servo output. Thus, the rotational linear velocity of the disk optimum thereto is obtained by the synthesis data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a disk servo device suitable for controlling the rotation of a motor of an optical disk playback device or the like.

[Conventional technology]

Conventionally, in an optical disk playback device that plays back music information recorded on a compact disk (CD), etc., as shown in FIG. Linear velocity (CL
V) A servo device is used.

Pickup 6 that uses laser light as a detection medium from CD4
The RF multiplied signal detected through the RF signal is applied to the phase difference detection circuit 8 and the speed detection circuit IO.

The phase difference detection circuit 8 outputs a phase difference signal Ph representing the phase difference between the synchronization signal detected from the CD 4 and the reference synchronization signal by comparing the two, and the speed detection circuit 10
The period of the synchronization signal is measured, and a speed signal Vr representing the speed is output from the measured value.

Then, the phase difference signal Pk is passed through a filter 12 made up of a resistor and a capacitor, and the speed signal (2) is similarly passed through a filter 14 made up of a resistor and a capacitor and added to an adder circuit 16 made up of an operational amplifier and a resistor. be done.

Since the addition output contains a carrier component, after passing through a filter 18 that removes it, the output is added to the driver 20, and the rotational speed of the motor 2 is controlled by the drive output generated by the driver 20.

[Problem that the invention seeks to solve]

Incidentally, in such a disk servo device, a filter 12.14 is provided before the addition circuit 16 to set the addition gain and frequency characteristics, and a filter 18 is provided on the addition output side to remove carrier components. The filters 12 and 14 are constructed from external components such as resistors and capacitors, and the gain and frequency characteristics are set by varying the resistors and capacitors.

Further, the filter 18 for removing carrier components must also be constructed of resistors and capacitors, and the settings of its gain and frequency characteristics must be varied, resulting in a large-scale circuit.

Therefore, the present invention aims to omit external components such as resistors and capacitors through analog processing, and to obtain an optimal control state.

[Means for solving problems]

As shown in FIG. 1, the disk servo device of the present invention includes a phase difference detection means that compares a synchronization signal reproduced from a disk (CD4) with a reference synchronization signal and detects the phase difference between the two as a digital value. (phase difference counter 38), a first digital filter 46 that obtains phase difference data of an arbitrary frequency component and arbitrary gain from the phase difference data detected by the phase difference detection means, and a first digital filter 46 that obtains phase difference data of an arbitrary frequency component and an arbitrary gain from the phase difference data detected by the phase difference detection means, a speed detection means (first or second speed counter 34, 40) that detects speed data as a digital value;
A second digital filter 48 obtains speed data of an arbitrary frequency component and an arbitrary gain from the speed data detected by the speed detection means, and mixes the speed data with the data obtained from the first and second digital filters 46 and 48. Data conversion means (level shift circuit 5) that sets and mixes the ratio
0.52 and an adder circuit 54).

[For production]

The phase difference detection means (phase difference counter 38) detects the phase difference between the synchronization signal and the reference synchronization signal as a digital value, and the first digital filter 46 extracts the necessary frequency component and gain position from the phase difference data. Obtain phase difference data. Also, a speed detection means (first or second speed counter 34.
40) detects speed data as a digital value from the speed information detected from the disk, and the second digital filter 48 obtains speed data with necessary frequency components and gains from the speed data.

Then, data conversion means (level shift circuits 50 and 52
and an adder circuit 54) sets a mixing ratio as a digital value for each data obtained by the first and second digital filters 46, 48, and synthesizes the data to obtain a servo output. Therefore, the optimum rotational linear velocity of the disk can be obtained by combining the phase difference data and velocity data.

〔Example〕

FIG. 1 shows an embodiment of a disk servo device of the present invention.

The rotation speed of the motor 2 that rotates the CD 4 is detected by a pickup 6 that uses laser light as a detection medium, and is added to a phase locked loop (PLL) 24 together with an RF multiplied signal waveform shaping circuit 22 obtained by the pickup 6. ,
In the waveform shaping circuit 22, the RF multiplied signal E F M (E
right to Fourteen Modulation
n) signal is detected, and the PLL 24 obtains a synchronized clock signal Sc. The EFM signal has a minimum bit length of 3T.
It is a pulse signal having a time width from IT to the longest pitch IT.

A synchronization pattern detection circuit 26 is installed as a synchronization signal detection means for detecting a synchronization signal from the RF multiplied signal.The synchronization pattern detection circuit 26 uses a synchronization clock signal oscillated by an oscillator 30 using a crystal oscillator 28 synchronization signal S from the EFM signal. Extract.

Synchronization signal S. is the synchronization signal S together with the phase difference detection circuit 32 that detects the phase difference with the reference synchronization signal S. is added to a first speed counter 34 for obtaining speed data from. The reference synchronization signal SE is a clock pulse CL oscillated by an oscillator 30, which is converted into a synchronization signal S by a frequency divider 36. The phase difference detection circuit 32 compares the synchronization signal So (!: base reference synchronization signal S color) and generates a phase difference signal SP representing the phase difference between the two.

The phase difference signal S is detected by a phase difference counter 3 as a digital phase difference detection means for detecting the phase difference as a digital value.
The phase difference can be quantitatively obtained as phase difference data D by counting the synchronized clock signal Sc added to the PLL 24 from the PLL 24.

The first speed counter 34 outputs first speed data Dv+ as digital data representing the rotational speed of the motor 2 by counting clock pulses CL from the oscillator 30 based on the synchronization signal S0.

In addition, a second speed counter 34 installed relative to the first speed counter 34
The speed counter 40 of the EFM signal has the longest bit 11
The second speed data Dv□ is output by counting the clock pulses CL for the time width representing T.

The first and second speed data DV+, DV□ are applied to a multiplexer (MPX) 42, and the judgment output J of the judgment circuit 44 is based on the count output of the speed counter 40.

Either one is selected by the MPX 42 and output. In other words, the second bit representing the time width of the longest bit 11T
Compare the speed data Dv
is output, and the maximum focus is 11T within the reference time range.
If there is no time width, the second velocity data DV2 is output based on the determination output J0.

The phase difference data D and the first or second speed data DVI% Dvz obtained in this way are applied to the first and second digital filters 46, 48 to have the necessary frequency components and gains. phase difference data D. ,
Speed data D and l are obtained.

The phase difference data D0 and speed data DI+ are added to level shift circuits 50 and 52 as ratio setting means for setting the mixing ratio of both data, and after setting the necessary ratio, the data D0°, DRO is added to an adder circuit 54 as a data synthesizing means. That is, the level shift circuits 50, 52 and the adder circuit 54 constitute data conversion means for obtaining necessary servo data D0 from the phase difference data D0 and speed data DR as original data.

Servo data D having a phase difference component and a velocity component obtained by the adder circuit 54. A digital pulse width modulation circuit (PWM circuit) 56 installed as a signal conversion means for converting into a drive control signal for the motor 2 generates a PWM signal by comparing it with reference data such as reference triangular wave data or sawtooth wave data. get the output. This pulse width modulation output is obtained as continuous pulses with a time width that compensates for the phase difference on the time axis.

This PWM output is applied to the driver 58, and the drive output generated by the PWM output is applied to the motor 2.
Servo data D that takes into account both phase difference information and velocity information. The rotational speed of the motor 2 is controlled to be constant.

FIG. 2 shows a specific example of the configuration of the level shift circuits 50 and 52.

For example, the phase difference data D0, which is the original data added from the digital filter 46 side, is transmitted to the bit shifter 60.
, the value "1" of the lower digit is transferred to the adjacent upper digit, and the data value is transferred. Figure 3 shows an example of its operation, where 0.1.2... is a 3-bit binary number ro OOJ, rooIJ, ro
When bit shifting is performed for 10J..., as shown by the arrow, ro OOJ becomes ro 00J, roo
lJ is roloJ, ro 10J is rlooj...
If you look at it in decimal notation, "0" is "0".
”, rlJ is changed to “2”, “2” is changed to “4”, and so on. Looking at this as data, the phase difference data D0 as original data is changed to phase difference data DQ' as other data.

This phase difference data D0' is added to the adder circuit 62 from the pit shifter 60, and is added to the output data of the adder circuit 62 which has been delayed through the delay circuit 64, and is converted into arbitrary changed data I)oo with a set ratio. The signal is taken out from the delay circuit 64.

Such data conversion is similarly performed for the speed data DR, and a desired addition ratio is set for each data D0° and DRO.

[Effects of the Invention] According to the present invention, the phase difference and velocity obtained by the rotation of the disk are processed using digital data, and each phase difference data and velocity data are synthesized at an arbitrary ratio, thereby obtaining optimal servo data. It is possible to optimally control disk rotation by obtaining the following information, and external components such as resistors and capacitors can be omitted due to analog processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the disk servo device of the present invention, FIG. 2 is a block diagram showing a specific configuration example of the level shift circuit of the disk servo device shown in FIG. 1, and FIG. FIG. 2 is a diagram showing the operation of a bit shifter in the level shift circuit shown in FIG. 2, and FIG. 4 is a diagram showing a conventional disk servo device. 4...CD (disk) 34...First speed counter (first speed detection means) 38...Phase difference counter (phase difference detection means) 40...
・Second speed counter (second speed detection means) 46...First digital filter 48...Second digital filter 50.52...Level shift circuit (data conversion means)

Claims (1)

[Claims] Phase difference detection means for comparing a synchronization signal reproduced from a disc with a reference synchronization signal and detecting a phase difference between the two as a digital value; and phase difference data detected by the phase difference detection means. The first step is to obtain phase difference data of any frequency component and any gain from
A digital filter, a speed detection means for detecting speed data as a digital value from the speed information detected from the disk, and speed data of an arbitrary frequency component and an arbitrary gain is obtained from the speed data detected by the speed detection means. A disk servo device comprising: a second digital filter; and data converting means for setting and synthesizing data obtained from the first and second digital filters at an arbitrary ratio.