JPS63177458A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To easily manufacture a semiconductor memory device whose structure can enhance the dimensional accuracy or the like by a method wherein grooves are made in such a way that they are arranged to be adjacent to each other via a word line and a gate insulating film and that they reach a capacitor or a bit line while semiconductor regions are formed inside the grooves so as to form channel regions. CONSTITUTION:When a semiconductor memory device is manufactured in such a way that memory devices composed of one transistor and one capacitor are arranged in a matrix form, word lines 13 are formed in the direction crossing a bit line 11 at the upper part of capacitors or the bit line 11; insulating layers 14 are formed on the word lines 13; grooves 15 are formed in such a way that they are arranged to be adjacent to each other via the word lines 13 and gate insulating films 16 and that they reach the capacitors or the bit line 11. After that, semiconductor regions 17 are formed inside the grooves 15; channel regions 19 are formed in the semiconductor regions 17; the bit line or the capacitors 20-22 are formed in such a way that they are connected to the semiconductor regions 17. During the above process, if the capacitors are formed on the side of a substrate 10, the bit line is to be formed on the upper part.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor memory device such as a DRAM (dynamic random access memory).

B1 Summary of the Invention The present invention provides a method for manufacturing a semiconductor memory device in which memory elements each consisting of one transistor and one capacitor are arranged in a matrix, in which the capacitor or the bit is adjacent to a word line with a gate insulating film interposed therebetween. By forming a groove that reaches a line, forming a semiconductor region in the groove, and providing a channel region, dimensional accuracy can be improved.

C1 Prior Art As an example of a conventional semiconductor memory device, a semiconductor memory device having a structure as shown in FIG. .

Here, an example of a conventional semiconductor memory device will be briefly described with reference to FIG. 3. A groove-shaped capacitor 112 is formed in a P-type semiconductor substrate or well region 134. Insulation N152
The polycrystalline silicon layer 150 and the N-half type source region 148, which are separated by a polycrystalline silicon layer 150, are used as electrode plates. An N-half type drain region 120 is formed above the N-half type source region 148 via a semiconductor region that becomes a channel, and this N-half type drain region 120 functions as a bit line in the DRAM. . The word line is a polycrystalline silicon layer 114 that fills the trench above the polycrystalline silicon layer 150, and the channel of the transistor in this cell is vertical. Note that the N-type drain region 120 is formed in self-alignment with the field oxide film 136.

D2 Problem to be solved by the invention This so-called trench capacitor (capacitor 112
) and whose channel direction is perpendicular to the substrate, the area occupied by each cell can be reduced accordingly, and high integration can be achieved.

However, when manufacturing a semiconductor memory device as shown in FIG. 3, a problem arises in that sufficient dimensional accuracy cannot be obtained due to the process and other aspects.

That is, in order to obtain a vertical channel, a drain region 148 is formed on the sidewall of the trench.
In order to obtain the drain region 148, for example, it is necessary to dig a trench in two stages.
If the position of is shifted, for example, in the vertical direction, the channel length of the transistor will vary. Furthermore, the accuracy of the positions of the source region 120 and the drain region 148 can only be obtained through a plurality of steps, and the manufacturing process is complicated.

Further, due to its structure, the capacitor 112 protrudes into the semiconductor substrate or well region 134, and when elements are arranged in high density, problems such as leakage and punch-through occur.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a method for manufacturing a semiconductor memory device that can easily manufacture a semiconductor memory device having a structure that improves dimensional accuracy.

Means for Solving the E0 Problem The present invention provides a method for manufacturing a semiconductor memory device in which memory elements each consisting of one transistor and one capacitor are arranged in a matrix. a step of forming a word line in a direction intersecting the word line, a step of forming an insulating layer on the word line, and a step of forming a word line adjacent to the word line via a gate insulating film and reaching the capacitor or the above By)&%. A semiconductor memory comprising the steps of forming a groove, forming a semiconductor region in the groove and forming a channel region in the semiconductor region, and forming the bit line or capacitor by connecting to the semiconductor region. The above-mentioned problems are solved by a method of manufacturing the device.

F1 Effect First, the capacitor of the memory element of the semiconductor memory device to be manufactured may be formed on the semiconductor substrate side, or may be formed on the transistor. The capacitor and bit line of each storage element are arranged vertically opposite to each other via the transistor of the storage element.

As described above, the present invention arranges a word line, forms an insulating layer, and forms a groove adjacent to the word line, thereby directly using the groove as an active region of a transistor of a memory element. be able to. That is, by forming a semiconductor region in a trench adjacent to a word line, a transistor whose channel direction is in the vertical direction can be obtained. At this time, the semiconductor region in the trench is formed by, for example, a selective epitaxial growth method, so that the source/drain region can be easily formed while growing, and the dimensions thereof can be highly controlled. Become something.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

The method for manufacturing a semiconductor memory device according to this embodiment allows a semiconductor memory device consisting of fine memory elements to be easily formed due to its process advantages. Below, Figure 1a to Figure 18
The process will be explained with reference to FIGS. 2a to 2e.

fat As shown in FIG. 1A, an N-half type impurity for forming a bit line is introduced into the vicinity of the surface of a P-type semiconductor substrate 10, for example, to form an N-half type impurity region 11. The planar shape of this N half-type impurity region 11 is a pattern as shown in FIG.
1 becomes a plurality of parallel lines that function as bit lines. Note that the N-half type impurity region 11 may have a bulging pattern at the connection portion with the transistor. Furthermore, instead of first forming the N-type impurity region 11 that will become the bit line, it is also possible to first form the impurity region that will become the capacitor of the storage element.

Next, as shown in No. 111; 21b, an insulating layer 1 such as a silicon oxide layer is formed on the semiconductor substrate 10 in which the N half-type impurity region 11 is introduced in the above-mentioned parallel line pattern.
A polycrystalline silicon layer 13 is further formed on the entire surface. This polycrystalline silicon layer 13 is used as a word line, and as shown in FIG.
The half-type impurity region 11 is etched into a pattern having a plurality of parallel lines in a direction intersecting with it. Here, the thickness 11 of this polycrystalline silicon layer 13 is the length of the gate electrode of the transistor of the memory element, as will be described later. You will be able to obtain

(C) After the polycrystalline silicon layer 13 serving as the word line is formed, the surface of the polycrystalline silicon N13 is oxidized, and as shown in FIG. 1C, a glabellar insulation layer 14 is formed on the entire surface. Then, the polycrystalline silicon layer 13 is completely covered. Then, the interlayer insulating layer 14 and the insulation M12 in the region adjacent to the polycrystalline silicon layer 13, which will become the word line, are removed to form the groove portion 15. This groove portion 15 can be formed, for example, by the tE method, and may be formed at a position with a thin gate oxide film 16 interposed between it and the polycrystalline silicon layer 13, or once separated from the polycrystalline silicon layer 13.
is exposed inside the trench and oxidized the gate again to form gate oxide film 1.
Form it so as to obtain 6.

By forming this trench 15, the N-type impurity region 11 formed at the bottom is exposed at the bottom of the trench 15.

In FIG. 2C, the position of such a trench 15 is shown by a broken line, and the N+ type impurity region 11 is adjacent to the polycrystalline silicon layer 13, which will become a word line, with a gate oxide film 16 interposed therebetween.
A groove portion 15 is formed at the top. IIW1 of the surface of the polycrystalline silicon Ji113 of this groove 15 is the channel width of the current transistor, and its dimensional accuracy is
It depends only on the dimensional accuracy of 5. Therefore, by increasing the dimensional accuracy of the groove portion 15, the dimensional accuracy of the semiconductor memory device can be easily increased.

(d+ As shown in FIG. 1d, the groove 1 is adjacent to the polycrystalline silicon layer 13 that becomes the word line via the gate oxide film 16, and the N half-type impurity region 11 faces the bottom.
5, a semiconductor region 17 is formed.

This semiconductor region 17 is formed by a selective epitaxial growth method, and is gradually grown as a single crystal from the bottom of the trench 15 using the exposed N half-type impurity region 11 as a seed. This selective epitaxial growth method uses, for example, a mixture of silane gas and hydrochloric acid gas, and
During the growth, the gas is switched and the semiconductor region 17 is
Then, a source region 18, a channel region 19, and a drain region 20 can be formed. Source area 18 here
The drain region 20 is an N-type high concentration impurity region.

Incidentally, in the semiconductor region 17 formed by such a selective epitaxial growth method, each region is formed with good dimensional accuracy. That is, the channel width of this transistor is the width w1 of the semiconductor region 17 filling the trench 15, and the channel length is also equal to the width w1 of the semiconductor region 17 filling the trench 15.
8. Since the drain region 20 is formed with good controllability, it is stable, and variations in each element can be extremely small. In addition, the groove portion 15 is simply formed adjacent to the polycrystalline silicon layer 13 that becomes the word line, and the groove digging process does not have to be performed multiple times, making it possible to easily avoid process complexity. Can be done.

Incidentally, a plan view corresponding to FIG. 1d is shown in FIG. 2d.

tel After the semiconductor region 17 is further grown and formed, a capacitor is formed on the top of the semiconductor region 17 so as to protrude and connect to the tatrain region 20, as shown in FIG. 1e.

In the structure of the capacitor, an insulating layer 21 serving as a dielectric layer is formed above the drain region 20, and a polycrystalline silicon layer 22 serving as one of the counter electrodes is further formed above the insulating layer 21. Note that the capacitor may be a PN capacitor, and its dielectric layer may have a nitride film sandwiched therebetween. Alternatively, the drain regions 20 may be sufficiently grown by selective epitaxial growth to bond each drain region 20 together, and then the drain regions 20 may be etched to separate each element.

Note that, as described above, when a capacitor is first formed on the semiconductor substrate 10 side, the above-mentioned polycrystalline silicon layer 1
A parallel bit line is formed in a direction intersecting 3 and connected to the drain region 20.

FIG. 2e is a plan view corresponding to FIG. 1e, and as shown in FIG. is adjacent to the intersection with the impurity region 11, and the N-half type impurity region 1
A semiconductor region 17 whose channel direction is in the vertical direction is formed in a region adjacent to the polycrystalline silicon layer 13 on the semiconductor region 1,
As described above, memory elements can be arranged at high density through a simple process.

As described above, in this embodiment, the polycrystalline silicon layer 13 serving as the word line is formed, and the groove 15 is formed adjacent to the polycrystalline silicon layer 13 on the bit line (or below the via line).
Since the semiconductor region 17 is formed by, for example, selective epitaxial growth, the source/drain region 18.2o can be easily obtained, and its dimensional accuracy is high, eliminating problems such as channel length variations between devices. will be easily solved.

H1 Effects of the Invention In the method for manufacturing a semiconductor memory device of the present invention, as described above, a trench is formed adjacent to a word line and a semiconductor region is formed in this, so the dimensional accuracy of each part of the device is Although the dimensional accuracy can be improved at the same time, the process is not complicated in any way, and it becomes possible to easily obtain a highly integrated semiconductor memory device.

[Brief explanation of the drawing]

1a to 1e are cross-sectional views of a semiconductor substrate, etc. for explaining an example of the method for manufacturing a semiconductor memory device according to the present invention according to the steps, and FIGS. 2a to 2e are cross-sectional views of a semiconductor substrate, etc. 1
FIG. 3 is a plan view of a semiconductor substrate, etc., for explaining an example of the method for manufacturing a semiconductor memory device according to the present invention according to its steps, corresponding to FIGS. It is a sectional view showing an example. 10... Semiconductor substrate 11... N half-type impurity region 12... Insulating layer 13... Polycrystalline silicon layer 14... Interlayer insulating layer 15... Groove 16... Gate oxide film 17 ...Semiconductor region 18...Source region 19...Channel region 20...Drain region 21...Insulating layer 22...Polycrystalline silicon layer Patent Applicant Sony Corporation Representative Patent Attorney Small Foam Mima Ei Tamura - Figure 1a Figure 1S Figure 1C Figure 1d Figure 1e Figure 2d Figure 2e

Claims (1)

[Claims] In a method for manufacturing a semiconductor memory device in which memory elements each consisting of one transistor and one capacitor are arranged in a matrix, words are formed above the capacitor or above the bit line in a direction crossing the bit line. a step of forming a line, a step of forming an insulating layer on the word line, a step of forming a groove adjacent to the word line via a gate insulating film and reaching the capacitor or the bit line, and inside the groove. 1. A method for manufacturing a semiconductor memory device, comprising: forming a semiconductor region in the semiconductor region; forming a channel region in the semiconductor region; and forming the bit line or capacitor connected to the semiconductor region.