JPS63175589A - Split display processor for color picture information - Google Patents

Abstract

PURPOSE:To concentrate the display of a CRT display system comprising a NTSC system and RGB system by picking up color component information read out of >=1 set of NTSC color information input/output timing correction means and Si1 set of RGB color information input/output timing correction means selectively. CONSTITUTION:NTSC color information input/output timing correction means 801a, 801b are formed as a set (a) and RGB color information input/output timing correction means 802a, 802b are formed as a set (b), (a, b are respectively 1 or over), and a color information selection means 820 is provided, which picks up selectively the read color component information of color information read timing control means 803 generating picture information pickup information corresponding to each split screen obtained by (a+b) division of the display screen of one field and the a set of NTSC color information input/output timing correction means 801a, 801b and a, b set of RGB color information input/output timing correction means 802a, 802b and outputs the result to the color CRT display. Thus, the scfreen split processing is facilitated and the display concentration on one set of the CRT display is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color split display that displays a multi-color screen on one color CRT display, and in particular,
[Prior Art] A CRT color display system is related to a split display processing device for displaying the above N, TSC color screen and one or more RGB color screens on an RGB color CRT display in a screen-divided manner. It is a display system consisting of peripheral circuits for driving it, and there are two main systems.

One of them is the NTSC system, which is typified by industrial ITVs, and this is a half-tone moving image display, which has the advantage of allowing images like so-called color photographs to be viewed on the moving image screen. The other type is the RGB method, which is typified by CRT displays for computers.This is a binary still image display, and so-called binary information (graphs, characters, illustrations, etc.) can be clearly seen in a still state. It has the advantage of being able to These ITV CRT displays and computer output CRT displays are highly sophisticated both technically and economically, and are used extremely widely in various fields.

[Problem that the invention seeks to solve]

However, since these conventional CRT displays simply reproduce incoming video signals as images, it is literally impossible to display more than one type of image on one screen at the same time. In places where large-scale monitoring is required, such as industrial, chemical, and steel plants, it is necessary to install a number of CRT display systems equal to the number of images required, resulting in an increase in space occupancy, power consumption, etc., and maintenance costs. Because of the above problems, it is desirable to centralize CRT display systems.

Also, for example, meters at the site can be photographed using an ITV and displayed on a CRT display for remote meter monitoring, and the site can be photographed using another ITV and displayed on a CRT display for site monitoring. The output (graphs, numerical tables, information, etc.) is displayed on a CRT display for commands or status notification, and the operation panel is also equipped with a CRT display for input. are often provided in one place, especially CR for NTSC and RGB systems.
It is desirable to centralize the T display system.

An object of the present invention is to consolidate the display of NTSC and RGB CRT display systems onto a single CRT display.

[Means for solving problems]

In order to achieve the above object, the present invention provides color division display information of the NTSC system and RGB system for televisions, computer displays, etc. each arriving at independent timings.
It is displayed on one screen of a video projection system by dividing the screen into areas. In the case of split display in this way, the information amount of one frame or field of video information,
If the amount of information in one frame, frame, or field of a color CRT display to be divided is the same, the video information is compressed to [1/number of divisions], or one frame or field of video information is compressed to [1/number of divisions]. /number of divisions] only the video information in the area needs to be extracted. However, in any case, the information on each divided plane on the divided display screen becomes coarse or the amount of information decreases. Recently, CRT displays with high quality and high image quality are using the NTSC system (ITV).
4 screens of video signals, or 4 computer output screens of about 2000 characters in RGB (computer display) format.
can be displayed on the screen without significantly reducing the resolution. Therefore, in a preferred embodiment of the invention, such N
Targeting TSC and RGB CRT displays, four screens are divided into one screen and displayed on a high-quality CRT display.

In this way, deterioration in the amount or quality of information due to screen division is avoided.

By the way, a plurality of video signal sources (I
Since screen information from TV cameras, computer outputs, etc.) is divided and displayed on one screen, the video signals from each video signal source are synchronized and synthesized into one screen on the CRT display for output (split display). must give.

In order to do this, in the present invention, three field memories are set as one set, and one set] is assigned to each of the three types of NTSC color component information.
Three sets of field memories, three field memories in each set are sequentially designated for writing on a field-by-field or frame-by-frame basis in synchronization with the NTSC color component information, and one of the field memories not designated for writing is designated for writing. read/write designating means for specifying reading, color information write address designating means for providing write address data in synchronization with NTSC color component information to field memory designated for writing, and field memory designated for reading; NTSC color information input/output timing correction means including a color information readout address designating means for providing readout address data based on a color information output synchronization signal; and one set of three field memories, and RGB color component information. 3 sets of field memories, one set for each of the 3 types, and 3 field memories in each set are designated for writing sequentially in frame or field units in synchronization with RGB color component information, and designated for writing. read/write designation means for designating one of the field memories that are not being read for reading; color information write address designation means for providing write address data in synchronization with RGB color component information to the field memory that is designated for writing; 5 sets of RGB color information input/output timing correction means, including a color information readout address designation means for supplying readout address data based on a color information output synchronization signal to a field memory designated by the field memory; a. b is 1
The above, further comprising a color information read timing control means for generating the color information output synchronization signal and generating image information extraction information corresponding to each divided plane obtained by dividing the display plane of the L field into a+b; and Based on the image information extraction information, the readout color component information of the a set of NTSC color information input/output timing correction means and the set of RGB color information input/output timing correction means is selectively extracted and output to a color CRT display. A color image information division display processing device is configured, comprising: a color information selection means for selecting a color image;

In the preferred embodiment of the present invention, the a+
Let b=4. That is, the number of screen divisions is set to four.

[Effect]

For ease of explanation and understanding, a+b=4. a=2. b
= 2, color video signals arrive from NTSC ITV cameras 1 and 2, and RGB signals arrive from dividers 1 and 2.
A mode in which color image information arrives will be explained.

NTSC video signals are transmitted to ITV cameras 1 and 2.
In each of the NTSC color information input/output timing correction means 1 and 2, the read/write designation means specifies read/write designation for each of the three field memories to which one set is assigned to each of the color component information (three types). The means sequentially specifies writing in synchronization with field updates of color component information, and the color information write address designation means designates write addresses in synchronization with color component information. As a result, each of the color component information (three types) is sequentially written into one set of three field memories.

The read/write designation means designates the field memory that is not designated for writing in one set for reading, and the color information read address designation means gives a read address based on the color information output synchronization signal, so that the field memory is not designated for writing. The color component information is read out in synchronization with the output synchronization signal.

Similarly, in the RGB color information input/output timing correction means 1 and 2 that receive RGB color component information from the computers 1 and 2, each of the color component information is synchronized with the update of the input information field. The data is sequentially written into one set of three field memories, and read out from field memories not designated for writing in synchronization with the output synchronization signal.

Therefore, in both the NTSC and RGB color information input/output timing correction means, the input timings are inconsistent and synchronized with the input information, but the output timings are consistent and synchronized with the output synchronization signal. Since this output synchronization signal is generated by the timing control means and given to each timing correction means, the output timing is the same for all the timing correction means. This timing control means generates image extraction information that divides the display surface of one field into four, and the color information selection means extracts the color information output by each timing correction means based on this extraction information. One field of the color information extracted by the selection means based on the output synchronization signal becomes a screen in which four screens, the output screens of the ITV cameras 1 and 2 and the output screens of the computers 1 and 2, are arranged on one side.

The timing difference between the field update of the camera or computer and the field update of the CRT for composite screen display (field update of the output synchronization signal) is one field period at most. Therefore, if ■ Serra 1~ are two field memories, when you write one field of information to field memory 1 and then write the next field to memory 2, reading from memory 2 is Conversely, when reading information from memory 1 is finished and the next field is to be read from memory 2, the problem arises that memory 2 is still in the process of being written. Therefore, in the present invention, one set is made up of three field memories to solve this problem. If there are three field memories, one field memory is placed between writing and reading, such that when memory 1 is used for writing, memory 3 is used for reading. In this case, it is possible to finish writing to memory 1 and continue writing the next field to memory 2. While writing the next field to memory 2, reading from memory 3 is completed and reading proceeds to memory 1.

In this way, overlapping of writes and reads is prevented and input/output timing adjustment is achieved.

According to the present invention, for example, an ITV camera image of the upper surface of molten steel in the continuous casting mold opening, an ITV camera image of the cast steel material, a graph screen showing the temperature distribution inside the mold processed by a computer, and various parts of the slab drawing process can be Halftone images for visual monitoring and binary images for data monitoring, such as graphs showing the temperature transition of treated steel, can be viewed on four screens in real time on one screen. In this way, NTSC system and RG
Integration of B-type CRT display systems is achieved.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

〔Example〕

FIG. 1 shows the configuration of an embodiment of the present invention. In this embodiment, NTSC color information of ITV cameras 301 and 302 is given to NTSC timing correctors 801a and 801b, and RGB color information of management or status monitoring computers 401 and 402 is given to RGB timing corrector 802a. and 802b.

The timing controller 803 performs readout of each timing corrector at a timing such that the screen output from each timing corrector is arranged neatly into four parts on the screen of a high-quality CRT display (not shown) for output display. controlling the effect and for the color information selector 820;
Specify the color information to be extracted. That is, in the first half of the field scanning period of the CRT display for output display, the first
Channel (301, -8018) and second channel (
302-801b) is read out line by line alternately, passed through the color information selector as one line data for output display, and in the latter half is read out from the third channel (401-801b).
The color information of the fourth channel 802a) and the fourth channel (402-802b) are read out line by line alternately and provided to the CRT display for output display as one line data for output display through color information selector 820. This action is repeated in synchronization with the field scanning period of the CRT display for output display. As a control signal for this,
The timing controller 803 controls the display section of the first quadrant (channel Cl2) and the second quadrant when one field of an output display CRT display (not shown) is divided into four.
Signals CHI to CH4 indicating the display interval of the quadrant (channel CIH), the display interval of the third quadrant (channel Cl43), and the display interval of the fourth quadrant (channel C) 14) are generated, and these signals are transmitted to the timing correctors 801a and 801b. , 8
02a and 802b, and also to the encoder 812b of the color information selector 820. That is,
Pixel synchronization pulse Px with the same period as the pixel division (pixel) period of the output display CRT display (not shown)
d is generated by a pulse oscillator 803a, and frequency-divided into a line synchronization pulse Pyd by a pixel counter 803b.

In this example, one line of the output display CRT display is a pixel. The count data of the pixel counter 803b is compared with N/2 by a comparator 803d, and the comparator 803d outputs L and M while the count data is less than O-N/2 (the display scan is in the second and third quadrants). /2 or more since 8
During this period (the display scan is in the first and fourth finite quadrants), H is generated and applied to the AND gate 803f for scanning channel detection. The line counter 803c has a line synchronization pulse Pyd.
When the line synchronization pulse for one field is counted, a carry pulse, that is, a field synchronization pulse Pfd is generated. The J field is the N line.

The count data of the line counter 803c is the comparator 8
03c, the comparator 803e compares the count data with N/2, and the comparator 803e detects that the count data is between 0 and less than N/2 (if the display scan is the first or second scan).
(quadrant) 1, between N/2 or more and less than N (display scan is 3rd
, 4 quadrants) 11 is generated and applied to an AND gate 803f for scanning channel detection. AND gate 803f for scanning channel detection connects comparators 803d and 803e.
From the output of
) to the fourth channel (CI) are generated. C)11=)l indicates that the output display scan is in the first channel (second quadrant); CI(2=H indicates that the output display scan is in the second channel (second quadrant);
Cl43=H indicates that the output display scan is in the third channel (third quadrant), and CH4=H indicates that the output display scan is in the fourth channel (fourth quadrant).
quadrant). These signals CHI to CH4 indicating the scanning area are each sent to a timing corrector 801.
a, 801b, 802a and 802b.

Timing corrector 801a.

In addition, pixel synchronization pulse Pxd, line synchronization pulse Pyd, and field synchronization pulse Pfd are applied to 801b, 802a, and 802b.

Each of the timing correctors 801a, 801b, 802a, and 802b has an identification signal generation means (308a in FIG. 2a, 309a in FIG. 3: described later) for NTSC system or RGB system in the control bus interface section. The identification signal = 16- is sent to the data selector 812 of the color information selector 820.
give to a.

The color information selector 820 includes a data selector 805 that receives color information from an NTSC timing corrector, a data selector 809 that receives color information from an RGB timing corrector, and one field of a CRT display (not shown) for output display. When divided into four, the display section of the first quadrant (channel CHI), the display section of the second quadrant (channel CH3), the display section of the third quadrant (channel C) 12), and the display section of the fourth quadrant (channel C
A signal C (11 to C old) indicating the display section of the color information selector 820 is generated and sent to the encoder 812 of the color information selector 820.
give to b. Input channel 0 of data selector 805
-3 are assigned to channels CH1-C old, respectively, and input channels 0-3 of data selector 809 are assigned to channels C111-CH, respectively. As shown in Figure 2, two NTSC
timing correctors 801a and 801b, and two RGB timing correctors 802a and 802b.
In other words, when two NTSC screens and two RGB screens are displayed on the same screen, for example, the NTSC timing corrector 801a is used.

80] b is connected to the first human-powered channel 0 and the second human-powered channel 1 of the data selector 805, and the RGB timing correctors 802a and 802b are connected to the third human-powered channel 2 and the fourth human-powered channel 3 of the data selector 809.
Connect to. The output of the data selector 805 is given to D/A converters 806y, m, and c, where it is converted into analog signals, passed through a color information conversion matrix 807, converted into R, G, and B signals (analog), level-adjusted, and then converted into analog signals. It is output through switch 808. Data selector 8
The output of 09 is converted into analog and level adjusted by an attenuator 810, and outputted through an analog switch 811. Scan area signals CHI to C indicating which of channels 1 to 4 the output display scan is on are sent to the encoder 8.
12b, the signal is converted into a code and applied to input channel designation terminals of data selectors 805 and 809. As a result, when the scanning area signal C old is 11, the data selectors 805 and 809
When the scanning area signal CH2 is H, the data of the second human power channel 1 is output, and when the scanning area signal CH3 is 11, the data of the third human power channel 2 is output, and the scanning area signal CH4 is output. When is 11,
Output the data of the 4th human power channel 3.

Timing correctors 80], a, 801b, 802a and 802b have identification signal generating means, which is a dip switch, and in the NTSC timing correctors 801a and 801b, this dip switch (3
08a) is set to close to generate the I signal, and in the RGB timing correctors 802a and 802b, this dip switch (309a) is set to open to generate the 11 signal.

The output signal of this dip switch is sent to the data selector 812.
When the scanning area signal C old is 11, the data selector 812a sends the dip switch signal I of the NTSC timing corrector 801a to the analog switches 808 and 81.1. When the scanning area signal CH2 is I(, the dip switch signal 1. of the NTSC timing corrector 801b is given.
is applied to the analog switches 80g and 81.1, and when the scanning area signal CH3 is 11, the data selector 812a
gives the signal H of the dip switch of the RGB timing corrector 802a to the analog switches 808 and 811,
When the scanning area signal C114 is 11, the data selector 812a sends the signal 11 of the dip switch of the RGB timing corrector 802b to the analog switches 808, 8.
Give to 11. Analog switch 808 is on when the control gate input is L and outputs the output of matrix 807 to the output display CRT display, and analog switch 811 is on when the control gate input is 11 and outputs the output of attenuator 811. Output to a CRT display for display.

With the above configuration, when the display scanning of the output display CRT display is in the second quadrant (first channel display) (CI
For H=1(), the NTSC timing corrector 801a
The output signal of
The signal is converted into an analog RGB signal through an A converter 806y+m+c+ matrix 807 and an analog switch 808, and is applied to a CRT display for output display.

The display scanning of the CRT display for output display is in the first quadrant (
2nd channel display) (CI42 = H), the output signal of the NTSC timing corrector 80 ratio is passed through the data selector 805 and the D/A converter 806
y, m, c, matrix 807 and analog switch 808, it is converted into an analog RGB signal and provided to a CRT display for output display.

The display scanning of the CRT display for output display is in the third quadrant (
3rd channel display) (CH3=H), RG
The output signal of the B timing corrector 802a is converted to an analog RGB signal through a data selector 809, an attenuator 810 and an analog switch 811, and is applied to a CRT display for output display.

The display scan of the CRT display for output display is in the fourth quadrant (
4th channel display) (CH4=H), R
The output signal of the G13 timing corrector 802b is converted to an analog RGB signal through a data selector 809, an attenuator 810 and an analog switch 811, and is applied to a CRT display for output display.

Note that the output display CRT display is supplied with a field synchronization signal Pfd, a line synchronization signal Pyd, and a pixel synchronization signal Pxd, and the display synchronizes with these signals and displays an image based on the supplied RGB signals. Perform display.

FIG. 2a shows the configuration of the NTSC timing corrector 801a. Note that the NTSC timing corrector 801b
The configuration is exactly the same. Referring to FIG. 2a, an NTSC video signal is applied from an NTC5 camera 301 to an image color demodulation circuit 101. Each color component of the video signal V, R-1' and B-'/multiple signal, respectively A
It is converted into digital data by ID converters 102 to 104 and stored in three field memory sets 305 to 307.
given to. On the other hand, a synchronization separation circuit 105 separates the synchronization signal in the NTSC video signal to generate a field synchronization signal Pfs, a line synchronization signal Pyd, and a pixel synchronization signal Pxd, and supplies these to the memory control circuit 106a. The memory control circuit 106a generates memory read/write control signals based on these synchronization signals and provides them to the field memory sets 305-307.

The synchronization signal is also provided to write address counter 107, which generates write address data and provides it to field memory sets 305-307.

On the other hand, output display synchronization signals Pfd, pyd and P
xd is connected to the memory control circuit 106b and the read address counter 11 via the control bus interface 114.
given to 3. Field memory set 305-30
The color image information read from 7 is sent to color information selector 820 via data bus interface 115.
is given to the first human channel 0 of the data selector 805.

The control bus interface 114 is equipped with a dip switch 308a as an identification signal generating means, which is set to close in the case of an NTSC timing corrector, and connects the L (ground) level voltage to the control bus. Via the interface 114, it is applied to the first human power channel 1 of the data selector 812a of the color information selector 820.

Field memory sets 305, 306, and 307 are each assigned to one of the color component signals Y, R-Y, and B-Y, and each is composed of three field memories, and the configuration is as follows. It's exactly the same.

FIG. 2b shows field memory set 307. Memory control circuit 106 (106a+106b), write address counter 107 and read address counter 113
The configuration is shown below. Referring to FIG. 2b, the synchronization signal Pfd for the image capture scan of the camera 1 and the synchronization signal Pfs for the video scan of the CRT display for output display are transmitted to the memory control circuit 1.0.
6 and counter 1.06R counts Pfd. The count data code of the counter 106R is decoded by the decoder 106D. II, 7, 10, 13.
...While the video signal of the field is being output, it becomes H and is output to the first field memory 12 as a write instruction signal.
3a read/write control end and gate 1081.1091.1
101 and 1111. Decoder 106D
The output end 1 of the camera 301 is the 2.5th, 8th, 11th, 1st
4. . . . While outputting the video signal of the field, it becomes H and serves as a write instruction signal to the read/write control end of the second field memory 123b and the gates 108□, 1092.
．． given to t1o2 and 111□. Decoder 10
The output end 2 of the 6D is connected to the camera 301 at the 3rd, 6th, 9th, and 12th
,14. ...While the video signal of the field is being output, it becomes H and serves as a write instruction signal between the read/write control end of the third field memory 123C and the gates 108a, 1.
093.1], Oa and 1113. Therefore, the field memories 123a to 123C are sequentially designated for writing for each field of video output from the camera 801a, and when designated for writing, the gates 1081 +23 and 1101 +2 +3 are opened, and the data selector 110 Writes the data given by. On the other hand, the count data of the counter 106R is applied to the data selector 110, and the color component data of the A/D converter 102 (FIG. 2a) is applied to the field memory designated for writing.

That is, in synchronization with Pfd, 1 is first stored in the memory 123a.
The color component data of the field is written and Pfd is 1.
When a pulse arrives, one field of color component data is written into the memory 123b, when another pulse of Pfd arrives, one field of color component data is written into the memory 123c, and when the next pulse arrives, this time, One field of color component data is written to the memory 123a, and the memory 123a-123b-
The digital data of the color component (1) of the camera 301 is written into the field memory set 307 by cycling from 123cm 123a- on a field-by-field basis.

The latch 106L is given data specifying the previous memory in the circulation direction among the field memories 123a to 123c specified for writing in this way, and Pfd
The latched data is latched in synchronization with the output data selector 111. As a result, among the two field memories 123a to 123c that are not designated for writing, the read data of the field memory that is one field memory before the one that is designated for writing in the circulation direction is transferred from the data selector 111. Data bus interface 1
15. The count data of the counter 106R is switched in synchronization with Pfs (camera 301), and this switching is not synchronized with Pfs (output display CRT). Therefore, the latch 106L latches the read designation data so that the read designation does not switch to another field memory while reading from one field memory.

In write address counter 107, counter 1
07x counts the pixel synchronization pulse Pxd and is cleared by the line synchronization pulse Pyd. counter 107y
counts the line synchronization pulse Pyd and is cleared by the field synchronization pulse Pfd. The count data of counters 107x and 107y is applied as a write address to gate 10811213, which is turned on (gate open) only when writing is designated (when the signal applied from decoder 106D is 11).

In the read address counter 113, CHI=
Counter 113X counts Pxs during H, is cleared by line synchronization pulse, and counter 113y counts Pxs when CH1=
Count Pys between H and field synchronization pulse Pf
Cleared with s. The count 1-data of the counters 113x and 113y is used as a read address by the gate 10, which is turned on (gate open) only when reading is specified (when the signal given from the decoder 106D is 1).
It is given to 91 +2 +3.

With the above configuration, for example, when the camera 301 is outputting the first field of video information, the data selector 1
10 outputs the input to output terminal 1, gate 1101 opens,
110□ and 1103 are closed, the y information of the video information is given only to the data line of the field memory 123a, the gate 1081 is open, and 1082 and 1083 are closed, the write address data is given only to the address line of the field memory 123a. Given.

Therefore, (1) information is written only to the field memory 123a. At this time, both field memories 123b and 123c are designated for reading, read address data is applied to both, and data output gate 1112
Both 1113 and 1113 are open, and data is read from both memories, but since data selector 1]■ is in the selected state to output the data of its input terminal 3, memory 12
Only the read data of 3c is output to the data bus interface 115.

Gate-2 is turned on (gate open) only when
8=1091 z2 +3 is given.

Next, when the camera 301 is outputting the second field of video information, the data selector 110 outputs the input to the output terminal 2, the gate 1102 is opened, and the gates 1101 and 1103
is closed, and the Y information of the video information is stored in the field memory 12.
Gate 1082 is open, gates 1081 and 1083 are closed, and write address data is applied only to the address line of field memory 123b. Therefore, ■ information is stored in the field memory 12.
Written only to 3b. At this time, field memory 1
23C and 123a are both designated for reading, read address data is applied to both, data output gates 1113 and 1112 are both open, and data is read from both memories, but the data selector 111
Since it is in the selected state to output the data of input terminal 1,
Only read data from memory 123a is output to data bus interface 115.

Next, when the camera 301 is outputting the third field of video information, the data selector 110 outputs the input to the output terminal 3, the gate 1103 is opened, and the gates 1101 and 1102
is closed, the ■ information of the video information is stored in the field memory 12.
Gate 1083 is open, gates 1081 and 108 are closed, and write address data is applied only to the address line of field memory 123c. Therefore, ■ information is stored in the field memory 12.
Written only to 3c. At this time, field memory 1
23a and 123b are both designated for reading, read address data is applied to both, data output gates 1111 and 1112 are both open, and data is read from both memories, but the data selector 111
Since it is in the selected state to output the data of input terminal 2,
Only read data from memory 123b is output to data bus interface 115.

Hereinafter, the writing of the color component Y information of the fourth field is the same as in the case of the first field, the writing of the color component Y information of the fifth field is the same as the case of the second field, and the writing of the color component Y information of the fifth field is the same as in the case of the second field.
The color component Y information of each field is written in the same manner as the third field, and so on, and the color component Y information of each field is sequentially written to the memories 123a to 123c and designated for writing. The memory immediately preceding the memory is designated for reading, and its data is read.

As can be understood from the above explanation, writing is performed by the camera 301.
Reading is performed in synchronization with the image scanning of the output display CRT. The pixel synchronization pulse Pxs and line synchronization pulse Pys are given to the readout address counters 113x and 113y only when the display scan of the output display CRT is in channel 1 (second quadrant). The read address is updated only during the corresponding period in synchronization with the image scanning of the output display CRT.

The configuration and operation of field memory sets 305 and 306 shown in FIG. 2a are also exactly the same as those of field memory set 307 described above, for writing and reading color component R-1 data and B-'/data, respectively. .

The configuration of the NTSC timing corrector 801b is also 801.
It has exactly the same configuration as a = 31-, but its read address counter (corresponding to 113) has C instead of CHI.
H2 is given.

FIG. 3 shows the configuration of the RGB timing corrector 802a. Since the input signal for this corrector 802a is for RGB, the configuration for synchronization signal processing and color component signal processing is slightly different depending on the difference between the NTSC system and the RGB system, but the field memory sets 405- The configuration of the timing corrector 407 is exactly the same as that of the NTSC timing corrector 801a. The dip switch 309a is RGB
is set to open to indicate that the
An H signal indicating that it is for RGB is applied to the data selector 812a of the color information selector 820 via the control bus interface 214.

The read address counter 213 of this RGB timing corrector 802a is given CH3 instead of C old, and the line synchronization pulse counter (corresponding to 113y) is given a line synchronization pulse only when Afh is H. Pyd is given.

The RGB timing corrector 802b has the same configuration as the RGB timing corrector 802a. However, the read address counter (corresponding to 213) has C instead of CH3.
H4 is applied.

With the above configuration and operation, in the embodiment shown in FIG. and 305 in field units, and then read out in field units sequentially during the scanning period of the second quadrant of one output display field in synchronization with video scanning of the output display CRT. In each set of field memories (for example 307), three field memories 12
3a to 123C, write the color component information ■ of each field of the camera 301 in a circular manner for each field,
Specify the memory immediately before the memory specified for writing for reading, and select the second memory in field 1 of the output display CRT.
The color component information (■) is read out in synchronization with the display scan of the quadrant.

Imaging color component information V, RY and B of camera 302
-■ is sequentially written field by field into each of the three field memory sets of the timing corrector 801b in synchronization with the imaging scan of the camera 302, and then in synchronization with the video scan of the output display CRT. , output display 1
During the scanning period of the first quadrant of the field, they are sequentially read out field by field.

The image color component information R, G and B of the computer 401 is
In synchronization with computer display output video scanning, each field is sequentially written into each of the three field memory sets 401, 407, and 405, and in synchronization with video scanning of the output display CRT, output display 1 During the scanning period of the third quadrant of the field, they are sequentially read out field by field.

The image color component information R, G and B of the computer 402 is
Fields are sequentially written in each of the three field memory sets in synchronization with the scanning of the computer display output video, and the fourth quadrant of one field of output display is written in synchronization with the video scanning of the output display CRT. During the scanning period of
These are sequentially read field by field.

In the embodiment shown in FIG. 1, two NTSC timing correctors and two RGB timing correctors are connected to the color information selector 820, but one NTSC timing corrector and RGB timing corrector are connected to the color information selector 820. When connecting three devices, connect one NTSC timing corrector to, for example, the first manual channel 0 of the data selector 805 and the first manual channel 1 of the data selector 812a, and
Three timing correctors for GB are connected to the second to fourth channels of the data selector 809 and the data selector 812.
Connect to channels 2 to 4 of 2nd to 4th person a. NTS
When connecting four timing correctors for C, they are connected to data selectors 805 and 8128, and when connecting four timing correctors for RGB, they are connected to data selectors 809 and 8128. When connecting three or less devices, it is sufficient to connect only the desired channels as described above.

In this way, in the embodiment shown in FIG. 1, only one of the NTSC timing corrector and the RGB timing corrector,
Alternatively, a total of four units of both can be connected.

〔Effect of the invention〕

As explained above, according to the present invention, moving images and still images such as the output of an ITV camera or a computer system can be displayed on a single CRT display device on multiple screens, which can be used in large-scale process monitoring systems, etc. is highly efficient and simplified, and the operator's viewing range for monitoring becomes narrower.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2a is a block diagram showing the configuration of the timing corrector 801a shown in FIG. 1, and FIG. 2b is a block diagram showing the configuration of the timing corrector 801a shown in FIG. 2a. 3 is a block diagram showing the structure of the timing corrector 802a shown in FIG. 1. FIG. 301.302: ITV camera (NTSC method) 4
01.402: Computer 801 that outputs RGB screen
a, 801b: NTSC timing corrector (NT
SC color information input/output timing correction means) 802a, 802b: RGB timing corrector (
RGB color information input/output timing correction means) 803: Timing controller (color information read timing control means)

Claims (2)

[Claims] (1) One set consists of three field memories, and the NTS
Three sets of field memories, one set assigned to each of the three types of C color component information, and the three field memories in each set can be written sequentially in field units or frame units in synchronization with the NTSC color component information. read/write designation means for designating one of the field memories not designated for writing for reading; and a color information write address for giving write address data in synchronization with the NTSC color component information to the field memory designated for writing. NTSC color information input/output timing correction means; a set of a; NTSC color information input/output timing correction means; Three field memories are set as one set, one set is assigned to each of the three types of RGB color component information, and the three field memories in each set are synchronized with the RGB color component information to create a frame. Or read/write specification means that sequentially specifies writing in field units and specifies one of the field memories not specified for writing for reading, and writes in synchronization with RGB color component information to the field memory specified for writing. RGB color information input/output including color information write addressing means for providing address data, and color information read addressing means for providing read address data to a field memory designated for reading based on a color information output synchronization signal. B sets of timing correction means are provided, where a and b are each 1 or more; Color information read timing control means for generating image information extraction information; and, based on the image information extraction information, the NTSC of the group a
A color information selection means for selectively extracting the read color component information of the color information input/output timing correction means and the RGB color information input/output timing correction means of the group b and outputting it to a color CRT display; a divided display of color image information; Processing equipment. (2) Claim No. (1), wherein a+b=4.
2. A split display processing device for color image information as described in 2.