JPS63175485A - Thin film light-emitting element - Google Patents

Thin film light-emitting element

Info

Publication number
JPS63175485A
JPS63175485A JP62006006A JP600687A JPS63175485A JP S63175485 A JPS63175485 A JP S63175485A JP 62006006 A JP62006006 A JP 62006006A JP 600687 A JP600687 A JP 600687A JP S63175485 A JPS63175485 A JP S63175485A
Authority
JP
Japan
Prior art keywords
film
substrate
single crystal
fluoride
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62006006A
Other languages
Japanese (ja)
Inventor
Hitoshi Onuki
仁 大貫
Junko Asano
純子 浅野
Yuji Miura
裕二 三浦
Kiyohiko Tanno
丹野 清彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62006006A priority Critical patent/JPS63175485A/en
Publication of JPS63175485A publication Critical patent/JPS63175485A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body

Abstract

PURPOSE:To make it possible to form GaAs films having an excellent crystallizability on an insulating substrate by a method wherein an insulator intermediate layer is provided on the single crystal substrate consisting of a metal and moreover, the P-type and N-type GaAs films are provided on its upper part. CONSTITUTION:An insulative fluoride film 2 is formed on a single crystal metal plate 1 consisting of such a metal as Fe, Ni, Al, Cu, Co and Cr, which can be matched with fluoride with respect to the thermal expansion coefficient to obtain a substrate. Thereby, the warpage of the substrate is prevented and the defect in the film 2 is eliminated to form GaAs films 3 and 5 having an excellent crystallizability thereon. The dielectric strength of fluoride is 10<5>V/m or more, the fluoride has sufficiently insulating properties and a strong orienta tion property, the single crystal fluoride film 2 is obtained on the single crystal metal plate 1 and moreover, the single crystal GaAs films 3 and 5 are easily grown on the film 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は情報を光学的に記録する光プリンタヘッド及び
情報を光学的に表示するディスプレイのヘッドならびに
光と半導体との両方の機能を合せもつ光ICに関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an optical printer head that records information optically, a display head that optically displays information, and a head that has both optical and semiconductor functions. Regarding optical IC.

貧従来の技術〕 高速、低価格、コンバク”ト化を目的に種々の光プリン
タが世に出ており、これらはレーザビームプリンタ液晶
プリンタ、LEDプリンタ等であるレーザビームプリン
タ(LBP)は印字速度が極めて早く、記録密度も高く
できる長所があるが、これはレーザビームを高速に回転
する回転多面鏡によって偏向し光走査を行ない、更に、
この光ビームを情報信号に応じて変調を加え被記録感光
体に与え、記録画像を形成する方法であるため、書き込
み容積が大きくなり、消費電力が大きく、装置全体とし
て値段が高くなるという欠点がある。
Poor conventional technology] Various optical printers have been released for the purpose of high speed, low cost, and compactness.These include laser beam printers, liquid crystal printers, and LED printers. It has the advantage of being extremely fast and capable of high recording density, but it uses a rotating polygon mirror that rotates at high speed to deflect the laser beam and perform optical scanning.
This method modulates this light beam according to the information signal and applies it to the photoreceptor to be recorded to form a recorded image, which has the drawbacks of a large writing volume, high power consumption, and a high price for the entire device. be.

また、LBPでは回転多面鏡をジッタもなく記録面への
焦点ボケもなく、レーザビームを結像させるには光学的
精度はもとより、モータの回転サーボ等機械的にも電気
的にも精度の高い手段を必要としていた。一方、液晶プ
リンタは光源(蛍光灯LBPの115)という長所があ
る。しかし、印字速度は極めて遅く(例えばLBPの1
/20)、記録密度も低い(LBPの2/3)という欠
点もある。
In addition, in LBP, the rotating polygon mirror has no jitter and no defocus on the recording surface, and in order to form a laser beam, it requires not only optical precision but also high mechanical and electrical precision such as the rotation servo of the motor. I needed the means. On the other hand, a liquid crystal printer has the advantage of a light source (fluorescent lamp LBP 115). However, the printing speed is extremely slow (for example, LBP 1
/20) and low recording density (2/3 of LBP).

他方、光プリンタ用ヘッドとして発光素子(LED)ア
レイを使用するものがある0水力式はLCの場合と同様
、可動部分がなく、LEDアレイと駆動用ICを載せた
基板だけのため、全体としての容積はLBPの1/15
程度と極めて小さくでき、しかも、印字速度も早< (
LBPの1/2〜1/3)、記録密度も高い(LBPと
同等以上)、シかし、LEDアレイでは多数のLEDの
チップを基板とは別に製造し、基板上に接着し記録ヘッ
ドとするため、走査線の精度を得るには精密なアライメ
ントを必要とすること、それぞれのチップを別々に接着
するため光の「むら」を生じ、′基板の上に薄膜(7)
 G a A sをMOCVD、MBE、あるいは、液
相成長法によって形成するが、単結晶基板の大きさは高
々2〜3インチ程度であること、さらに、この基板には
転位等の欠陥の密度が極めて高く、従って、成長させた
G a A s膜中に;も極めて高い密度の欠陥が導入
されるため、場所により発光効率が変化することになる
。また、G a A sの単結晶基板の値段も極めて高
いため。
On the other hand, the 0-hydraulic type, which uses a light emitting element (LED) array as an optical printer head, has no moving parts, just like the LC case, and only has the LED array and driving IC mounted on the board, so the overall performance is The volume of is 1/15 of LBP
It can be made extremely small, and the printing speed is also fast.
(1/2 to 1/3 of LBP) and high recording density (same or higher than LBP).However, in LED arrays, many LED chips are manufactured separately from the substrate, and then glued onto the substrate and connected to the recording head. Therefore, precise alignment is required to obtain the accuracy of the scanning line, and since each chip is glued separately, it causes "unevenness" in the light, and the thin film (7) on the substrate is
Ga As is formed by MOCVD, MBE, or liquid phase growth, but the size of the single crystal substrate is about 2 to 3 inches at most, and furthermore, this substrate has a high density of defects such as dislocations. Therefore, since an extremely high density of defects is introduced into the grown GaAs film, the luminous efficiency changes depending on the location. In addition, the price of GaAs single crystal substrates is extremely high.

装置全体の値段を下げられないという欠点もある。Another disadvantage is that the price of the entire device cannot be lowered.

しかし、GaAs単結晶基板の代りに、安価で、しかも
、転位密度が極めて低いSi基板、サファイア基板等の
上に発光ダイオードを形成することが可能になれば、こ
れらの欠点のないLEDプリンタ、ディスプレイ、三次
元光ICが安価に作製できると考えられる。このため、
各研究所において表1に示すようにSi単結晶上にSi
と格子定数の極めて近いGeを設けた後、G a A 
sを成長させる方法(1)や、GaAsそれ自体をSi
上に多層に設け、さらにその上部にG a A sの発
光轡子を設ける方法(2)等が検討されている。
However, if it were possible to form light emitting diodes on Si substrates, sapphire substrates, etc., which are inexpensive and have extremely low dislocation density, instead of GaAs single crystal substrates, it would be possible to create LED printers and displays that do not have these drawbacks. It is believed that three-dimensional optical ICs can be manufactured at low cost. For this reason,
At each research institute, Si is deposited on Si single crystal as shown in Table 1.
After providing Ge whose lattice constant is very similar to that of G a A
Method (1) of growing GaAs itself and Si
A method (2) of providing a multi-layered layer on top and further providing a GaAs light-emitting screen on top is being considered.

表  1 しかし、(1)の方法では、Geとその上部に形成する
G a A sとの格子定数がかなり異なる、;(表1
参照)ため、G a A s中に多数の転位等の欠陥が
導入され、発光効率は極めて悪くなるという欠点がある
Table 1 However, in method (1), the lattice constants of Ge and Ga As formed on top of it are quite different; (Table 1
), a large number of defects such as dislocations are introduced into GaAs, resulting in extremely poor luminous efficiency.

(2)の方法の場合、多層のGaAg層を積層させる必
要があるため、時間を必要とすること、格子定数が異な
るため多数の転位が導入される等の欠点がある。
In the case of method (2), since it is necessary to laminate multiple GaAg layers, there are drawbacks such as requiring time and introducing a large number of dislocations due to different lattice constants.

また、中間層として、Si上にGoと同様これと極めて
格子定数の近いCaFz膜を蒸着法によって形成し、そ
の上部にG a A sを形成する方法(H、l5hi
hara et、al:Mat、Res、Symp、P
roc、25pp。
Furthermore, as an intermediate layer, a CaFz film having a lattice constant similar to that of Go is formed on Si by vapor deposition, and GaAs is formed on top of the CaFz film (H, l5hi).
hara et, al: Mat, Res, Symp, P
roc, 25pp.

393−403 )も検討されている。しかし、CaF
zの熱膨張係数はSiの五倍もあるため、大きなそりを
生じ、その上部に形成したG a A s膜も欠陥を多
く含むものになるという欠点があり、今までのところ、
絶縁板上に結晶性に優れたG a A s膜を形成した
例は見当らない。
393-403) are also being considered. However, CaF
Since the coefficient of thermal expansion of z is five times that of Si, it has the disadvantage that it causes large warpage and the GaAs film formed on top of it also contains many defects.
No examples have been found in which a GaAs film with excellent crystallinity is formed on an insulating plate.

なお、この種の技術として関連するものには。In addition, related to this type of technology.

例えば特開昭59−182582号がある。For example, there is Japanese Patent Application Laid-Open No. 59-182582.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

した薄膜発光素子を作ることによって機械走査も不要な
高密度の基板一体型光プリンタヘッドを提供することに
ある。
The object of the present invention is to provide a high-density, substrate-integrated optical printer head that does not require mechanical scanning by manufacturing a thin film light emitting device.

従来からのLEDの製作工程はG a A s等の基板
上に液相、または、気相エピタキシャル成長技術により
、 G a A s等の発光接合部を作るものであった
* GaAs基板の大きさは最大で三インチである。従
って光プリンタで必要とする原稿面に対応できる長さの
ものを一体の基板上に作ることは不可能であり、複数個
の発光ダイオードを多数波ベアライメントし、一本の光
ヘッドとしていた。
The conventional manufacturing process for LEDs is to create a light-emitting junction of GaAs, etc. on a GaAs substrate using liquid phase or vapor phase epitaxial growth technology.* The size of the GaAs substrate is The maximum length is three inches. Therefore, it is impossible to fabricate on a single substrate a length that can accommodate the document surface required by an optical printer, and a single optical head has been formed by performing multi-wave bear alignment of a plurality of light emitting diodes.

一方、最近の薄膜技術の進歩によって1M0CVDある
いはLBEにより高性能のG a A s薄膜を作製す
ることができるようになってきて、例えば、異種基板で
あるシリコン上、あるいは、サファイア上にG a A
 s薄膜を成膜しようとする試みがなされている。しか
し、材質の異なる基板とその上部に形成する薄膜との間
の格子定数が異なる場合′シミは、成長膜中に多数の転
位が導入されるか、あ”!b b’、は、多結晶1,4
6ヨ能性があ6.3ゎを防止するには、絶縁基板と成長
膜との間に′格子歪を緩和する中間層を形成する必要が
あり、このため、Ge、CaFx等が検討されている。
On the other hand, recent advances in thin film technology have made it possible to produce high-performance GaAs thin films by 1M0CVD or LBE.
Attempts have been made to form s thin films. However, if the lattice constants between the substrate made of different materials and the thin film formed on the substrate are different, then the stain may be due to the introduction of a large number of dislocations into the grown film, or the formation of polycrystalline stains. 1,4
In order to prevent the 6.3° potential, it is necessary to form an intermediate layer between the insulating substrate and the grown film to alleviate the lattice strain, and for this reason, Ge, CaFx, etc. are being considered. ing.

しかし。but.

GeはSiとの格子定数の差が表1に示すように大きす
ぎるし、ふつ化物はSiと格子定数はマツチするものの
上述したように、Siとの熱膨張係数の差が大きく、大
面積の中間層を必要とするプリンタヘッドでは、成膜後
に大きな「そり」を生じ、これに起因してふっ化物にf
s&細クチクラックるいは、転位等の欠陥を生じること
になる。
Ge has a large difference in lattice constant from Si as shown in Table 1, and although the lattice constant of common compounds matches that of Si, as mentioned above, the difference in thermal expansion coefficient from Ge is large and it is difficult to use large areas. In printer heads that require an intermediate layer, a large "warp" occurs after the film is formed, and this causes f
S & fine cuticle cracks result in defects such as dislocations.

〔作用〕[Effect]

Cu、AQ、Few Ni、Go等の金属板の熱膨張係
数は12〜26 X 10’−’/’Cの範囲にあり、
ふつ化物のそれ(17,5X10″”8/”C)に近い
The thermal expansion coefficient of metal plates such as Cu, AQ, Few Ni, and Go is in the range of 12 to 26 x 10'-'/'C,
It is close to that of a common creature (17.5 x 10""8/"C).

したがって、金属板上にふっ化物膜を形成しても。Therefore, even if a fluoride film is formed on a metal plate.

S i (3,5X 10−”/℃)上に成膜した場合
に比べて、そりをほとんど無くすことができ、ふっ化物
膜中にも欠陥はほとんど導入されない。また′長する。
Compared to the case where the film is formed on Si (3,5 x 10-''/°C), warping can be almost eliminated and defects are hardly introduced into the fluoride film.

また、ふっ化物膜/単結晶板上に形成すルG a A 
s膜との格子定数のミスマツチは、CaFzとSrF2
の配合組成を制御することによりほとんど無くすことが
可能である。
In addition, G a A formed on the fluoride film/single crystal plate
The mismatch in lattice constant with the s film is caused by CaFz and SrF2
It is possible to almost eliminate it by controlling the blending composition.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、このようなことにかんがみ、なされたもので
、ふつ化物の熱膨張係数とマツチングのとれる、Fe、
Ni、AQy Cu、Co、Cr等の単結晶金属板上に
絶縁性ふつ化物膜を形成して、基板にして、「基板のそ
り」を防ぎ、ふつ化物膜中の欠陥をなくして、その上に
結晶性に優れたG a A s膜を形成しようとするも
のである。
The present invention has been made in view of the above-mentioned problems, and includes Fe, which can be matched with the coefficient of thermal expansion of the fluoride.
An insulating fluoride film is formed on a single crystal metal plate such as Ni, AQy Cu, Co, Cr, etc., and used as a substrate to prevent "substrate warpage" and eliminate defects in the fluoride film. The aim is to form a GaAs film with excellent crystallinity.

ふつ化物の絶縁耐圧は10’V/m以上であり、十分に
絶縁性がある。
The dielectric strength voltage of the common compound is 10'V/m or more, and it has sufficient insulation properties.

またふつ化物は配向性が強く、単結晶金属板上には単結
晶のふつ化物膜が得られる。
Furthermore, fluorides have strong orientation, and a single-crystal fluoride film can be obtained on a single-crystal metal plate.

さらに、単結晶ふつ化物膜上には、単結晶G a A 
s膜が容易に成長する。
Furthermore, on the single crystal fluoride film, single crystal Ga A
s film grows easily.

〔実施例〕〔Example〕

以下、本発明を実施例を用いて説明する。 The present invention will be explained below using examples.

第1図は5i(111)面上に真空蒸着(10−7To
rr)によってCaFx膜(中間層)を0.1〜0.5
μm付けた場合及びCu(111)単結晶板上に。
Figure 1 shows vacuum evaporation (10-7To) on the 5i (111) plane.
CaFx film (intermediate layer) by 0.1 to 0.5
μm and on a Cu(111) single crystal plate.

同様に真空蒸着によってCaFx膜を付けた場合の基板
のそりを示したものである。CaFz/Si基板のそり
はCaFx膜が厚くなるにつれて、がなり大きくなるが
、CaFz/Cu 基板ではほとんどそってないことが
わかる。但し基板の直径はSowである。
Similarly, the figure shows the warping of the substrate when a CaFx film is attached by vacuum evaporation. It can be seen that the warpage of the CaFz/Si substrate becomes larger as the CaFx film becomes thicker, but there is almost no warping of the CaFz/Cu substrate. However, the diameter of the substrate is Sow.

第2図はCaFxl金展板のそりに及ぼす金属板の熱膨
張係数の影響を示している。金属板の熱膨張係数がl0
XIO””6℃以上になると、そりがほとんどなくなる
ことがわかる。
FIG. 2 shows the influence of the coefficient of thermal expansion of the metal plate on the warpage of the CaFxl gold plate. The coefficient of thermal expansion of the metal plate is l0
It can be seen that when the temperature exceeds 6°C, the warpage almost disappears.

第3図は第1図においてMBEにより■Si上のCaF
x膜上にG a A s 膜を1μm形成した場合、■
Cu上のCaF2膜上にGaAs5膜を1μm形した場
合について、それぞれのG a A s膜の結晶性を調
べるために、ホトルミネセンス強度とそ)いる。
Figure 3 shows ■CaF on Si obtained by MBE in Figure 1.
When a 1 μm thick G a As film is formed on the x film, ■
In order to examine the crystallinity of each GaAs film in the case where a 1 μm thick GaAs film is formed on a CaF film on Cu, the photoluminescence intensity and its values are measured.

図から明らかなように、CaFz膜/ Cu上に成長さ
せた場合のG a A s膜の結晶性はG a A s
基板上に成長させたG a A s膜に近いことがゎが
る。またCaFz/Si 上に成長させた場合の結品性
が最も悪い。
As is clear from the figure, the crystallinity of the GaAs film when grown on the CaFz film/Cu is
It is preferable that it be similar to a GaAs film grown on a substrate. Furthermore, the crystallization property is the worst when grown on CaFz/Si.

第4図は半導体発光素子の一実施例を示したものである
。Cu単結晶(111)基板上に真空蒸着(10″″7
Torr)によってCaF2膜を約0.1μm付け、次
にMBEによって600〜700℃の温度範囲において
、P型G a A s、次にn型G a A sを約4
μm付けた。次に、図のようにパターンニング、Au電
極を形成後、ワイヤボンディングしてドライバに接続し
て、素子上部から発光させるものである。CuとCaF
x膜の熱膨張係数はそれぞれ、17X10−’/”e、
17.5X10−8/℃でありほぼ一致しているため、
基板のそりはない。
FIG. 4 shows an embodiment of a semiconductor light emitting device. Vacuum deposition (10″″7) on Cu single crystal (111) substrate
Torr) to deposit a CaF2 film with a thickness of about 0.1 μm, then apply MBE to a temperature range of 600 to 700°C to deposit P-type Ga As and then n-type Ga As to approximately 4 μm.
Added μm. Next, as shown in the figure, after patterning and forming Au electrodes, the device is connected to a driver by wire bonding to emit light from the top of the device. Cu and CaF
The coefficient of thermal expansion of x film is 17X10-'/”e, respectively.
17.5X10-8/℃, which is almost the same, so
There is no warping of the board.

グーまたCaFxの代りにCaFzとSr″12の混合
゛、・・ ]・膜(CaFz(1−x)SrFx  x=o〜0.
6)でも良い。
Also, instead of CaFx, a mixture of CaFz and Sr''12 ゛,... ]・film (CaFz(1-x)SrFx x=o~0.
6) But that's fine.

第5図は本発明による光プリンタヘッドの基本構成図で
ある0図中、31は基板でGaAsLEDアレイの基板
となるもので、サファイア、Siなど平滑な平面が利用
される。32はLEDアレイで格子−個、−個が発光部
に対応し、隣接ドツトとは電気的に分離され、独立に光
の発光ができる構成となっていて、同一基板内に必要な
画素数によって構成され、画素密度も被記録情報に対応
する。33は各LEDアレイ32を駆動するためのドラ
イバ素子で、通常、ラッチ回路の付加されたトランジス
タ付のドライバで、ドライバの部はトランジスタ、また
は、MOSのドライバ回路を付加したものである。34
.35は、この配線パターンを概念的に示したものであ
る。この配線は主としてワイヤボンディングによるが半
田リフロー接続でも良い。
FIG. 5 is a basic configuration diagram of an optical printer head according to the present invention. In FIG. 0, reference numeral 31 denotes a substrate that serves as a substrate for a GaAs LED array, and a smooth flat surface such as sapphire or Si is used. Reference numeral 32 denotes an LED array, in which each dot in the grid corresponds to a light emitting part, is electrically separated from adjacent dots, and is configured to be able to emit light independently, depending on the number of pixels required on the same substrate. The pixel density also corresponds to the recorded information. Reference numeral 33 denotes a driver element for driving each LED array 32, which is usually a driver with a transistor and a latch circuit added thereto, and the driver section has a transistor or MOS driver circuit added thereto. 34
.. 35 conceptually shows this wiring pattern. This wiring is mainly done by wire bonding, but solder reflow connection may also be used.

第6図は、第5図の実施例に示したLED、ド、ライバ
アレイなどを実装した光プリンタヘッド等′) ゛・を適用した光プリンタの例である。1は感光ドラム
で、Se、’5eTe、あるいは、その複合体。
FIG. 6 is an example of an optical printer to which an optical printer head, etc., mounted with the LED, driver array, etc. shown in the embodiment of FIG. 5 is applied. 1 is a photosensitive drum made of Se, '5eTe, or a composite thereof.

a−8i、OPCなどより構成さねており、一般の電子
写真技術の分野での技術で作られたものである。
It is composed of A-8i, OPC, etc., and is made using technology in the field of general electrophotography.

2はこの感光体表面に付感、すなわち、電荷を与えるた
めの帯電器を示し、3は本発明の光プリンタヘッドを示
す、帯電器2によってコロナ帯電された感光ドラム1は
光プリンタヘッド3による情報信号に従った露光をうけ
、情報に応じて電荷の消去が行なわれ、残留した電荷に
より静電潜像が形成される。この静電潜像は、直ちに現
像器4により現像剤6が付着した現像ローラ5により現
像されトナー像7となる。一方、記録紙9は給紙カセッ
ト8に納められ、残数記録枚数に合せて記録紙押えバネ
10により記録紙押え捧11に押し付けられ、記録紙給
紙ロール12が稼動すると一枚毎に記録紙の給紙が行な
われる。記録紙駆動ロール14.15によりドラム1の
回転とほぼ同速帯電器17によって荷電され、現像画像
7は記録紙に転写し、ばくり放電等余分な荷電が残らず
、また、転写帯電器の効果も十分発揮できるような位置
に付けた除電器18の部分を通り、像が転写され、転写
画像19を乗せ給紙ガイドロール20を経て熱定着ロー
ル21に入る。転写画像19は未定着であるので、fM
単に画像が取れてしまうので、ガイド等の設計に十分な
注意が必要となる。
Reference numeral 2 indicates a charger for applying charge to the surface of the photoreceptor, and reference numeral 3 indicates an optical printer head of the present invention. It is exposed to light in accordance with an information signal, the charges are erased in accordance with the information, and an electrostatic latent image is formed by the remaining charges. This electrostatic latent image is immediately developed by a developing roller 5 to which a developer 6 is attached by a developing device 4, and becomes a toner image 7. On the other hand, the recording paper 9 is stored in the paper feed cassette 8, and is pressed against the paper presser foot 11 by the paper presser spring 10 according to the number of remaining recording sheets, and when the paper feed roll 12 is operated, the paper is recorded one by one. Paper is fed. The recording paper driving rolls 14 and 15 are charged by the charger 17 at almost the same speed as the rotation of the drum 1, and the developed image 7 is transferred to the recording paper, so that no unnecessary charges such as flash discharge remain, and the transfer charger is The image is transferred through the static eliminator 18 which is placed at a position where the effect can be fully exerted, and the transferred image 19 is placed on the paper feed guide roll 20 before entering the heat fixing roll 21. Since the transferred image 19 is unfixed, fM
Since the image will simply be taken, sufficient care must be taken when designing guides, etc.

紙22は記録紙スタッカ23へ、順次、積み重ねられる
。一方、感光ドラム1にはわずかな転写残りの残留現像
材が残っているので、残留電荷除去のための除電光源2
5により除電の後、残留現像材除去部26を通過し、か
き落し板28によってかき落され残留現像材27として
除去部26の中にたまる。この状態で、ドラム表面はク
リーニングされた状態29となって再使用が可能な状態
に戻る。
The papers 22 are stacked one after another on a recording paper stacker 23. On the other hand, since a small amount of residual developing material remaining after transfer remains on the photosensitive drum 1, a static eliminating light source 2 is used to remove the residual charge.
5, the developer passes through the residual developer removing section 26, is scraped off by the scraping plate 28, and accumulates in the removing section 26 as residual developer 27. In this state, the drum surface is in a cleaned state 29 and returns to a state in which it can be reused.

〔発明の効果〕〔Effect of the invention〕 【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を説明するCaFz膜厚と基板のそりと
の関係を表わす線図、第2図は基板の熱膨張係数と基板
のそりとの関係を示す線図、第3図はホトルミネセンス
強度とその半値幅をを示す線図、第4図は本発明の一実
施例のLEDを示す断面図、第5図はヘッドの構造を示
す説明図、第6図はLEDプリンタを示す構造図である
。 1− Cu、2− Ca F x、 4− A u、6
・・・保護膜、高1図 CαF2 膜、1.(μ゛m) 不2−日 東3図 基板め1類 第5日 高6図
Fig. 1 is a diagram showing the relationship between the CaFz film thickness and the warpage of the substrate to explain the present invention, Fig. 2 is a diagram showing the relation between the thermal expansion coefficient of the substrate and the warpage of the substrate, and Fig. 3 is a diagram showing the relationship between the CaFz film thickness and the warpage of the substrate. A diagram showing the luminescence intensity and its half-width, Fig. 4 is a cross-sectional view showing an LED according to an embodiment of the present invention, Fig. 5 is an explanatory diagram showing the structure of the head, and Fig. 6 shows an LED printer. It is a structural diagram. 1-Cu, 2-CaFx, 4-Au, 6
...Protective film, height 1 figure CαF2 film, 1. (μ゛m) Fu2-Nitto 3 map board 1st class 5th Hidaka 6 diagram

Claims (1)

【特許請求の範囲】[Claims] 1、結晶質の基板上に、中間層が設けてあり、さらにそ
の上部にp型、n型のGaAs膜が設けられた構造から
なる薄膜発光素子において、上記結晶質は金属の単結晶
であり、中間層は絶縁体であることを特徴とする薄膜発
光素子。
1. In a thin film light emitting device having a structure in which an intermediate layer is provided on a crystalline substrate, and p-type and n-type GaAs films are further provided on top of the intermediate layer, the crystalline material is a single crystal of metal; , a thin film light emitting device characterized in that the intermediate layer is an insulator.
JP62006006A 1987-01-16 1987-01-16 Thin film light-emitting element Pending JPS63175485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62006006A JPS63175485A (en) 1987-01-16 1987-01-16 Thin film light-emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62006006A JPS63175485A (en) 1987-01-16 1987-01-16 Thin film light-emitting element

Publications (1)

Publication Number Publication Date
JPS63175485A true JPS63175485A (en) 1988-07-19

Family

ID=11626644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62006006A Pending JPS63175485A (en) 1987-01-16 1987-01-16 Thin film light-emitting element

Country Status (1)

Country Link
JP (1) JPS63175485A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6404476B1 (en) 1989-09-01 2002-06-11 Semiconductor Energy Laboratory Co., Ltd. Device having an improved connective structure between two electrodes

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6404476B1 (en) 1989-09-01 2002-06-11 Semiconductor Energy Laboratory Co., Ltd. Device having an improved connective structure between two electrodes
US6956635B2 (en) 1989-09-01 2005-10-18 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal device and manufacturing method therefor

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