JPS63175380A - Dimming control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention Technical Field The present invention selects the signal with the highest level from among the dimming signals set by a plurality of dimming operation consoles, and controls the dimmer using the dimming signal with the maximum level. This invention relates to a dimming control method.

BACKGROUND ART Conventionally, when a plurality of events are held simultaneously in a multipurpose hall or the like, a plurality of light control consoles are sometimes used. In such a case, the number of consoles that control this dimmer is limited to one. Therefore, if you try to control all the dimmers at once, you will have to operate all the consoles at once, which causes problems such as manual labor and timing shifts. In addition, when controlling one dimmer from a plurality of consoles, for example, as shown in FIG. OR circuit 62
can be controlled with high priority. However, as the number of dimming consoles increases, the diode OR circuit 62 also becomes larger, making the circuit configuration more complex.

In another prior art, digital dimming level data is transmitted in parallel from an operator console via a transmission line to a CPU (processing circuit).
is given, and the maximum value calculation is performed by this CPU. Such prior art requires maximum value calculation by a CPU or the like, which complicates the configuration. Furthermore, it is not possible to perform high-speed transmission accordingly.

Purpose An object of the present invention is to provide a dimming control method that can select and transmit the highest level signal from among the dimming signals of a plurality of dimming control consoles at high speed and with a simple configuration. That's true.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention. A plurality of dimming operation consoles A 1 , A 2 , ..., An (indicated by reference mark A when collectively referred to) are connected to a dimming signal transmission mz
individually connected to i. The highest value of the dimming signals from the dimming operation consoles A1 to An is selected as described later, and the transmission #I
! 1 to the control device 1. Light control console A1
~An and the control device 1 are connected via a synchronization signal transmission line 12. A synchronizing signal from the control device 1 is given to each of the dimming consoles A1 to An through the transmission #i, 1'2, and the dimming signal is transmitted in synchronization with this synchronizing signal.

The light control consoles A1 to An include transmission output control circuits Bl, B2 .・
...=B+t (indicated by the reference mark B when collectively referred to) is provided. The control device 1 converts the digital signal received via the transmission PA 1 into an analog signal, and outputs this analog dimming signal to each of the dimmers CI, C2, . . . , C-. Accordingly, each of the dimmers 01 to C- is controlled to dim.

FIG. 2 is a timing chart during transmission of the dimming signal, and FIG. 13 is a block diagram showing the basic configuration of the transmission output control circuit B. The light control consoles A1 to An are shown in Figure 2 (2
), channel data CHI, CH2,...
, OH logic (generally referred to as 1icH), and this channel data C11 is composed of 8 bits from the most significant bit (D7) to the least significant bit (D0) as shown in FIG. In addition, when referring to D collectively, it is indicated by a reference mark.

The transmission output control circuit B includes a memory 2 that stores 8-bit digital dimming data, a serial transmission circuit 3 that serially transmits the dimming data from the memory 2 from the most significant bit D7 to the least significant bit DO. A transmission propriety data creation circuit 4 includes a switch SW interposed between the serial transmission circuit 3 and the transmission line 71, a transmission propriety data creation circuit 4, a transmission propriety determination circuit 5, and a channel number creation circuit 6.
is the dimming data from the serial transmission circuit 3 and the transmission line l
Transmission line signal data on the transmission line 5 are input, and the transmission judgment circuit 5 generates propriety data according to the logical state of these data.
Derived as follows. The transmission permission determination circuit 5 inputs the transmission permission data and the dimming data, and derives a control signal to the switch SW to change the switching mode of the switch SW according to the logical state of these data. The channel number generation circuit 6 derives a reset signal that resets the transmission permission data to "1" so that the dimming data is transmitted at the lowest bit (DO*).

As shown in FIG. 2 (1), when a synchronization signal is given from the control device 1 via transmission #i72 at time t1, the second
Channel data CHI is transmitted as shown in Figure (2). That is, the 8-bit digital signal stored in the memory 2 is applied in parallel to the serial transmission circuit 3, so that the serial transmission circuit 3 sequentially transmits the lowest pit D7 to the lowest pit D7. When the beep D to be output is, for example, "1", the transmission permission data becomes "1", and therefore the transmission permission determination circuit 5 turns on the switch SW. This makes "1" the transmission line number 1.
will be sent to. In addition, when the pin D to be output is "O" and the transmission line signal data is "0",
The transmission permission data is "1", so the transmission permission determination circuit 5 shuts off the switch SW. Therefore "0"
is not output. When the bit to be output is "0" and the transmission line signal data is "1", the transmission possibility data creation circuit 4 sets the transmission possibility data to "0". Therefore, from then on, the transmission permission determination circuit 5 continues to cut off the switch SW. Therefore, serial transmission circuit 3
The transmission of empty bit data is interrupted. In other words,
If the dimming data of the other console is "1" and the bit data of the console is "0", the dimming of the counterfeit console is being transmitted serially starting from the most significant bit of the digital data. The signal is not at its maximum value.

Therefore, there is no need to output subsequent bit data, and transmission is interrupted. In this way, by successive comparison for each pip) D7 to Do, smaller dimming level data is not output, and finally only the maximum level data is output.

When the transmission for one channel is completed in this way, the channel number creation circuit 6 gives the channel change (no.
” is reset. By resetting this transmission enable/disable data to "1", the operator console which had stopped transmitting becomes capable of transmitting again, and the output of the next channel data CH2 is controlled in the same way as the channel data of Moe. In this way, from channel data CHI to channel data CI-I
Transmission line J to n! 1, thereby transmitting the transmission line as shown in FIG. 2 (3)! As for the transmission line signal at No. 1, the maximum level dimming signal among the dimming signals of the operating consoles A1 to An is transmitted. After the transmission of all channel data CH1 to CHn is completed in this way, as shown in FIG.
Channel data CHI is transmitted again from time t2 in synchronization with the synchronization signal shown in 1).

FIG. 5 is an electric circuit diagram showing a specific configuration of the transmission output control circuit B. FIG. A clock signal from the clock signal generation circuit 10 is applied to a channel number generation circuit 11 implemented by a counter or the like, and a parallel/serial conversion circuit 12 implemented by a shift register or the like that converts upstream parallel data into serial data. The random access 7 memory 13 includes D7 to DO 8 shown in FIG.
Dimming data consisting of bits is stored.

The channel number generation circuit 11 derives a read signal to the random access memory 13 when a predetermined count value is reached. As a result, 8-bit dimming data from the 2-band access memory 13 is input in parallel to the parallel/serial conversion circuit 12. The parallel/serial conversion circuit 12 synchronizes with the clock signal to
Transmission data from the parallel/serial conversion circuit 12, which is serially transmitted in this order from D8 to the least significant bit DO, is sent to the input terminal of the tri-state buffer 14, one input terminal P1 of the AND date 15, and the AND
It is applied to one input terminal P3 of the date 17.

The output terminal of the tri-state buffer 714 is connected to the transmission line 1.
1 and the output terminal of input buffer 16. The output from input cover 7716 is applied to the other input terminal P4 of AND date 17. The output from AND date 17 is applied to the set terminal S of the 7-lip, 70-tube FFI. This 7-lip 70-tube FFI is set when the set terminal S rises from a low level to a high level.

The reset terminal R of the lip 70 knob FFI is connected to line 73.
It is connected to the channel number creation circuit 11 via. The output terminal Q of the 7-rip 70-tube FFI is AND date 15
is connected to the other input terminal P2. The output terminal of this AND date 15 is connected to the control terminal of tristate buffer 714.

In addition, the synchronization signal from the transmission 4172 is transmitted to the input buffer 18.
as a reset signal via the channel number creation circuit 1
1 is given.

Next, the control operation of the transmission output control circuit B having such a configuration will be explained. In addition, to simplify the explanation, 3
The three dimming operation consoles A 1 , A 2 , and A 3 will be explained, and it will be assumed that the data of the first channel CH1 of the dimming manipulation consoles A 1 , A 2 , and A 3 is in the tjSi table.

Table 1 First, when a synchronization signal is applied from the synchronization signal connection fin 12 to the input buffer 18 to the channel number generation circuit 11, this channel number generation circuit 11 is connected to the reset terminal of the 7-lip 70 tube F1 via the fin 73. Deriving a high level signal to.

As a result, the 7-rip 70-tube F1 is reset.

At the same time, channel data CHI is transmitted in parallel from the random access memory 13 and applied to the parallel/serial conversion circuit 12. The parallel/serial conversion circuit 12 performs serial transmission sequentially from bit D7 to bit DO in synchronization with the clock signal.

In the light control consoles A 1 , A 2 , and A 3 , bit D7 is first output from the parallel/serial conversion circuit 12 . On the light control console A1, D7 is "0".
Therefore, the input terminal P1 of AND date 15 becomes low level. Therefore, the output of the AND date 15 becomes a low level, and the tristate buffer 14 enters a high impedance state and output is prohibited. Remaining light control console A2. A3 also beeps) D7 is "0", so the output line becomes high impedance and output is prohibited, similar to the dimming console A1. In this way, all the light control consoles A 1 , A 2 , A 3
When output is inhibited, the transmission line signal is set to rOJ by a pull-up resistor or a pull-down resistor (not shown). In addition, this! 1 Dimming control table A 1 , A 2
.

At A3, the transmission line signal is "0", so AND
The input terminal P4 of the gate 17 is at a low level, so the output of the AND date 17 is at a low level. Therefore, the 7-lip 70-tub FFI is not set.

Next, when the beep)DO is output from the parallel/serial conversion circuit 12, the beep)DO becomes "1" on the dimming control console A1.
Therefore, the input terminal P3 of the AND date 17 becomes a low level, and therefore the output terminal Q of the 7-lip, 70-tube FFI becomes a high level. On the other hand, the input terminal P1 of the AND date 15 is at a high level, so the output of the AND date 15 is at a high level. This makes the tri-state buffer 14 ready for output, and the transmission line! 1 is output. Regarding the dimmer console A2, DO is "1", so the dimmer console A2 is
Similar to 1, transmission line J! 1 is output. on the other hand,
On the light control console A3, DO is "0", so
AND5'-to 150 input terminal P1 is at a low level, and therefore the output of AND5' is at a low level. As a result, the tristate IC 7714 enters a high impedance state and output is prohibited. At this time, the remaining light control console A1. From A2, “1” is sent to the transmission line 11.
" is output, so this transmission signal line is connected to the input bag 771.
6 to one input terminal P4 of the AND date 17. The other input terminal P3 of the AND date 17 is at a high level as described above, so the output of the AND date 17 is at a high level. As a result, the 7-rip, 70-tube FFI is set, and the output terminal Q is held at a low level. Therefore, in this dimming operation console A3, the output of the beep) DO is prohibited, and the subsequent outputs are also prohibited.

Next, when the beep) D5 is output from the parallel/serial conversion circuit 12, the beep)DO becomes "1" on the dimming control console A1.
Therefore, the input terminal P3 of this AND date 17 becomes a low level, and therefore the output of the AND date 117 becomes a low level. With this, 7 lips 70 tubes FF
The output terminal Q of I is at a high level, while the input terminal P1 of AND date 15 is at a high level, so that A
The output of the ND gate 15 becomes high level. As a result, the tristate buffer 14 becomes ready for output.
“1” is output to the transmission line 11. In the light control console A2, D5 is "0", so the above-mentioned light control console A3
Similarly to the case of beep) D7, the output of this beep) D6 is prohibited, and the output of subsequent beeps) D5 to DO are also prohibited.

Therefore, from then on, bits D4 to D4 of the dimming console A1
DO is sequentially output to transmission #X-1. In this way, the maximum value among the plurality of dimming data is selected and output.

After the transmission of the channel data CHI is completed, the channel number generation circuit 11 derives a reset signal to the 7 ribs and 70 ribs FF1. As a result, the light control console A 1 , A
2 and A3 perform the transmission process of the next channel data CH2 in the same manner as described above, so that among the respective channel data CHI to CHm from the plurality of dimming operation consoles A1, A2, and A3. The maximum value of channel data CH
Only 1 to CHm are selected and transmission #l! 1.

After the transmission of the channel data CH1 to CHm is completed in this manner, a synchronization signal is applied to the channel number generation circuit 11 via the input buffer 18, and the channel number generation circuit 11 is reset. With this, the light control console A
1 t A 2 + A 3 is again the channel data C
FIG. 6 is a specific electrical circuit diagram of the control device i1. The dimming data transmitted via the transmission line 11 is sent via an input buffer 20 to a serial/parallel conversion circuit 21 realized by a register.
given to. The serial/parallel conversion circuit 21 includes
A clock signal is applied from the clock signal generation circuit 22, and the serial/parallel conversion circuit 21 outputs parallel data to the digital/analog converter 23 in synchronization with this clock signal. Analog dimming data from the digital/analog converter 23 is given to a sample hold circuit 24. Further, the clock signal from the clock signal generation circuit 22 is given to a channel number generation circuit 25 realized by a counter, and this channel number generation circuit 25 sends a high signal to the sample and hold circuit 24 every time transmission of one channel data is completed. Derive the level signal. As a result, the channel data CH is transferred from the sample hold circuit 24.
I, CH2,..., CHn are dimmers C1, C2,...
...is sequentially output to yCn. Note that the channel number generation circuit 25 detects the end of reception up to channel data CH+a, and outputs a synchronization signal to the transmission line 12 via the output rose 772G. As a result, a synchronizing signal is given to the channel number creation circuit 11 of the transmission output control circuit 81 to Bn of each dimming console A1 to An, the channel number creation circuit 11 is reset, and the transmission output control circuit 81 to Bn of each dimmer console A1 to An is reset. , the transmission process is started from channel data CHI.

FIG. 7 is an electrical circuit diagram of a transmission output control circuit according to another embodiment. This embodiment is similar to the previous embodiment, and corresponding parts are given the same reference numerals.It should be noted that the transmission line 12 is omitted in this embodiment, and each channel data C0 One bit data of "0" is inserted in between. In other words, 1 channel data is (pi)D7-D
It consists of 9 bits with "0" added to the beginning of "0" and this bit (D7). In addition, a serial/parallel conversion circuit 30 realized by a N7 trendostar that converts serial data to parallel data, and [0FF(H)J
A reference data setting circuit 31 in which (H indicates hexadecimal notation) is stored, and a comparison circuit 32 that compares the output from the serial/parallel conversion circuit 30 and the output from the reference data setting circuit 31 are provided. A clock signal from the clock signal generation circuit 10 is given to the serial/parallel conversion circuit 30, and in synchronization with this clock signal, the serial/parallel conversion circuit 30 transmits [J! The transmission line signal data on i is input and output to the comparison circuit 32. In the random access memory 13, after the channel data CHa, [OF (H)J
is stored, thereby channel data CH
- After the transmission of l'O to the serial/parallel conversion circuit 30,
F F (H)J is output, and furthermore, [
0FF(H)J is given.

Since this matches the output from the reference data setting circuit 31, the comparison circuit 32 outputs a reset signal to the channel number generation circuit 11, thereby resetting the channel number generation circuit 11.

In this way, all the dimming control consoles A1 to An are reset, and transmission of channel data is started again from channel data CH1 at the same time. In addition, since rOFF(H)J is used to reset the channel number creation circuit 11, the channel data CH1 to CHSO1, beep) D7 to DO are all "
1" is not used. Thus, in this embodiment, the transmission line! 2 can be omitted.

FIG. 9 is an electrical circuit diagram of a transmission output control circuit according to still another embodiment. This embodiment is similar to the previous embodiment,
Corresponding parts are given the same reference numerals. In this embodiment, a relay switch SWI is interposed in the middle of the output line to the transmission line No. 1 of each of the dimming consoles A1 to An.
taJ? Relay switch SW2 is placed in the middle of the input line of 2.
is intervened.

These relay switches SWI and SW2 are relay coils 40
It is configured to conduct when the relay coil 40 is energized and to shut off when the relay coil 40 is demagnetized. Further, an AND date 41 and a 7-lip 70-tube FF2 are provided.

One input terminal of AND date 41 is AND date 15
The other input terminal of the AND date 41 is connected to the output terminal Q of the 7-rip, 70-tube FF2.

The output terminal of AND date 41 is connected to the control terminal of tristate buffer 14. 7 lip 70 lip FF2
The reset input terminal R of is connected to the output terminal of the input part 7a18. A set input terminal S of the 7-rip, 70-tube FF2 is connected to the connection point between the resistor 42 and the capacitor 43.

One side of the resistor 42 is connected to the power supply voltage Veal, and one side of the capacitor 43 is grounded. With such a configuration, when the power is turned on, the relay coil 40 is excited, which makes the relay switches SWI and SW2 conductive and enables transmission. Furthermore, when the power is cut off, the relay coil 40 is demagnetized, which cuts off the relay switches SWI and SW2, and the dimmer console A is connected to the transmission line No. 1.
be completely separated from. Therefore, when the power is cut off, it is possible to prevent other devices from being adversely affected.

Furthermore, when the power is turned off and turned on, the switches SWl and S
Although W2 becomes conductive, the set input terminal S of the 7-rib, 70-tube FF2 becomes a high level immediately after the power is turned on, and therefore the output terminal Q of the 7-rib, 70-tube FF2 becomes a low level. Therefore, one input terminal of AND date 41 is at a low level, so the output from AND date 41 is at a low level, and the output line remains high. After that, a synchronization signal is given to the reset terminal R of the 7-lip 70-tube FF2, which resets the 7-lip 70-tube FF2, and at the same time, the channel number creation circuit 11 is reset, which causes the channel CH1 to Output is synchronized with the control console.

Therefore, it is possible to eliminate the adverse effects of synchronization when the power is turned on.

Effects As described above, according to the present invention, the maximum value of a plurality of dimming signals can be selected and dimming control can be performed using the selected dimming signal. Furthermore, only one transmission line can be used to transmit the dimming signal, regardless of the number of dimming operation consoles. In addition, diode OR circuits and CPUs as explained in the prior art section
This eliminates the need for maximum value calculations such as, etc., and the configuration can be simplified.

Furthermore, since there is less processing per channel, multi-channel transmission and high-speed transmission are possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a timing chart showing the transmission processing operation of a dimming signal, and FIG. 3 is a basic configuration of transmission output control circuit B. Block diagram, Figure 4 is a diagram showing the data structure of one channel dimming level data, Figure 5 is transmission output control circuit B
TT46 is an electric circuit diagram showing the configuration of the control device 1, FIG. 7 is an electric circuit diagram of another transmission output control circuit, and FIG. 8 is a transmission output control circuit shown in FIG. 7. Figure 9 shows the data structure of 1 channel data when using
This figure is an electric circuit diagram of another transmission output control circuit, and FIG. 10 is an electric circuit diagram of a prior art. DESCRIPTION OF SYMBOLS 1... Control device, 2... Memory, 3... Serial transmission circuit, 4... Transmission propriety data creation circuit, 5...
Transmission availability 14 Constant [il path, G, 11.25...Channel number creation four paths, 10.22...Clock signal generation circuit, 12...Parallel/serial conversion circuit, 13
... Random access memory, 21,30... Serial/parallel switching circuit, 14... Tri-state buffer, 15.17.41... AND de
- G, 1 6, 20. 1 8... Input parts 77, A1 to 8n... Light control console, Bl to Bn
...Transmission output control circuit, 01-Cn...Dimmer, F
F1. FF2-7 lip 7 a '7b, SW, SWI
. SW2...Switch, 40...Relay coil,! 1
...Transmission line for dimming data, J! 2... Transmission line agent for synchronization signal Patent attorney Number of strokes Keiichi No. 31! Y Figure 4 Figure 10 Procedural amendment November 24, 1986

Claims (1)

[Claims] Dimming that selects the signal with the highest level among the dimming signals set by a plurality of dimming control consoles and controls the dimmer using the dimming signal with the highest level. In the control method, the plurality of dimmer consoles are individually connected to a single transmission line, and each dimmer console has a logic combination of digital dimming level data and transmission line signal data on the transmission line. A transmission output control circuit is provided to control the output of dimming level data to the transmission line, and the transmission output control circuit sequentially outputs the dimming level data from the most significant bit to the least significant bit in this order. transmit,
During this transmission, the bits are successively compared starting from the upper bit, and when the bit is at high level, the bit is output to the transmission line, when it is at low level, output is prohibited, and when the bit is at low level, the bit is output to the transmission line. When the dimming data is at a high level, the output of subsequent data is prohibited, and when the output of all the dimming control consoles is prohibited, the transmission line signal is set to a low level. Light control method.