JPS63175260U

JPS63175260U -

Info

Publication number: JPS63175260U
Application number: JP4374988U
Authority: JP
Priority date: 1988-03-31
Filing date: 1988-03-31
Publication date: 1988-11-14

Description

[Brief explanation of the drawing]

第１図は本考案の第１の実施例を示す図、第２
図は第１の実施例の動作を説明するための図、第
３図は切り換え制御を含むプログラムの流れを示
す図、第４図は本考案の第２の実施例を示す図お
よび第５図は第２の実施例の動作を説明するため
の図である。第１図から第５図において、１……第１のマイ
クロプロセツサ、２……第２のマイクロプロセツ
サ、３……アドレス・バス、４……プロセツサモ
ードフリツプフロツプ、５……切替制御回路、６
……記憶部、７……データ・バス、８……フリツ
プフロツプセツトリセツト制御回路、９……制御
実行部、１０……マイクロプロセツサ。 FIG. 1 is a diagram showing the first embodiment of the present invention, and FIG.
The figures are for explaining the operation of the first embodiment, FIG. 3 is a diagram showing the flow of a program including switching control, FIG. 4 is a diagram showing the second embodiment of the present invention, and FIG. FIG. 3 is a diagram for explaining the operation of the second embodiment. 1 to 5, 1...first microprocessor, 2...second microprocessor, 3...address bus, 4...processor mode flip-flop, 5... switching control circuit, 6
...Storage unit, 7...Data bus, 8...Flip-flop reset control circuit, 9...Control execution unit, 10...Microprocessor.

補正昭６３．４．１考案の名称を次のように補正する。考案の名称データ処理装置実用新案登録請求の範囲、図面の簡単な説明を
次のように補正する。【実用新案登録請求の範囲】第１のマイクロプロセツサと、この第１のマロクロプロセツサとは種類の異な
る第２のマイクロプロセツサと、前記第１のマイクロプロセツサと前記第２のマ
イクロプロセツサとに共有されるアドレスバスと
、このアドレスバスに接続され前記第１のマイク
ロプロセツサ用のプログラムおよび前記第２のマ
イクロプロセツサ用のプログラムを記憶する記憶
手段と、この記憶手段からのプログラムを解読する解読
手段と、この解読手段からの解読結果に応答して前記第
１および第２のマイクロプロセツサのいずれが動
作状態であるか否かを表示する表示手段と、この表示手段の表示に応答してマイクロプロセ
ツサのうちの１つを動作させ他の１つを停止させ
るよう指示する制御手段とを含むことを特徴とす
るデータ処理装置。【図面の簡単な説明】第１図は本考案の一実施例を示す図、第２図は
一実施例の動作を説明するための図、第３図は切
り換え制御を含むプログラムの流れを示す図であ
る。第１図から第３図において、１……第１のマイ
クロプロセツサ、２……第２のマイクロプロセツ
サ、３……アドレス・バス、４……プロセツサモ
ードフリツプフロツプ、５……切替制御回路、６
……記憶部、７……データ・バス、８……フリツ
プフロツプセツトリセツト制御回路、９……制御
実行殊、１０……マイクロプロセツサ。 Amendment April 1, 1981 The name of the invention is amended as follows. Title of the invention: Data processing device The scope of claims for utility model registration and the brief description of the drawings are amended as follows. [Claims for Utility Model Registration] A first microprocessor, a second microprocessor different in type from the first microprocessor, and the first microprocessor and the second microprocessor. an address bus shared by the processor; a storage means connected to the address bus for storing a program for the first microprocessor and a program for the second microprocessor; a decoding means for decoding the program; a display means for displaying which of the first and second microprocessors is in an operating state in response to the decoding result from the decoding means; A data processing device comprising: control means for instructing one of the microprocessors to operate and the other to stop in response to a display. [Brief Description of the Drawings] Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram for explaining the operation of the embodiment, and Fig. 3 is a diagram showing the flow of a program including switching control. It is a diagram. 1 to 3, 1...first microprocessor, 2...second microprocessor, 3...address bus, 4...processor mode flip-flop, 5... switching control circuit, 6
. . . storage unit, 7 . . . data bus, 8 . . . flip-flop reset control circuit, 9 . . . control execution function, 10 .

Claims

[Claims for Utility Model Registration] (1) A first microprocessor; a second microprocessor different in type from the first microprocessor; the first microprocessor and the second microprocessor; an address bus shared by the microprocessor; a storage means connected to the address bus for storing a program for the first microprocessor and a program for the second microprocessor; a decoding means for decoding a program from the decoding means; a display means for displaying which of the first and second microprocessors is in an operating state in response to the decoding result from the decoding means; 1. A data processing apparatus comprising: control means for instructing one of the microprocessors to operate and the other to stop in response to an indication from the means. (2) a microprogram controlled processor, a microprocessor, an address bus shared by the microprogram controlled processor and the microprocessor, and a program connected to the address bus for the microprogram controlled processor; and storage means for storing a program for the microprocessor; decoding means for decoding the program from the storage means; a display means for displaying whether or not one of the microprocessors is in an operating state; and a control means for instructing one of the microprocessors to operate and the other one to stop in response to the display on the display means. A data processing device comprising: