JPS63172585A - Picture memory device - Google Patents

Abstract

PURPOSE:To secure the continuity of the phase of a color subcarrier without deteriorating the activity efficiency of a picture memory by initializing the memory address of the picture memory which is designated when the composite video signal is written into/read from the picture memory at a timing when the composite video signal synchronizes with the color subcarrier. CONSTITUTION:The write termination timing of the video signal into the picture memory 3 or the initialization timing of the memory address of the picture memory 3 being a read termination timing are synchronized with a color subcarrier output signal 200. Consequently, the write/read period of the video signal goes to integer-multiplied color subcarrier period. Thus, the phase of the color subcarrier of the video signal which has been read from the picture memory 3 can securely set continuous. It comes to be unnecessary to write picture data for Nf cycle of the color subcarrier into the picture memory 3, and the activity efficiency of the picture memory 3 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image memory device used for obtaining still images in televisions, VTRs, and the like.

(Prior Art) Conventionally, still images are obtained by using an image memory device that writes a video signal into an image memory and reads out the written video signal. In other words, this type of image memory device writes a so-called composite video signal including a color width carrier wave into the image memory for one field period, and reads out this composite video signal. The wave number of the width carrier wave is not an integer as shown in the NTSC system and PAL system joint equation.

Therefore, if you simply write/read one field (or one frame) worth of composite video signal into the image memory, the phase of the color width carrier wave will change between fields (or between frames) as shown in Figure 3 (C). Due to the discontinuity, colors may not appear on some television receivers.

Conventionally, in order to solve the above problem, image data for an integer number of cycles of the color width carrier wave is written to the image memory for each address of the image memory, or color data is written to a number address (NA address) of the image memory. Image data for Nf cycles of the width carrier wave is written, and the writing or reading end timing (memory address initialization timing) is synchronized with the clock signal of the address counter, and the phase of the color width carrier wave is continuous. A method is adopted in which the phase of the color width carrier wave of the video signal is made continuous by using a timing signal.

However, in the above method, image data for an integer number of cycles of the color width carrier wave is written to one address of the image memory, or image data for Nf cycles of the color width carrier wave is written to a number address (NA address) of the image memory. Moreover, since the memory address reset timing is synchronized with the address clock under the condition that the color width carrier wave is continuous, the usage efficiency of the image memory decreases and the vertical and horizontal synchronization signals included in the video signal become discontinuous. was there.

(Problems to be Solved by the Invention) As mentioned above, in the conventional image memory device, in order to maintain the phase continuity of the color width carrier wave when writing/reading a composite video signal to/from the image memory, the image memory This has the disadvantage that the efficiency of using the device is lowered, and in some cases, the vertical and horizontal synchronizing signals included in the video signal become discontinuous.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, and to ensure continuity of the phase of the color width carrier wave when writing/reading a composite video signal to/from the image memory without reducing the usage efficiency of the image memory. An object of the present invention is to provide an image memory device capable of storing images.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an image memory device for obtaining a still image signal by writing/reading a composite video signal into/from an image memory. The image processing apparatus is configured to include memory address initialization means for initializing a memory address of the image memory specified at the time of reading at a timing synchronized with a color width carrier wave of the composite video signal.

(Function) In the image memory device of the present invention, the memory address initialization means initializes the memory address of the image memory specified when writing/reading the composite video signal to/from the image memory. This is done at a timing synchronized with the width carrier wave. Therefore, the writing and reading period of the composite video signal to the image memory becomes an integral multiple of the color width carrier wave cycle, and the phase of the color width carrier wave of the read video signal becomes continuous.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of the image memory device of the present invention. Reference numeral 1 denotes a reproduced video signal processing circuit that inputs the reproduced signal from the head and performs various processing, 2 an A/D converter that converts the analog composite video signal from the reproduced video signal processing circuit 1 into a digital composite video signal, and 3 is an image memory (field memory) in which digital composite video signals are read and used.
4 is a D/A converter that converts the digital composite video signal into an analog composite video signal; 5 is a write/read control circuit that controls writing/reading of the composite video signal to and from the image memory 3; 6 is a color width carrier wave as a reference. Reference color width carrier oscillator 7 generates an output signal 200, 7 generates an input signal 172
8 is a multiplier circuit that multiplies the input signal by 6 times; 9 is a frequency divider circuit that divides the input signal into 178; 1
0 is a signal converter that converts the serial signal of the image memory 3 into a parallel signal when loading and the parallel signal into a serial signal when reading, 11 is an address counter that outputs the address of the image memory 3, and 12 is from the address counter 11. an address decoder for decoding the address of 13.
14 is a D flip-flop that detects the edge portion of the address reset signal; 15 is a D flip-flop that is set by the output of the address decoder 12; and 16 is an OR circuit that takes the logical sum of the outputs of the D flip 70 tubes 14 and 15. .

Next, the operation of this embodiment will be explained. First, a reproduced signal 100 from a VTR head (not shown) is input to the reproduced video signal processing circuit 1. A luminance signal is separated from this reproduced signal and subjected to FMI adjustment, and a color signal is extracted from the reproduced signal. After being separated and frequency converted, both signals are combined again to form an analog composite video signal, which is output to the A/D converter 2. At this time, the reproduced video signal processing circuit 1
is the color width carrier output signal 2 from the reference color width carrier wave oscillator 6.
00 is supplied and the above processing is performed. Further, the color width carrier wave output signal 2 of the frequency fsc (4.43 MH2 in the case of PAL system) outputted from the reference color width carrier wave oscillator 6
00 is multiplied by 6 in multiplier circuit 8 and then converted to 172 in frequency divider circuit 7.
Multiplied by frequency 3f. This is the A/D signal.
It is supplied to the A/D converter 2 as a (sampling) clock signal 300. Thereby, the A/D converter 2 converts the analog composite video signal into a digital composite video signal (for example, 6 bits) using the clock signal, and outputs the converted signal to the signal converter 10. For this reason, the digital composite video signal is serial-to-parallel converted by the serial-to-parallel converter of the signal converter 10, with 4 samples as one set.
4-bit parallel image data 401- is supplied from the signal converter 10 to the image memory 3. On the other hand, the write/read control circuit 5 supplies a write timing signal 501 to the image memory 3 based on the color width carrier wave output signal 200 supplied from the reference color width carrier wave oscillator 6, and also supplies the image memory 3 with an address counter 11. A memory address 600 is supplied from. As a result, 24-bit parallel image data 401 is sequentially written into the image memory 3. Here, since the digital composite video signal (same as the parallel image data 401) is written with four samples corresponding to one address in the image memory 3, the frequency of the address clock 700 that causes the address counter 11 to count up is 3/3. 4f. bawl.

Therefore, the address clock 700 is generated by multiplying the output signal 200 of the reference color width carrier wave oscillator 6 by 6 in the multiplier circuit 8 and then dividing the frequency by 8 in the frequency dividing circuit 9. Therefore, data for 473 wavelengths of color width carrier waves are written into one address of the image memory 3. Figure 4 shows that image memory 3 is PA
In the case of an L-type field memory, the number of color width carrier waves per memory address, the total number of addresses required to write one field of video signal, and the memory element (
258 indicates the number of used bits (address 64K x data 4 bits), and when the color width carrier wave number is 473, 6 memory elements are required. However, the sampling frequency is 3fSc and the quantization is 6 bits.

As described above, the data (digital composite video signal) written in the image memory 3 is read out as shown below. That is, the data at the address of the image memory 3 specified by the memory address 600 output from the address counter 11 is read out by the read timing signal 502 supplied from the write/read control circuit 5, and this is read out by the signal converter 10. It is output to the parallel/serial converter 42. The parallel/serial converter 42 converts the input data (parallel) into serial data, and converts the input data to the D/A converter 4.
Output to. As a result, the D/A converter 4 outputs an analog composite video signal 800. Therefore, a still image can be obtained by repeatedly and continuously reading out the data in the image memory 3. Note that the memory address clock 700 and the D input to the D/A converter 4 at the time of reading are
The /A clock 300 has the same frequency as the memory address clock 700 during writing and the A/D clock 300 supplied to the A/D converter 2.

Next, the memory address reset operation will be explained. By the way, the memory address reset signal indicating the division of one field has a period of one frame, for example (PAL:
25H2) is a switching pulse of 1000,
It is input from terminal 16. In the half cycle of the head switching pulse, that is, in one field period, the wave number of the color width carrier wave originally has a fraction.

Therefore, in order to make the phase of the color width carrier wave continuous between consecutive fields when reading out from the image memory 3 continuously or when changing from the writing state to the reading state, it is necessary to It is only necessary that the end timing of writing or reading of one field's worth of composite video signal, that is, the initialization of the memory address, be synchronized with the color width carrier included in the composite movie signal.

Therefore, a method of periodizing the head switching pulse 1000 and the color width carrier wave will be described below. Head switching pulse 1 shown in FIG. 2 (A) input from terminal 16
000 is the clock input terminal G of the D flip-flop 13
Since it is input to K, the value "H" applied to the output terminal Q of the D flip-flop 13 at the rising edge of the head switching pulse 1000 is applied to the input terminal as shown in FIG. 2(B).
The output is as shown in .

This output is input to the input terminal of the D flip-flop 14, and the color width carrier wave output signal 200 shown in FIG. 2(C) is input to the clock input terminal GK of the D flip flop 14. The output signal from the output terminal Q of the D flip-flop 14 becomes high level as shown in FIG. 2(D) in synchronization with the rise of the color width carrier wave output signal 200. On the other hand, since the output signal from the output terminal ◇ of the D flip-flop 14 becomes low level, the D flip-flop 13 is cleared;
The output terminal Q of becomes low level. Therefore, at the next rising edge of the next color width carrier wave output signal 200, the output terminal Q of the D flip-flop 14 becomes low level. As a result, an address clear pulse 1100 for one period of the color width carrier wave output signal 200 is obtained via the OR circuit 16, and this pulse is input to the clear terminal of the address counter 11. Therefore, the memory address 600 output from the address counter 11 is 665 as shown in FIG. 2(E).
Next to address 04 is address O. Such image memory 3
By initializing the memory address, a new video signal (parallel data 401) ml is written into the image memory 3, or a new readout of the written video signal from the image memory 3 is performed. Furthermore, the point in time when the output of the address counter 11 that specifies the write or read address (memory address) to the image memory 3 becomes address O is the head switching pulse 1000 as shown in FIGS. 2(A) and (E). Since it is delayed from the rising timing and synchronized with the color width carrier output signal 200,
In readout mode, subsequent images will be delayed slightly. FIG. 3 shows this situation.

That is, FIG. 3 (A> is, for example, a video signal waveform processed by the reproduced video signal processing circuit 1 in FIG. 1, and FIG.
) is the output signal waveform from the D/A converter 4 when the above synchronization process is performed, and TD in the figure indicates the delay between the two signals. Note that FIG. 3(C) shows the output signal waveform from the D/A converter 4 when no synchronization processing is performed, and it can be seen that the phase is discontinuous. On the other hand, in this example in which the synchronization process is performed as shown in FIGS. 3A and 3B, the phase continuity of the color width carrier wave is ensured in the writing or reading operation to the image memory 3. Note that input reproduction signal 100 and head switching pulse 1
Even if jitter is included in 000, the above operation does not change.

After the address has been cleared as described above, the address in the next field is cleared by the address decoder 12.
This is done by the output of That is, the address decoder 12 detects that the address output of the address counter 11 becomes 68504, and this detection output is input to the D flip 70 knob 15. As the clock for this D flip-flop 15, the color width carrier wave output signal 200 is used similarly to the D flip flop 70 block 14. Therefore, the detection output of the address decoder 12 is also synchronized with the color width carrier wave and then inputted to the address counter 11 as a head clear pulse 1100 via the OR circuit 16. Further, address clearing of the next field is again performed by the output signal of the D flip-flop 14 mentioned above. The reason for the above circuit configuration is that the frequency of the head switching pulse is 25H2 (PAL system), and only one edge of the head switching pulse is used to clear the address, and the middle point (near the other edge of the switching pulse) ) is caused by the address decoder 12 to generate the address clear pulse. Note that if the image memory 3 is a frame memory,
The address decoder 12 and D flip-flop 15 become unnecessary.

By the way, mode switching of the image memory 3 is performed by write/read timing signals 501 and 502 output from the write/read control circuit 5. These write/read timing signals 501 and 502 are mode signals 1200 . Control pulse 1 used to control the phase of the capstan motor of a VTR
300. It is formed by synchronizing the head switching pulse i ooo and the color width carrier output signal 200 of the color width carrier oscillator 6 . For example, if the VTR is in slow playback mode, the image memory 3
After writing the digitized video signal to
After the written video signal is read out from the image memory 3 several times, the operation is repeated in which the data is loaded into the image memory 3 again.

According to this embodiment, the initialization timing of the memory address of the image memory 3, which is the end timing of writing or reading out the video signal to the image memory 3, is synchronized with the color 5vlW1 transmission output signal 200. The t loading/reading period of the video signal is an integral multiple of the color width carrier wave cycle, thereby ensuring that the phase of the color width carrier wave of the video signal read out from the image memory 3 is continuous. Further, it is no longer necessary to write image data for Nf cycles of the color width carrier wave into the image memory 3 as in the conventional case, and the usage efficiency of the image memory 3 can be improved.

[Effects of the Invention] As described above, according to the image memory device of the present invention, the phase of the color width carrier wave when writing/reading a composite video signal to/from the image memory can be adjusted without reducing the usage efficiency of the image memory. This has the effect of ensuring continuity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image memory device of the present invention, FIG. 2 is an operation waveform timing diagram of the image memory device shown in FIG. 1, and FIG. 3 is an image of the image shown in FIG. 1. Video signal waveform diagram of each part in the memory device, Figure 4 is PAL
This is a diagram showing the wave number of color width carrier waves per one memory address in a system field memory, the number of addresses required to store one field, and the number of memory elements used. 1... Reproduction video signal processing circuit 2... A/D converter 3... Image memory 4... D/A converter 5... Write/read control circuit 6... Reference color width carrier wave Oscillator 7.9...Frequency divider circuit 8...Multiplier circuit 10...Signal converter 11...Address counter 12...Address decoder 13, 14.15...D flip-flop agent Patent attorney Noriyoshi Chika Hiroshi Uji Diagram 2 < 3.

Claims (1)

[Claims] In an image memory device that obtains a still image signal by writing/reading a composite video signal to/from an image memory, initialization of a memory address of the image memory specified when writing/reading a composite video signal to/from the image memory is performed by the composite An image memory device comprising memory address initialization means that performs memory address initialization at a timing synchronized with a color width carrier wave of a video signal.