JPS63172360A - Buffer circuit for data transfer - Google Patents

Abstract

PURPOSE:To enable a data transferer to transfer data regardless of the states of other transferers by providing buffers in response to those data transferers. CONSTITUTION:Each buffer 30 is provided in response to each data transferer and one of input signal D I1 is defined as a data valid signal line. The data are fetched by the buffers 30 independently of each other in accordance with data valid signals. When these buffers 30 are filled, the buffer full signals are outputted via a buffer full signal output circuit 43. At the same time, a selection deciding means 40 selects one of buffers 30 based on the data remaining state of each buffer 30 as well as the state of the receiver of data and informs this selected buffer 30 to a multiplexer circuit 42. Thus the circuit 42 selects the relevant buffer 30 for output of data.

Description

[Detailed Description of the Invention] [Summary] In a data transfer buffer circuit used for data exchange, a plurality of buffers corresponding to data transfer sources are prepared, and a circuit that outputs buffer full (No. 8) of each buffer,
A circuit that selects a buffer according to the status of each buffer and the transfer destination, and i! By providing a circuit that sends the data read from the translated buffer, the amount of buffers required can be reduced and the amount of data transferred from multiple data transfer sources to multiple data transfer destinations can be reduced. Easy to control transfer.

[Industrial application field]

The present invention is achieved by, for example, allowing a plurality of processors to proceed with processing while exchanging data with each other.

A data transfer bus used in a multi-processor system that accomplishes one task, a 7-way circuit, and a data transfer bus that can realize a network system that exchanges data efficiently and with simple control. This relates to buffer circuits.

[Conventional technology]

An architecture that speeds up processing by arranging a large number of processors, connecting them with a communication network, dividing one task among each processor, exchanging data with each other using one communication network, and proceeding with processing in parallel. is considered.

Such systems require a device that can exchange data between processors quickly and economically using as little material as possible. However, conventionally, there is no suitable device for such data exchange, and switching is performed using, for example, a switch. Alternatively, data was exchanged by means such as reading into a common memory.

[Problems to be Solved by the Invention] FIG. 6 is a diagram for explaining the second invention in detail. In FIG. 6, 70 is a switch, 71 is a data transfer source,
72 represents a data transfer destination, 73 represents an input buffer, and 74 represents an output buffer.

When transferring data from a plurality of data transfer sources 71 to a plurality of data transfer destinations 72, for example, as shown in FIG. In a directly connected configuration, data transfer destination 7
2 conflict, it is necessary to make the data transfer of one of the processors wait, and it is necessary to control the timing of its own data transfer depending on the transfer request of the other processor.

In order to simplify this control, for example, as shown in FIG. 6(b), an input sofa 73 and an output sofa 74 with sufficient capacity are placed before and after the switch 70 to prevent conflicts in the data transfer destination 72. One idea would be to accumulate data that should be transferred in case this happens.

However, in the method shown in FIG. 6(b).

A large amount of buffers is required, especially when circuits that perform such data exchange are connected in multiple stages.

There is a problem that the buffer is wasted.

The present invention aims to solve the above-mentioned problems, and with a small buffer,
Another object of the present invention is to provide a data transfer buffer circuit that allows a data transfer source to transfer data without being aware of conflicts with other data transfer sources.

[Means for solving problems]

FIG. 1 shows an example of the basic configuration of the present invention.

In FIG. 1, 20 is a PISO (parallel in serial out) buffer, and 30 is a buffer.

31 is a selector, 40 is a selection decider, 41-0 to 41-3
．． 41-X is a register, 42 is a multiplexer circuit, 4
3 represents a buffer full signal output circuit. Also, 010~
DI3 is an input signal containing data, DO is an output signal, FO
~F3 represents a buffer full (δ number), NO~N3 represent data remaining ■ signals, RO~R3 represent read signals, DO~D3 represent data read from each buffer, and SEL represents a selection signal.

In the following description, an example will be described in which the number of data transfer sources is four and the number of data transfer destinations is also four.

The PISO buffer 20 corresponds to a data transfer buffer circuit of the present invention.

Each buffer 30 is provided corresponding to a data transfer source. The input signals DIO to D+3 to each buffer 30 are zero data including a parity bit as necessary and one data valid signal. Data is independently taken into each buffer 30 according to the data valid signal. The buffer 30 is composed of, for example, a FIFO memory,
Each buffer 30 is full (or for dark values with a large amount of data)
-), a buffer full signal is output via the buffer full signal output circuit 43.

The selection device 31 selects the buffer 3 that has accumulated the most data.
This is a circuit that preferentially selects 0, generates a data valid signal fε from, for example, a transfer destination address indicated in the data, and outputs the data. That is.

The selection decider 40 selects one of the buffers 30 based on the remaining data amount signals NO to N3 from each buffer 30 and the buffer full signal from the transfer destination.

Data read signals RO to R3 to the buffer 30 are output. It also outputs a selection signal SEL to the multiplexer circuit 42. Based on this selection signal SEL, the data selected by the multiplexer circuit 42 is outputted via the register 41-X. A data valid signal 18 indicating the data transfer destination is added to this output, and the output signal DO consists of 0 data and 4 data valid signals corresponding to the transfer destination.

[Effect]

The buffer 30 is provided corresponding to the data transfer source, and the data from the data transfer source is stored independently regardless of the transfer destination. Regardless of the original state, data can be sent with only the buffer full signal in mind.

The selection determiner 40 selects one of the buffers 30 according to the data residual state of each buffer 30 and the transfer destination state, and the data read from it is selected by the multiplexer circuit 42 and automatically output. Therefore, the buffer 30 can be utilized without wasting space or time.

At a data source or a data transfer source that relays data, simply sending data to the buffer 30 automatically sends the data 13 to the desired transfer destination.
Control is extremely simple.

〔Example〕

FIG. 2 is an example of the format of communication data used in an embodiment of the present invention, FIG. 3 is an example of the internal configuration of the buffer shown in FIG. 1, and FIG. 4 is the internal configuration of the selection determiner shown in FIG. 1. example,
FIG. 5 shows an example of a system to which the present invention is applied.

The format of communication data in the communication system in which the present invention is used is as shown in FIG. 2, for example.

One data transfer unit generally has a variable length, and the data width W is the amount of data that can be moved on the network in one clock. This data width W is called a data word, and a set of data is divided into two by data delimiter information @sD at the beginning of each data word. For example, if the data delimiter information SD is 1 bit, only H& of data is “1”.
” (END) and set the others to “0”.

Recognize data boundaries. However, if the data transfer unit is a fixed length, the data delimiter information SD is not necessary. For example, the first data word.

Contains address information of data transfer destination.

In the registers 41-0 to 41-3 shown in FIG.

Initially, data including the transfer destination address, etc., which is the first word of the data shown in FIG. 2, is launched.

The internal configuration of the buffer 30 shown in FIG. 1 is as shown in FIG. 3, for example. In FIG. 3, 50 is a memory cell array, 51 is a write address register, and 52 is a read address register.

53 represents a subtracter, and 54 and 55 represent AND circuits. C
LK represents a clock.

The data written into the memory cell array 50 is as follows.

The address pointed to by the write address register 51 is occupied. The write address register 51 is counted and amplified by the write signal Wi generated by the data valid signal.

Reading from the memory cell array 50 is performed from the address pointed to by the read address register 52. The read address register 52 is counted up by the read signal Ri generated by the selection determiner 40 shown in FIG.

The subtracter 53 calculates the difference between the value of the write address register 51 and the value of the read address register 52. This difference is the residual data amount signal Ni.

The selection decision unit 40 is notified. This signal may be the actual number of remaining data, but it also indicates the amount of data sampled to the j power of 2 by compressing the information, such as using only the upper j bits of the address for calculations, and also indicates empty. By adding one.

It is also possible to reduce the number of signal lines. For example, if the depth of the buffer is 2 words, to represent the remaining number, use 1
1 bit is required, but if j = 2, “00” is 0.
~word at 0,5, -IK word at 0.5 with "Ol",
"10" represents a word at IK ~ 1.5, "11" represents a word at 1.5 ~ 2, one line representing the sky, and one line representing the groove if necessary, per l buffer. It can be composed of 4 pieces.

Further, a buffer full signal Fi can be generated from the output of the subtracter 53.

The selection determining unit 40 shown in FIG. 1 is configured as shown in FIG. 4, for example. In FIG. 4, 60 represents a buffer selection determining circuit, and 61 represents an address decoder.

The address decoder 61 includes registers 41-- shown in FIG.
It decodes the transfer destination address on 0 to 41-3 and outputs a signal indicating the transfer destination. Buffer selection decision circuit 60
The buffer shown in Figure 1 (θ
~3) 30.

It is recognized from the output of the address decoder 61, and 5
By recognizing the buffer with the largest amount of residual data from the signals NO to N3, it is determined which buffer 30's data is to be transferred. The determination result is the read signal RO~R
3, each buffer 30 is notified. Further, No. 13 SEL for selecting the buffer 30 is output.

The multiplexer circuit 42 shown in FIG. 1 receives the selection signal SEL from the 1 selection tJ<determiner 40 and selects one of DO to D3. The register 41-X is.

Latch that value. This data is output together with four data valid signals generated from the address decoding results. This data valid signal specifies which of the four transfer destination buffers should receive this data.

In this selection situation, data delimiter information is selected by 3 selector 4.
0 indicates data being transferred (registers 41-0 to 41-
It is locked until it is detected from the data selected from 3). When the lock is released, the register 41
-0 to 41-3.

The data including the data transfer destination, which is the first word of the data, is latched and returns to the initial state.

Although the data delimiter information detection circuit is omitted in FIG. 4, there is no need to explain it here, but the circuit can be constructed using nine simple logic circuits.

The selection determiner 40 includes a PISO buffer 20 that includes the selection determiner 40.
The location information on the communication network is set internally in advance. As a result, the address decoder 6 receives the transfer destination address from the registers 41-0 to 41-3.
1 can determine which of the four destination buffers the data should be sent to.

The expression for the destination address may or may not be unique. For example, if there are 64 processors and the transfer destination is expressed in 6 bits, the transfer destination will be unique.

Only one of the four data valid signal trees becomes valid.

For example, if the transfer destination is expressed in 12 bits, and each bit of the 6-bit address is expressed in 2-bit I, OO"-
0,”Of”-1,”10”=lo “0.”11”=1
If multiple destinations are expressed at once, such as orQ, multiple of the four data valid signals become valid at the same time, allowing simultaneous transfer to multiple buffers. In this case 1 for example.

The transfer destination of '000000001001'' corresponds to the 6-bit addresses "0000QI" and 000011, and the data valid signals for these two transfer destinations are enabled. Note that such address expressions can be modified in various other ways.

FIG. 5 shows an example of a multiprocessor system using a prso buffer according to the present invention.

In FIG. 5, PO to PI5 are processors.

20-1 is a PISO buffer, and op is an output port.

IP stands for input boat.

In this example, 16 processors are divided into groups of 4 and connected in one hierarchy via PISO ports.

r'3. to processor PO. P4-P7. P8-P11
, PI2 to P15 are each a group of first floor stores. The entire processors PO to P15 are a second layer group. Output port OP and input port IP are
Connected to a host device or other external device.

For example, when sending data from the processor PO to the processor P3, one processor PO sends the data by validating only the data valid signal corresponding to the PISO buffer 20-3 among the four data valid signals. In PISO Hasofupu 20-3.

Assume that the input from the processor PO is assigned to the terminal of the input signal DIO shown in FIG.

Data is taken into the buffer (0) 30 shown in FIG. The data is then transferred to the processor P3 via the 1 selector 31.

Data transfer from processor P4 to processor pH is as follows:
PISO buffer 2O-XI, PISO buffer 20-
18. This is done via PISO buffers 20-11.

〔Effect of the invention〕

As described above, according to the present invention, data exchange between multiple data transfer sources and multiple data transfer destinations can be performed with a small number of buffers and with simple control. It is particularly useful for systems that require a large amount of data communication between processors.

[Brief explanation of the drawing]

FIG. 1 is an example of the main configuration of the present invention, FIG. 2 is an example of the format of communication data used in an embodiment of the present invention, FIG. 3 is an example of the internal configuration of the buffer shown in FIG. 1, and FIG. 4 is 1 shows an example of the internal configuration of the selection determining device shown in FIG. 1, FIG. 5 shows an example of a system to which the present invention is applied, and FIG. 6 shows a diagram explaining the problem of the present invention. In the figure, 20 is a PISO buffer, 30 is a buffer, 31
is a selector, 40 is a selection decider, 41-0 to 41-3.4
1-X is a register, 42 is a multiplexer circuit, and 43 is a buffer full signal output circuit. DIO to DI3 are input signals, Do is output signals, F0 to F
3 represents the buffer full signal, NO~N3 represents the remaining data amount signal, RO~R3 represents the read signal, and SEL represents the selection signal 6

Claims (1)

[Claims] A data transfer buffer circuit that performs data exchange for outputting data supplied from a plurality of data transfer sources to a plurality of data transfer destinations, the data transfer buffer circuit configured to perform data exchange for outputting data supplied from a plurality of data transfer sources to a plurality of data transfer destinations. a buffer (30) corresponding to the data transfer source that independently receives and stores the data, and a buffer full signal output circuit that outputs a buffer full signal when the amount of data stored in the buffer (30) exceeds a predetermined amount. (43); and a selection determiner (40) that selects one of the buffers (30) according to the remaining data state of the buffer (30) and the state of the transfer destination, and generates a data read signal for the buffer (30). ); and a selection sending circuit (42) that selects and sends out the data read out from the buffer (30) selected by the selection determiner (40). circuit.