JPS63170712U - - Google Patents
Info
- Publication number
- JPS63170712U JPS63170712U JP6487487U JP6487487U JPS63170712U JP S63170712 U JPS63170712 U JP S63170712U JP 6487487 U JP6487487 U JP 6487487U JP 6487487 U JP6487487 U JP 6487487U JP S63170712 U JPS63170712 U JP S63170712U
- Authority
- JP
- Japan
- Prior art keywords
- setting
- channel
- signals
- output port
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例による多チヤンネル
観測装置の設定状態を表示する回路図である。第
２図は従来の多チヤンネル観測装置の設定状態を
表示する回路図である。
２０…ＣＰＵを備えた装置、２２…ＣＰＵ、２
４…ＲＯＭ、２６…ＲＡＭ、２８，３０…入出力
ポート、３２…バスライン、３４…ＧＰ―ＩＢ用
のコントローラ、３６…設定スイツチ、３８…設
定データ入力ライン、４０…Ｆ／Ｆ、４２…ＸＯ
Ｒ回路、４４…設定データ出力ライン、４６…設
定状態表示器。
FIG. 1 is a circuit diagram showing the setting state of a multi-channel observation device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the settings of a conventional multi-channel observation device. 20...device equipped with CPU, 22...CPU, 2
4... ROM, 26... RAM, 28, 30... input/output port, 32... bus line, 34... controller for GP-IB, 36... setting switch, 38... setting data input line, 40... F/F, 42... XO
R circuit, 44...setting data output line, 46...setting status indicator.
Claims (1)
有するＣＰＵを備えた装置と、各チヤンネル毎に
備えた対応する設定スイツチと出力ポートの端子
から入力信号を受け、入力ポートに設定信号を与
える複数のＸＯＲ回路と、各チヤンネル毎に備え
た対応するＸＯＲ回路から設定信号を受け、その
チヤンネルの設定状態を表示する複数の設定状態
表示器とから成ることを特徴とする多チヤンネル
観測装置。 A device equipped with a CPU having an input port and an output port for displaying the setting status, and a plurality of XORs that receive input signals from the terminals of the corresponding setting switch and output port provided for each channel and provide setting signals to the input ports. A multi-channel observation device comprising a circuit and a plurality of setting status indicators that receive setting signals from corresponding XOR circuits provided for each channel and display the setting status of the channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6487487U JPH052818Y2 (en) | 1987-04-27 | 1987-04-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6487487U JPH052818Y2 (en) | 1987-04-27 | 1987-04-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63170712U true JPS63170712U (en) | 1988-11-07 |
| JPH052818Y2 JPH052818Y2 (en) | 1993-01-25 |
Family
ID=30901429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6487487U Expired - Lifetime JPH052818Y2 (en) | 1987-04-27 | 1987-04-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH052818Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3144802A1 (en) | 2015-09-16 | 2017-03-22 | Thomson Licensing | Method and device for synthesizing a sound |
-
1987
- 1987-04-27 JP JP6487487U patent/JPH052818Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH052818Y2 (en) | 1993-01-25 |
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