JPS63169792A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPS63169792A
JPS63169792A JP105887A JP105887A JPS63169792A JP S63169792 A JPS63169792 A JP S63169792A JP 105887 A JP105887 A JP 105887A JP 105887 A JP105887 A JP 105887A JP S63169792 A JPS63169792 A JP S63169792A
Authority
JP
Japan
Prior art keywords
printing
solder resist
resist
soldered
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP105887A
Other languages
Japanese (ja)
Inventor
博文 牧野
田村 俊夫
安田 誠之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP105887A priority Critical patent/JPS63169792A/en
Publication of JPS63169792A publication Critical patent/JPS63169792A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は印刷配線基板の製造方法に関し、特にソルダー
レジストの印刷不良を改善したものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a printed wiring board, and particularly to a method for improving printing defects of solder resist.

〔発明の概要〕[Summary of the invention]

本発明は非ハンダ付領域へのソルダーレジスト印刷方法
に関し、導体配線回路パターンを形成する導体層の厚み
による凹凸をなくすための第1の印刷工程と、非ハンダ
付領域を被うための第2の印刷工程とを含んだ印刷配線
基板の製法において、ソルダーレジストの第1の印刷工
程を導体配線回路パターン形成のために用いたエツチン
グレジストを残したままソルダーレジスト厚が導体厚と
ほぼ同等になるように行うことにより、第1及び第2の
印刷工程の制御条件を緩和し、非半田付部の露出防止及
び半田付部へのレジストのにじみ防止を完全にならしめ
るものである。
The present invention relates to a method of printing solder resist on non-soldered areas, and includes a first printing process for eliminating unevenness due to the thickness of a conductor layer forming a conductor wiring circuit pattern, and a second printing process for covering the non-soldered areas. In the manufacturing method of a printed circuit board including a printing process of the first solder resist, the thickness of the solder resist becomes almost equal to the thickness of the conductor while leaving the etching resist used for forming the conductor wiring circuit pattern in the first printing process of the solder resist. By doing so, the control conditions for the first and second printing steps are relaxed, and the exposure of the non-soldered portions and the bleeding of the resist into the soldered portions are completely prevented.

〔従来の技術〕[Conventional technology]

従来より例えばテレビジョン受像機、ラジオ受信機等の
電子機器には印刷配線基板が多用されている。この印刷
配線基板は、例えば、絶縁基板上に導体材料により配線
パターンを形成した後、いわゆるハンダブリッジ等を防
止するために、ランド(ハンダ付領域)を除く領域すな
わちランド間を接続するラインを含む非ハンダ付領域に
ソルダーレジストを塗付することによって製造される。
2. Description of the Related Art Conventionally, printed wiring boards have been widely used in electronic devices such as television receivers and radio receivers. This printed wiring board includes, for example, after forming a wiring pattern using a conductive material on an insulating substrate, an area other than the lands (soldering area), that is, a line connecting between the lands, in order to prevent so-called solder bridges. Manufactured by applying solder resist to non-soldered areas.

ソルダーレジストは一般にスクリーン印刷により塗付さ
れる。その際に、非ハンダ付領域にソルダーレジストを
1回だけ印刷する印刷方法(1回印刷法)にはソルダー
レジストの「ニジミ」 (ハンダ付領域への印刷滲み)
「エツジ入らず」 (非ハンダ付領域の露出)の問題が
あった。そこで、この問題を解決するために、基板上の
非ハンダ付領域を完全に被覆するようにかつ導体層の厚
み以上の厚みをもって第1のソルダーレジスト印刷を行
った後、導体層上を研摩し、ハンダ付領域内外の領域に
第2のソルダーレジスト印刷を行う2回印刷法(2回印
刷法A)が提案されている。
Solder resist is generally applied by screen printing. At that time, the printing method that prints solder resist only once on the non-soldered area (single printing method) may cause "bleeding" of the solder resist (print bleeding on the soldered area).
There was a problem with ``no edges'' (exposure of non-soldered areas). Therefore, in order to solve this problem, the first solder resist is printed to completely cover the non-soldered area on the board and to a thickness that is greater than the thickness of the conductor layer, and then the conductor layer is polished. , a two-time printing method (two-time printing method A) has been proposed in which a second solder resist is printed on areas inside and outside the soldering area.

さらに、1回印刷法における「ニジミ」及び「エツジ入
らず」の問題を解決しつつ、チップ部品実装時の半田未
着の問題を解決するために、配線回路パターンとは逆の
パターンを有するマスクを用いて基板上に第1のソルダ
ーレジスト印刷を行なった後、導体層の表面を研摩し、
次いで導体層のうちのハンダ付領域を除いた部分に対応
したパターンを用いて導体層上に第2のソルダーレジス
ト印刷を行なうこと(2回印刷法B)が提案されている
Furthermore, in order to solve the problems of "bleeding" and "no edges" in the one-time printing method, and also to solve the problem of non-solder adhesion during chip component mounting, we created a mask with a pattern opposite to the wiring circuit pattern. After printing the first solder resist on the board using
It has been proposed that a second solder resist is then printed on the conductor layer using a pattern corresponding to the portion of the conductor layer excluding the soldering area (two-time printing method B).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、従来の技術によればソルダーレジスト印
刷条件の適正範囲が狭く制御困難なため、製造上「ニジ
ミ」 「エツジ入らず」などの印刷不良を防ぐことは容
易でなかった。
However, according to the conventional technology, the appropriate range of solder resist printing conditions is narrow and difficult to control, so it is not easy to prevent printing defects such as "bleeding" and "missing edges" during manufacturing.

例えば2回印刷法への第1の印刷において導体間の凹部
に十分なソルダーレジストを充填するためにはスクリー
ン印刷機のスキージ印圧を十分にかける必要があるが、
通常のソルダーレジスト印刷では半田付部への「ニジミ
」が出るため十分な印圧がかけられなかった。あるいは
スキージ印圧を高くした場合には機械的研磨に際してハ
ンダ付領域(ランド)の表面の仕上げに細心の注意が必
要であった。
For example, in the first printing of the two-time printing method, it is necessary to apply sufficient squeegee printing pressure of the screen printer in order to fill the recesses between the conductors with sufficient solder resist.
With normal solder resist printing, sufficient printing pressure could not be applied because "bleeding" appeared on the soldered areas. Alternatively, when the squeegee printing pressure is increased, careful attention must be paid to the surface finish of the soldered area (land) during mechanical polishing.

例えば2回印刷法Bの第2の印刷において平坦度不足の
ため「ニジミ」を防止出来るスキージ印圧ではレジスト
塗膜を厚く出来ないため、「エツジ入らす」を防止出来
る印刷条件を注意深く設定し監視しなければならなかっ
た。
For example, in the second printing of two-time printing method B, the resist coating cannot be thickened using the squeegee printing pressure that can prevent "bleeding" due to insufficient flatness, so printing conditions that can prevent "edges" must be carefully set. I had to keep an eye on it.

さらに、2回印刷法AまたはBいずれにおいても、第2
の印刷前に機械的研摩によって導体上のソルダーレジス
ト除去を必ず行なわなければならなかった。
Furthermore, in either the two-time printing method A or B, the second
Before printing, the solder resist on the conductor had to be removed by mechanical polishing.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に係る印刷配線基板の製造方法は、上述の問題点
を解決するために従来技術の2回印刷法AまたはBの第
1の印刷を、導体配線回路パターン形成のために用いた
エツチングレジストを残したままソルダーレジスト厚が
導体厚とほぼ同等になるように行なうことを特徴として
いる。
In order to solve the above-mentioned problems, the method for manufacturing a printed wiring board according to the present invention is characterized in that the first printing of the conventional two-time printing method A or B is performed using an etching resist that is used for forming a conductor wiring circuit pattern. The method is characterized in that the thickness of the solder resist is made almost equal to the thickness of the conductor while leaving .

〔作用〕[Effect]

本発明によれば、2回印刷法AまたはBの第1の印刷に
おいてハンダ付領域(ランド)にはエツチングレジスト
が残されていて、ソルダーレジストの滲みが起こらない
ためスキージ印圧を上げて配線間凹部に十分にソルダー
レジストを充填させることが出来る。第2の印刷におい
ては、非ハンダ付領域がほぼ平坦なため、レジスト厚み
方向の寸法及び形状の精度が増しスキージ印圧は通常よ
り低くてすみ、「ニジミ」の発生しない印圧で印刷する
ことが容易となる。さらに、ハンダ付領域へのソルダー
レジストの滲みが起こらないため、かつ非ハンダ付領域
がほぼ平坦なため、第2の印刷前に機械的研摩等によっ
て導体上のレジスト除去を行なうことが必要ではなくな
った。
According to the present invention, the etching resist is left in the soldering area (land) in the first printing of the two-time printing method A or B, and the squeegee printing pressure is increased to prevent the solder resist from bleeding. The solder resist can be sufficiently filled in the recessed portions. In the second printing, since the non-soldered area is almost flat, the precision of the dimension and shape in the resist thickness direction is increased, and the squeegee printing pressure can be lower than usual, making it possible to print with a printing pressure that does not cause "bleeding". becomes easier. Furthermore, since the solder resist does not bleed into the soldered areas and the non-soldered areas are nearly flat, it is no longer necessary to remove the resist on the conductors by mechanical polishing or the like before the second printing. Ta.

〔実施例〕〔Example〕

本発明に係る印刷配線基板の製造方法の一実施例につい
て工程順に説明する。
An embodiment of the method for manufacturing a printed wiring board according to the present invention will be described in order of steps.

第1図に示すように絶縁基板5上にランド(ハンダ付領
域)2、ライン3.4などの導体配線回路パターンを形
成するために用いたエツチングレジスト1を残したまま
の状態で保持する。
As shown in FIG. 1, the etching resist 1 used to form conductor wiring circuit patterns such as lands (soldering areas) 2 and lines 3.4 is left on the insulating substrate 5.

次に第2図に示すように第1のソルダーレジスト印刷に
より、パターン間隙(配線間凹部)にソルダーレジスト
6を導体厚とほぼ同じ厚みが得られるように充填する。
Next, as shown in FIG. 2, a first solder resist printing is performed to fill the pattern gaps (inter-wiring recesses) with solder resist 6 to a thickness that is approximately the same as the conductor thickness.

従来技術におけるソルダーレジスト印刷では半田付部へ
の印刷滲みが出るため、レジスト膜厚を導体厚とほぼ同
等にするために十分なスキージ印圧を与えることは困難
であったが、本発明ではエツチングレジスト1を残して
いるため「ニジミ」の心配な(十分にスキージ印圧を上
げることが出来る。本実施例でソルダーレジストとして
USR−2G(タムラ化研製、UV硬化型)、S−22
2(太陽インキ製、熱硬化型)等を使用し、柔らかいス
キージと目の粗いスクリーンを使用して従来の4〜5倍
のスキージ印圧をかけた。
In conventional solder resist printing, printing bleeds into the soldered area, making it difficult to apply sufficient squeegee printing pressure to make the resist film thickness approximately equal to the conductor thickness.However, in the present invention, etching Because resist 1 remains, there is no need to worry about "bleeding" (the squeegee printing pressure can be increased sufficiently. In this example, the solder resists used were USR-2G (manufactured by Tamura Kaken, UV curing type) and S-22.
2 (manufactured by Taiyo Ink, thermosetting type), etc., and a soft squeegee and a coarse screen were used to apply a squeegee printing pressure of 4 to 5 times the conventional pressure.

次に第3図に示すように、エツチングレジスト1の剥離
を行なう。
Next, as shown in FIG. 3, the etching resist 1 is removed.

エツチングレジスト1としてはドライフィルムではPH
T−865−AFT (日立化成製、アルカリ現像型)
、PHT−142F (日立化成製、溶剤現像型)、イ
ンキではER−33−2(ソマール製、UV硬化型)、
DA−380B (サンフ化学製、熱硬化型)等いずれ
も使用可能であり、剥離は使用するエツチングレジスト
に適合した剥離剤を用いて行なう。必要があれば、剥離
前に整面によりエツチングレジストl上ににじんだ第1
ソルダーレジストの除去を行なってもよい。なお、整面
ばスキージ様の治具でこするか回転ベルト式等の機械的
研磨等により行うことが可能である。
As etching resist 1, dry film has a pH of
T-865-AFT (manufactured by Hitachi Chemical, alkaline development type)
, PHT-142F (manufactured by Hitachi Chemical, solvent development type), ER-33-2 (manufactured by Somar, UV curing type),
DA-380B (manufactured by Sunf Chemical Co., Ltd., thermosetting type) and the like can be used, and peeling is performed using a stripping agent compatible with the etching resist used. If necessary, remove the first layer that has smeared onto the etching resist l by surface preparation before peeling.
The solder resist may also be removed. Note that the surface can be leveled by rubbing with a squeegee-like jig or by mechanical polishing using a rotating belt type or the like.

次に第4図に示すように、第2のソルダーレジスト印刷
を、ソルダーレジスト7が基板上のハンダ付領域に掛か
らないようにかつ少くとも上記導体配線回路パターンの
非ハンダ付領域に含まれる領域を完全に被うように行な
う。なお、はぼ平坦な面に印刷するため、レジスト厚み
方向の寸法及び形状の精度が増し、ハンダ付領域へソル
ダーレジスト厚が滲まないスキージ印圧で第2のソルダ
ーレジスト印刷を行なうことは容易であるが、例えば特
開昭57−113298のようにハンダ付領域をカバー
インキで被いソルダーレジストの印刷及び硬化後にとり
のぞくようなことをしてもよい。
Next, as shown in FIG. 4, a second solder resist is printed so that the solder resist 7 does not cover the soldered area on the board and is included in at least the non-soldered area of the conductor wiring circuit pattern. Cover completely. Furthermore, since printing is performed on a substantially flat surface, the accuracy of the dimension and shape in the resist thickness direction is increased, and it is easy to perform the second solder resist printing with a squeegee printing pressure that does not cause the solder resist thickness to bleed into the soldering area. However, it is also possible to cover the soldering area with cover ink and remove it after printing and curing the solder resist, as disclosed in Japanese Patent Application Laid-Open No. 57-113298.

本実施例では第3図に関し、第2図エツチングレジスト
1の除去を容易にするため第2図第1ソルダーレジスト
印刷を上記導体配線回路パターンとは逆のパターンを有
するマスクを用いて行なったが、非ハンダ付領域全面に
ソルダーレジスト印刷を行なった後、上記同様の方法に
よる整面によりエツチングレジスト1上のソルダーレジ
ストを除去し、その後にエツチングレジスト1の剥離を
行なうことも可能である。かかる場合にも、従来技術の
2回印刷法における第1のソルダーレジスト印刷とはソ
ルダーレジスト1を残している点で根本的に異なる。
In this example, regarding FIG. 3, in order to facilitate the removal of the etching resist 1 shown in FIG. 2, the solder resist 1 shown in FIG. It is also possible to print the solder resist on the entire non-soldered area, remove the solder resist on the etching resist 1 by smoothing the surface using the same method as described above, and then peel off the etching resist 1. Even in this case, it is fundamentally different from the first solder resist printing in the conventional two-time printing method in that the solder resist 1 remains.

上記の実施例では本発明に係る工程のみについて述べた
が、本発明による印刷配線基板は片面基板、両面基板、
多層基板のいずれも実施可能であり、導体配線回路パタ
ーンのうち、スルーホールの製法については第1図の導
体配線回路パターンエツチング以前に形成してしまう方
法であれば、テンティング法、孔埋め法、その他一般に
知られた方法は全て実施可能である。
In the above embodiments, only the steps related to the present invention were described, but the printed wiring board according to the present invention can be a single-sided board, a double-sided board,
Any of the multilayer boards can be used, and the method for manufacturing through-holes in the conductor wiring circuit pattern may be the tenting method or the hole filling method if the method is to form them before the conductor wiring circuit pattern etching shown in Figure 1. , and other generally known methods can all be implemented.

〔発明の効果〕〔Effect of the invention〕

上述した実施例の説明から明らかなように配線回路パタ
ーンの形成後に、エツチングレジストを残したままで、
ソルダーレジスト厚と導体厚とがほぼ等しくなることを
重視した第1のソルダーレジスト印刷を行い、これによ
り表面をほぼ平滑化し、最後に仕上のみを重視した第2
のソルダーレジスト印刷を行うことにより、非ハンダ付
領域の露出、ハンダ付領域への印刷滲みといった不良の
ない印刷が出来る。従って、半田未着等のハンダ付不良
を無くし、ハンダ付の信顧性を大幅に向上させることが
出来た。さらに、従来技術の2回印刷法に比べると、第
2のソルダーレジスト前に導体上のソルダーレジストを
機械的研摩により取り除く工程が必要で無くなり、工程
短縮によるコストダウンも実現出来た。
As is clear from the description of the above-mentioned embodiments, after the wiring circuit pattern is formed, the etching resist remains.
The first solder resist printing is done with emphasis on making the solder resist thickness and the conductor thickness almost equal, this makes the surface almost smooth, and finally the second solder resist printing is done with emphasis on finishing only.
By performing solder resist printing, it is possible to print without defects such as exposure of non-soldered areas and printing blur in soldered areas. Therefore, it was possible to eliminate soldering defects such as unattached solder, and to greatly improve the reliability of soldering. Furthermore, compared to the two-time printing method of the prior art, there is no need for a step of removing the solder resist on the conductor by mechanical polishing before applying the second solder resist, and cost reduction can also be achieved by shortening the process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第4図は本発明に係る印刷配線基板の製造方法
の一実施例を工程順に示す各概略断面図である。 第5図は従来の印刷配線の一例を示す概略斜視図(a)
及び断面図(b)である。 1、エツチングレジスト 5、絶縁基板 6、第1ソルダーレジスト 7、第2ソルダーレジスト 8、非ハンダ付部の露出 9、ニジミ(ランドへのソルダーレジストの印刷滲み) 10、ソルダーレジスト 特許出願人   ソニー株式会社 エッチンクパ 第1 図 第1ツルクーレジ゛Xト印刷 第2図 / エツチングレジスト 2 ランド(ハ〉り゛ン寸/丙1、せ戸)3 ライン 4 ライン 5 絶岳ゑ基析、 6  第1ゾルダニレジスト エ・/モ←ングレジレζト子り離 第3図 第2ソ2レターレジ又ト印塑] 第4図 / エーンチングレジ×ト 2 ランド()\ンダ付柑υへ) 3 ライン 4 ライン 5 絶間1−更 6 第1ソルダニレジスト 7 第2ソルクニしジズト
FIGS. 1 to 4 are schematic cross-sectional views showing one embodiment of the method for manufacturing a printed wiring board according to the present invention in the order of steps. Figure 5 is a schematic perspective view (a) showing an example of conventional printed wiring.
and a cross-sectional view (b). 1. Etching resist 5, insulating substrate 6, first solder resist 7, second solder resist 8, exposure of non-soldered parts 9, bleeding (printing of solder resist on land) 10. Solder resist patent applicant Sony Corporation Company etching resist No. 1 Figure 1 Tsuruco resist Registration/Mo←Registration ζ Toko Separation Fig. 3 2nd So 2 Letter Registration Matrice] Fig. 4/ Enching Registration Zetsukan 1-Kara 6 1st solder resist 7 2nd solder resist

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上に導体配線回路パターンの形成された印刷配
線基板の製造方法において、配線回路パターン形成時に
用いたエッチングレジストを残したまま、基板上の非ハ
ンダ付領域の少なくとも導体間凹部を完全に被うように
かつ厚みが導体厚とほぼ等しくなるように第1のソルダ
ーレジスト印刷を行い、しかる後に、基板上のハンダ付
領域に掛からないようにかつ少なくとも上記導体配線回
路パターンの上記非ハンダ付領域に含まれる領域を完全
に被うように第2のソルダーレジスト印刷を行うことを
特徴とする印刷配線基板の製造方法。
In a method for manufacturing a printed wiring board in which a conductor wiring circuit pattern is formed on an insulating substrate, at least the recesses between the conductors in the non-soldered area on the board are completely covered while leaving the etching resist used when forming the wiring circuit pattern. The first solder resist is printed so as to have a thickness almost equal to that of the conductor, and then printed so that it does not cover the soldered area on the board and at least covers the non-soldered area of the conductor wiring circuit pattern. A method for manufacturing a printed wiring board, comprising printing a second solder resist so as to completely cover an area included in the printed wiring board.
JP105887A 1987-01-08 1987-01-08 Manufacture of printed wiring board Pending JPS63169792A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP105887A JPS63169792A (en) 1987-01-08 1987-01-08 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP105887A JPS63169792A (en) 1987-01-08 1987-01-08 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPS63169792A true JPS63169792A (en) 1988-07-13

Family

ID=11490938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP105887A Pending JPS63169792A (en) 1987-01-08 1987-01-08 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPS63169792A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267829A (en) * 1992-03-23 1993-10-15 Nec Corp Printed wiring board and manufacture thereof
JPH06338677A (en) * 1993-05-31 1994-12-06 Nec Corp Manufacture of printed wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267829A (en) * 1992-03-23 1993-10-15 Nec Corp Printed wiring board and manufacture thereof
JPH06338677A (en) * 1993-05-31 1994-12-06 Nec Corp Manufacture of printed wiring board

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