JPS63167944A - Data transfer control method - Google Patents

Abstract

PURPOSE:To suppress a drop of the transfer efficiency by transferring a data from the head of the data to a transfer section data positioned in the end of a block boundary, and inhibiting the storage to a buffer memory of the data which is read out previously, when the subsequent data transfer is aborted. CONSTITUTION:An operation control unit 3 sends out a block boundary block read request for instructing an abortion of a data transfer in a block boundary, to a memory control unit 2. Its contents are transmitted to a request processing circuit 21, and the circuit 21 reads out a necessary data by referring to a buffer memory 20 by a received memory address, and continuously, a block data is read out successively. In this case, the circuit 21 reads out extending from the head of the necessary data to a transfer section data in the end of a block boundary, in accordance with an instruction of a received request designating part, inhibits read-out of the subsequent transfer section data, and also, inhibits a fact that a block data containing this unnecessary data is written onto the buffer memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer control system between an arithmetic control unit and a main memory device.

〔overview〕

The present invention provides a method in which an arithmetic and control unit obtains required data all at once from a main memory device in response to a block read request. By transmitting the transfer section data up to the end of the boundary to the arithmetic control unit and discontinuing the transfer of the remaining transfer section data, the reduction in data transfer efficiency caused by transferring unnecessary data to the arithmetic control unit is suppressed. It has been made possible to do so.

[Conventional technology]

In large-scale information processing systems, high-speed data processing is required in both the fields of business processing calculations and scientific and technical calculations, and a high-speed buffer memory that stores a copy of a portion of the data in the main memory is installed in the memory control unit. It is provided.

To obtain the data required by the arithmetic control unit, the buffer memory in the memory control unit is first indexed, and if the required data exists, it is transferred from the buffer memory to the arithmetic control unit, and if it does not exist, it is transferred to the main memory device. A block data transfer request is made to the memory control device, and the block data starting with the required data is transferred to the memory control device in several parts. Within the memory control device, this block data is written into a buffer memory, and the required data at the beginning is directly transferred to the arithmetic control device.

Here, in order to obtain the data required by the arithmetic and control unit all at once, a block data transfer request is made to the memory control unit (hereinafter, a block data transfer request made by the arithmetic and control unit to the memory control unit is called a block read request). ) may be carried out. In this case, in the conventional data transfer control method, when the required data exists on the buffer memory in the memory control device, the required block data on the buffer memory is divided into multiple sections, and the transfer section at the accessed address is All required block data is transferred to the arithmetic and control unit in several batches, starting with the data. If the block data does not exist, a block data transfer request is made to the main memory device, the required block data read from the main memory device is divided into multiple sections, and the transfer section data at the accessed address is the first section. Transfer to memory controller. Inside the memory control unit, this block data is written to the buffer memory, and all of the required block transfer data is transferred directly to the arithmetic control unit in several batches, starting with the transfer classification data at the accessed address. was under control.

[Problem that the invention seeks to solve]

By the way, array calculation processing is an example of frequent block read requests for the purpose of obtaining data required by the calculation control device all at once. In the field of scientific and technical computing, it is desired to perform the same processing at high speed on large amounts of array data regularly arranged in memory, and it is necessary to transfer data at high speed to the arithmetic unit in the arithmetic control unit. The arithmetic and control unit reads the required data all at once in response to a block read request.

In this case, in the conventional data transfer control method described above,
All block data will be transferred starting with the transfer classification data on the accessed address. For example l
When the block data is 64 bytes, as shown in Figure 3, the 64 bytes of block data are divided into data lengths (8 bytes in this case) determined by the data transfer width between the arithmetic control unit and the memory control unit. The block data is divided into 8 times and all transferred to the arithmetic and control unit. Here, the 64-byte block data from the beginning of the block boundary to the end of the block boundary are word numbers O to 7, and the array data required by the arithmetic control unit is continuous from the address position of word number 3 in the direction of increasing addresses. If the arithmetic and control unit wants to obtain the required array data all at once through a block read request, the memory control unit must send a block read request at the address corresponding to array data 0. In the conventional data transfer control method, word number 3 of array data O is sent to the arithmetic control unit, regardless of whether or not this array data 0 exists on the buffer memory in the memory control unit. All block data of word numbers 4 to 7 and word numbers 0 to 2 are successively transferred starting with the transfer classification data of .

At this time, the transfer classification data with word numbers 0 to 2 is unnecessary data that is not needed by the arithmetic control unit, and the data transfer rate that occurs when transferring the data of word numbers O to 2 of this unnecessary data to the arithmetic control unit. There are drawbacks, such as a decrease in performance and the process of separating necessary data from unnecessary data within the arithmetic and control unit.

Furthermore, if the required data does not exist on the buffer memory in the memory control device and the required block data is read from the main memory device, this read block data is written onto the buffer memory in the memory control device. Therefore, while this block data is being written onto the buffer memory, processing of a new request sent from the arithmetic control unit is made to wait within the memory control unit. That is, writing block data containing unnecessary data onto the buffer memory has the disadvantage that processing of new requests is delayed and buffer memory usage efficiency is reduced.

The present invention aims to eliminate such drawbacks and provides a data transfer control method that can inhibit unnecessary data from being transferred to an arithmetic control unit and improve data transfer efficiency.

[Means for solving problems]

The present invention transfers block data held in this buffer memory to a calculation control unit that has issued a block transfer request via a buffer memory that holds a part of data stored in a main memory device in block units. In a data transfer control method that sequentially transfers data of multiple sections starting with the requested section among the sections divided into sections, when the data related to the block transfer request is on the buffer memory, it is stored in this buffer memory. Transfers the data from the requested section to the last section of the block boundary to the arithmetic control means among the plurality of sections that have been requested, and when the data requested by the block transfer request is not on the buffer memory, The data related to the block transfer request is read from the main memory device, storage of the read data in the buffer memory is prohibited, and the read data is divided into sections from the request section to the last section of the block boundary. It is characterized in that it is transferred to the arithmetic control means.

[Effect]

When the data required by the arithmetic control unit is placed continuously from the middle of the block boundary and the required data is obtained all at once, transfer of data from the beginning of the required data to the end of the block boundary. to prevent further data transfer.

Further, when required data is not present on the buffer memory in the memory control device and required block data is read from the main memory device, writing of block data containing this unnecessary data to the buffer memory is prohibited.

〔Example〕 Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block configuration diagram showing the configuration of an embodiment system of the present invention. FIG. 2 is a conceptual diagram showing memory data formats of various memories in the embodiment system of the present invention. In FIG. 2, young addresses are located on the left, and word numbers O to 7 indicate word identification for every 8 bytes. A 64-byte boundary indicates an address position where the address is evenly divisible by 64.

First, the configuration of this embodiment system will be explained based on FIG. This embodiment system includes a main memory device 1, a memory control device 2, and an arithmetic control device 3. Here, the main memory device 1 includes a memory section 10 that stores instruction words, operand data, etc., an address register 11 that holds an address for accessing the memory section 10 sent from the memory control device 2, and a memory section 10 that stores instructions and operand data. a data register 12 that holds read data; and a data register 12
and a data selection circuit 13 that selects the order in which the data read out to the memory control device 2 is sent.
The memory control device 2 also includes a buffer memory 20 that holds part of the data read from the memory unit 10 in the main memory device 1, and a request processing unit that processes various requests instructed by the arithmetic control device 3. A circuit 21;
A data register 22 that holds data sent from the main memory device 1, a data selection circuit 23 that selects the first half data and the second half data of the data register 22, and data read from the buffer memory 20 and data selection. A data selection circuit 24 that selects the data selected by the circuit 23, a request specifying section that specifies the memory address of the data sent from the arithmetic control device 3 and required by the arithmetic control device 3, and the content of the request. It is equipped with a request address receiving register 25 and a request specifying part receiving register 26 which are held respectively, and also has a request address receiving register 25 and a request specifying part receiving register 26.
has the same configuration as a known arithmetic and control device, and includes a device such as an input/output device that needs to read data from a main memory device. Also, an interface line 1 is connected between the main memory device 1, memory control device 2, and arithmetic control device 3.
00 to 104 are connected.

Next, the operation of this embodiment device will be explained based on FIGS. 1, 2, and 3.

First, the data width of the data transfer path 104 from the memory control device 2 to the arithmetic control device 3 is 8 bytes, and the data width of the data transfer path 101 from the main memory device 1 to the memory control device 2 is 16 bytes. 10 and buffer memory 20 are both 64 bytes in block size. That is, when transferring block data from the memory unit 10 and the buffer memory 20, one block of data is both 64-byte data from a 64-byte boundary. Further, the circuit elements of the main memory device R1 are slower than the circuit elements of the memory control device 2 and the arithmetic control device 3, and the machine cycle time thereof is set to be twice as fast. That is, from the perspective of the memory control device 2, data transfer from the main memory device 1 is at a rate of 16 bytes in 2 machine cycles.

Now, suppose that the arithmetic control unit 3 needs to fetch an instruction or an operand, and a memory request is sent to the memory control unit 2.

Here, a case will be described in which a normal block read request is sent for the purpose of obtaining block data including data required by the arithmetic and control device 3 all at once. The arithmetic control unit 3 sends the memory address of the required data and a request specifying section specifying a normal block read request to the memory control device 2, and the respective contents are stored in the request address receiving register 25 and the request specifying section receiving register 2.
6 respectively. Next, the request address receiving register 25 and the request specifying part receiving register 26
The contents of are transmitted to the request processing circuit 21.

The request processing circuit 21 receives the contents of the request specifying section specifying the memory address of the required data and a normal block read request, and first indexes the buffer memory 20 with the memory address of the required data. If the required data exists in the buffer memory 20, the required data is read out, and then the block data are sequentially read out. That is, the 64-byte block data is divided into 8 transfer section data of 8 bytes each, and the 8 transfer section data with the 8-byte required data at the beginning are sequentially read out and processed via the data selection circuit 24. Control device 3
sent to.

If the required data does not exist in the buffer memory 20,
The request processing circuit 21 sends a block data transfer request to the main memory device 1 along with the memory address of the required data. In the main memory device 1, the address of this required data is set in the address register 11, and the data is read from the memory section 10. 64-byte data including the required data from the 64-byte boundary is read from the memory unit 10 and set in the data register 12. The block data read into the data register 12 is sent to the memory control device 2 via the data selection circuit 13 in four parts every 16 bytes.

At this time, the data transfer order of the 64-byte block data to the memory control device 2 is, for example, if the memory address of the required data from the arithmetic control device 3 indicates the position corresponding to word number 3, word number 3 to 7.0～
Data transfer of 64 bytes is performed in the order of 2. That is,
The sending order starts with word numbers 3 and 4 of the required data.
The second word numbers are 5 and 6. The third word number is 7, and the 0.4th word numbers are 1 and 2. They are sequentially transmitted in groups of two words each.

Now, in the memory control device 2, each 16-byte data sent from the main memory device 1 is stored in a data register 22.
The first 8 bytes and the second 8 bytes are selected by the data selection circuit 23 in this order, and 64 bytes of data are directly sent to the arithmetic and control unit 3 via the data selection circuit 24 and written to the buffer memory 20. It will be done.

The above is the operation of a normal block read request, which is similar to the conventional data transfer control method.

Next, the characteristic operation of the data transfer control system of the present invention will be described. Here, it is assumed that the arithmetic and control unit 3 processes array data, and that the required array data is continuously arranged on the memory from the address position of word number 3 in the direction of increasing addresses as shown in FIG. The arithmetic control bag w3 sends a block read request to the memory control device 2 for the purpose of pre-fetching array data in order to perform high-speed processing of array data. In this case, if you send the above-mentioned normal block read request, in addition to the data of the required word numbers 3 to 7,
Since the unnecessary data up to 2 is transferred to the arithmetic and control device 3, the data transfer speed decreases due to the transfer of the unnecessary data, and processing for separating necessary data from unnecessary data occurs within the arithmetic and control device 3. Therefore, the arithmetic and control unit 3 sends a block read request (hereinafter referred to as block boundary block read request) instructing to terminate data transfer at the block boundary. That is, the arithmetic control unit 3 sends a memory address indicating array data 0 and a request specifying section specifying a block boundary block read request to the memory control device 2, and this memory address and request specifying section are sent to the request address receiving register 25 and the request specifying section. They are respectively set in the designated section receiving register 26.

The contents of the request address receiving register 25 and the request specifying section receiving register 26 are transmitted to the request processing circuit 21, and the request processing circuit 21 first indexes the buffer memory 20 using the received memory address. If the required data exists in the buffer memory 20, the required data is read out, and then the block data are sequentially read out. At this time, the request processing circuit 21 transfers the last transfer classification data of the block boundary starting from the required data of 8 bytes of the 64-byte block data according to the instruction of the request specifying section that specifies the received block boundary block read request. control is performed to prevent reading of subsequent transfer classification data. In this example, the transfer section data of word numbers 3 to 7 corresponding to array data O to 4 are read out, and the subsequent unnecessary data of transfer section data of word numbers O to 2 are not read out. . The transfer classification data of word numbers 3 to 7 read from the buffer memory 20, that is, the array data 0 to 4, are sent to the arithmetic and control unit 3 via the data selection circuit 24.

If the required data does not exist in the buffer memory 20,
The request processing circuit 21 sends a block data transfer request to the main memory device 1 along with the memory address of the required data. Thereafter, the reading of block data from the main memory device 1 and the sending to the memory control device 2 are performed in the same manner as in the case of the normal block read request described above. That is, the required 64-byte block data read from the memory unit 10 is first transferred to the memory control device 2 in the order of word numbers 3 to 7 and O to 2.

In the memory control device 2, each 16-byte data sent from the main memory device 1 is set in a data register 22, and the data selection circuit 23 selects the first 8 bytes and the latter 8 bytes in this order. Data transfer to the arithmetic and control unit 3 is performed by a request processing circuit according to instructions from a request specifying section that specifies a block boundary block read request;
Based on the control of 21, the last transfer segment data at the block boundary with the required data at the beginning of the 64-byte block data, that is, word numbers 3 to 7 (array data θ to
Only the transfer classification data up to 4) is sent to the arithmetic and control unit 3 via the data selection circuit 24, and the transfer of the subsequent transfer classification data of word numbers O to 2 is discontinued. Furthermore, writing of this block data to the buffer memory 20 is also inhibited by the control of the request processing circuit 21,
New requests sent from the arithmetic and control unit 3 are processed without being made to wait.

The above is the operation of the block boundary block read request which is a feature of the data transfer control system of the present invention, and only the array data O to 4 required by the arithmetic and control device 3 are sent to the arithmetic and control device 3.

〔Effect of the invention〕

As explained above, the present invention is useful when processing data in which data required by an arithmetic and control unit is arranged continuously from the middle of a block boundary, such as when processing array data. , in response to a block read request used by the arithmetic control unit to obtain the data it needs all at once, it transfers the data from the beginning of the required data to the end of the block boundary, and prevents the transfer of subsequent data. Since the means is added, it is possible to improve the decrease in data transfer efficiency that occurs when unnecessary data is transferred to the arithmetic control unit, and to reduce wasteful processing that occurs when separating necessary data from unnecessary data within the arithmetic control unit. It has the effect of making a reduction.

Furthermore, if the required data does not exist on the buffer memory in the memory control device and the required block data is read from the main memory device, writing the block data containing this unnecessary data onto the buffer memory is prohibited. , processing is performed without having to wait for a new request sent from the arithmetic and control unit, and the efficiency of buffer memory usage can also be improved.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment system of the present invention. FIG. 2 is a conceptual diagram showing the memory data format. FIG. 3 is an arrangement diagram of array data. 1... Main memory device, 2... Memory control device, 3.
...Arithmetic control unit, lO...Memory section, 11...Address register, 12.22...Data register, 1
3.23.24...Data selection circuit, 20...Buffer memory, 21...Request processing circuit, 25...
-Request address receiving register, 26...Request specification section receiving register.

Claims (1)

[Claims] (1) The block data held in this buffer memory is sent to the arithmetic and control unit that issued the block transfer request via a buffer memory that holds part of the data stored in the main memory device in blocks. In a data transfer control method that sequentially transfers data of multiple sections starting with the request section among the sections divided into sections, when the data related to the block transfer request is on the buffer memory, the data is stored in this buffer memory. The data starting from the requested segment and ending with the last segment at the block boundary is transferred to the arithmetic control means among the plurality of segments, and when the data requested by the block transfer request is not on the buffer memory, the data is transferred to the arithmetic control means. The data related to the block transfer request is read from the main memory device, storage of the read data in the buffer memory is prohibited, and the read data is divided into the sections starting from the request section and ending with the last section at the block boundary. A data transfer control method characterized by transferring data to an arithmetic control means.