JPS63167628A - Overcurrent-proof circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an overcurrent prevention circuit suitably used in a DC motor that drives a small printer used in, for example, an electronic cash register.

BACKGROUND OF THE INVENTION Small printers used in electronic cash registers typically use a direct current motor or the like as a drive device. In order to achieve miniaturization, the above-mentioned small printers often employ a mechanism in which a single motor performs operations such as paper feeding, print head movement, and ink ribbon feeding. In addition to simply driving the motor, it is necessary to quickly stop the motor during rotation at a predetermined timing.
A drive circuit that controls this drive and stop is realized by the configuration shown in FIG. 4, for example.

Referring to FIG. 4, a fifth transistor is connected to the bases of both the PNP type transistor TR2 and the NPN type transistor TRI.
When the H-level stop signal S shown in FIGS. 1 and 2 is applied, the transistor TR2 becomes disconnected and the transistor TRI becomes conductive. Therefore, the motor 15 has a power supply voltage of +V
Power line powered by CC! A motor drive current Id flows through the motor 15, thereby driving the motor 15.

On the other hand, when an L-level drive signal and a stop signal S are applied to the bases of transistors TRI and TR2, respectively, transistor TR2 becomes conductive, and transistor TR
I is in a cut-off state. As a result, the power line 12
A braking current Is flows as shown in FIG. 4, and the rotating motor 15 is thereby quickly stopped. Drive and stop of the motor 15 are controlled by such a drive circuit.

Problems to be Solved by the Invention However, if the motor 15 is overloaded due to, for example, a paper jam in a small printer, or if the transistor TR2 suffers a short-circuit failure, the drive circuit 14 is Short circuit current I flows as follows. This causes problems such as destruction of the non-faulty transistor TRI or abnormal heat generation of the power supply and motor 15. Furthermore, if the transistor TRI suffers from a short-circuit failure while the motor is stopped, the short-circuit current T will similarly flow, causing the problem α that the above-mentioned abnormal situation occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide an overcurrent prevention circuit that can solve the above-mentioned problems and advantageously protect a drive device, switching means, etc. from abnormal current.

Means for Solving the Problems The present invention provides: a drive device that is powered and driven; switching means provided in association with the drive device for activating/stopping the drive device; and a drive device with respect to the switching means. Abnormal current detection means, provided on the opposite side, detects abnormal current exceeding a certain level and derives a signal at one level during that period, and switching means when the output from the abnormal current detection means changes to the one level. This is an overcurrent prevention circuit characterized in that it includes a switching control means for cutting off the overcurrent.

Function: In the overcurrent prevention circuit according to the present invention, when an abnormal current exceeding a certain level flows through the switching means for driving/stopping the drive device, the abnormal current detection means detects this and detects whether the abnormal current is flowing. During this period, a signal at one level is output. The switching control means controls the switching means to cut off when the output from the abnormal current detection means changes to one level. When an abnormal current flows through the switching means in this manner, the switching means is cut off by the switching control means, so that the drive device can be protected from the undesired abnormal current.

Embodiment FIG. 1 is a diagram showing the electrical configuration of a motor drive circuit 2 including a protection circuit 1, which is an embodiment of the present invention. The motor drive circuit 2 includes a DC motor 3, which is a drive device for driving a small printer used in an electronic cash register, for example, an NPN transistor TRI, a PNP transistor TR2 and a protection circuit 1, and the like. 3
is the power line powered by the power supply voltage +Vcc! The emitter of the transistor TR2 is connected to the power supply line No. 1, the collector is connected to the collector of the transistor TRI via the connection point A, and the output of the motor 3 is connected to the connection point A. given to.

The emitter of the transistor TRI is grounded through the current detection layer resistor R8.The base of the transistor TR2 is connected to the power supply line through the resistor R1! 1 while the resistor R
2 and an inverter 4 to an output terminal of an AND circuit 5. The base of transistor TRI is resistor R3
Power line via J! 1, and is connected to the output terminal of a NAND circuit 7 via an inverter 6.

The above two inverters 4 and 6 are connected to an AND circuit 5 and a NA
The output of the ND circuit 7 is inverted and the two transistors TR
It is provided for converting to a voltage level for driving I and TR2.

A connection point B between the emitter of the transistor TRI and the current detection resistor R8 is connected to a non-inverting input terminal of a comparator 9 via an integrating circuit 8 consisting of a resistor R4 and a capacitor C1, and the inverting input terminal is connected to a reference voltage VO. is applied.

Note that the current detection resistor R3, the integrating circuit 8, and the comparator 9
An abnormal current detection section 11, which will be described later, is configured.

The output of the comparator 9 is, for example, an R-S type 7-lip 70.
It is applied to the set input terminal S of the latch circuit 10 realized by a knob or the like, and the output terminal Q of this latch circuit 10 is
The output from the AND circuit 5 and the NAND circuit 7 are given to one terminal of each. Also, these AN
The other terminals of the D circuit 5 and the NAND circuit 7 are supplied with a stop signal S and a drive signal, which will be described later, respectively, and the reset input terminal of the latch circuit 10 is supplied with a protection circuit reset signal R, which will be described later. The two inverters 4 and 6, the AND circuit 5, the NAND circuit 7, and the 1/-7 circuit 10 constitute a switching control means.

2 and 3 are timing charts for explaining the operation of the motor drive circuit 2. FIG. The operation of the motor drive circuit 2 when the motor 3 is driven will be described with reference to FIG. 151 and FIG. Note that the latch circuit 10 is normally in a reset state, and an H level signal is output from the output terminal Q to the AND circuit 5 and the NAND circuit 7.
is given to one terminal of each.

At R mark 10, the stop signal S becomes L level as shown in FIG. Output Q2 is shown in the same figure (7)
As shown in the figure, it becomes H level.

When the H level output Q2 is applied to the base of the PNP transistor TR2, this transistor T
R2 enters the cut-off state.

On the other hand, at time t1, when the drive signal becomes H level and is input to the other terminal of the NAND circuit 7 (see (1) in the figure), the NAND circuit 7 gives an L level signal to the inverter 6. As a result, the output Q1 of the inverter 6 becomes H level as shown in (8) of the same figure. In this way, when the H level output Q1 is given to the base of the N P N type) lannostar TRI, this transistor T
RI becomes conductive.

In this way, at time t1, the transistor T
R2 is in a cut-off state, and transistor TRI is in a conductive state. Therefore, the power line J! 1, a motor drive current Icl flows through the motor 3 and the transistor TRI toward the connection point B, thereby driving the motor 3. The reason why the levels of the stop signal S and the upstream drive signal are not changed at the same time is as follows. That is, for example, at time to, if the drive signal is set to H level, both transistors TRI and TR2 become conductive, thereby causing the power supply line! 1 will be grounded and short-circuited. Therefore, when driving the motor 3, in order to prevent the above-mentioned short-circuit, the switching of the level of the drive signal is given a slight delay from the switching of the level of the stop signal S. , try to do this. Further, as will be described later, the same operation is performed when the motor 3 is stopped and released.

Next, the operation of stopping the motor 3 will be described with reference to FIGS. 1 and 3. Note that in this case as well, the latch circuit 10 is in a reset state, and an H level signal is output from the output terminal Q.

Referring to FIG. 3, at time L6, the figure (1
) As shown in the figure, the drive signal D fJt becomes L level,
This is input to the other terminal of the NAND circuit 7.

As a result, the NAND circuit 7 provides an H level output to the inverter 6, and the output Q1 of the inverter 6 becomes L level (see (8) in the figure). This L level output Q
When 1 is applied to the base of a PNP transistor TR1, this transistor TR1 is turned off.

At time t7, the stop signal S becomes H level as shown in FIG. This causes inverter 4 to
The output Q2 of the transistor becomes L level (see (7) in the figure). When this L level output Q2 is applied to the base of the transistor TR2, the transistor TR2 becomes conductive.

In this way, at time t7, the transistor T
RI is in a cut-off state, and transistor TR2 is in a conductive state. Therefore, the power line J! 1 and connection point A are short-circuited, thereby causing a braking current Is to flow through the motor 3 and stopping the motor 3.

In this manner, when the latch circuit 10 is in the reset state, when the H level drive signal rises and the L level stop signal S is applied to the other terminals of the AND circuit 5 and the NAND circuit 7, the motor 3 is driven. On the other hand, when the H level stop signal S is applied to the AND circuit 5 and the NAND circuit 7 from the L level drive signal, the motor 3 is stopped.

Next, the operation of the protection circuit 1 will be explained with reference to the tIS2 diagram.At time t1, as described above, the transistor TR2 is in the cut-off state, and the transistor TR
I becomes conductive, and the motor 3 is driven. At this time, since the motor 3 is driven from a stopped state, the load is large, and the potential at the connection point B suddenly increases as shown in Figure 2 (3), forming a peak portion P1. However, once the motor 3 starts to drive, the load becomes smaller, so the potential becomes stable.

A peak portion P1 of the voltage at the connection point B when the motor 3 is started is smoothed by the integrating circuit 8 and provided to the comparator 9. Note that in the integrating circuit 8, the reference voltage vO applied to the inverting input terminal of the comparator 9 is set to a level higher than the level output from the integrating circuit 8 due to the peak gP1. Therefore, depending on the peak portion P1 when the motor 3 is started, nothing is output from the comparator 9.

For example, at time t2, the rotating motor 3
If an abnormal current flows due to an overload on the transistor TR2 or a short circuit failure in the transistor TR2,
The potential at the connection point B begins to rise rapidly as shown in Figure 2 (3), and a peak portion P2 is formed. When the output of the integrating circuit 8 exceeds the reference voltage vO at time t3 (see (4) in the same figure) due to the second voltage, the comparator 9 gives an output of a certain level to the set input terminal of the circuit 10. .

The latch circuit 10 is brought into a set state by the output from the comparator 9. As a result, the output from the output terminal Q becomes L level, and this becomes the AND circuit 5 and the NAND circuit 7.
are given to one terminal of each.

Therefore, in the AND circuit 5, an L level output is always given to the inverter 4 regardless of the signal level of the stop signal S. As a result, the transistor TR2 is also always cut off. On the other hand, regardless of the signal level of the drive signal in the NAND circuit 7, the inverter 6 is
level output is given, which causes the transistor T
RI is always cut off. When the latch circuit 10 is in the set state in this way, regardless of the signal level of the stop signal S and the rising drive signal, the two transistors TRI
, TR2 are both cut off.

In this way, at time L3, transistor TR1,
When both TR2 are cut off, the potential of the connection αB becomes O level immediately. It should be noted that the output of the comparator 9 does not immediately reach the θ level, but falls below the reference voltage ■O at time t4, for example, and then the potential gradually decreases. Therefore, the output of comparator 9 is when 'XIJ t
After 4, the level becomes 0 (see (5) in the same figure).
The latch circuit 10 enters the set state by catching the rising edge of the output from the comparator 9, and thereafter remains in the set state unless the reset signal R is input to the reset input terminal.

Next, with reference to FIG. 3, the operation of the protection circuit 1 while the motor 3 is stopped will be described.

At time t7, as described above, the transistor TRI is in the cut-off state and the transistor TR2 is in the conductive state, so the motor 3 is stopped.

Therefore, the potential at connection point B is as shown in PIS3 diagram (3)
As shown in the figure, it becomes the θ level.

So, for example, at time 8, the transistor T
When an abnormal current flows due to a short-circuit failure of the RI, the potential at the connection point B begins to rise rapidly, and a peak portion P3 is formed. As a result, for example, time t9
When the output from the integrating circuit 8 exceeds the reference voltage VO as shown in FIG.
is set. As a result, as described above, both transistors TRI and TR2 are turned off, and the potential at the connection point B immediately becomes O level. Further, the output from the integrating circuit 8 does not immediately go to the 0 level as described above, but falls below the reference voltage VO at time L10, and then gradually decreases.

In this way, if a short-circuit failure occurs between the emitter and collector of either transistor TR1 or TR2 due to an accident or an overload on the motor 3, and an abnormal current flows, the abnormal current detection unit 11, the occurrence of an abnormal current is detected and the latch circuit 10 is set. This allows the two transistors TR1
, TR2 are both cut off, and the two transistors T
R1 and TR2 can be protected from the above abnormal current.

Note that in order to bring the latch circuit 10 in the set state into the reset state, the reset signal R may be manually inputted to the reset input terminal R of the latch circuit 10, for example, or each of the transistors T R1 and T2 may be input manually. These transistors TRI, A reset signal may be given to the latch circuit when it is detected that no abnormal current flows through both of TR2. In addition, the above detection circuit has an emitter
The voltage level between the collectors may be detected. In this way, when it is detected that the transistors TRI and TR2 are normally operated, the latch circuit 10 can be automatically reset. Furthermore, when the motor 3 is overloaded, if the reset circuit 10 is set, the original state can be restored by removing, for example, a paper jam that is causing the overload. can.

In this way, according to this embodiment, it is possible to prevent the transistors TRI, TR2, the motor 3, etc. from being destroyed due to the occurrence of abnormal current.

Effects As described above, in the overcurrent prevention circuit according to the present invention,
That drive 9! When an abnormal current occurs in the switching means provided in connection with the II device, the switching means controls to cut off the abnormal current, so that the abnormal current is removed. In this way, for example, even if an overload on the drive device or a short-circuit failure in the switching device occurs, the current flowing through these devices can be cut off to the extent that the drive device or the switching device is not damaged. . The level of this abnormal current can be set to a desired level by suitably selecting a constant level value set in the abnormal current detection means. This makes it possible to advantageously protect the drive, the switching means, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the electrical configuration of a motor drive circuit 2 which is an embodiment of the present invention, and FIG. 2 is a timing chart illustrating the operation of the motor drive circuit 2 while the motor 3 is being driven. FIG. 3 is a timing chart for explaining the operation of the motor drive circuit 2 while the motor 3 is stopped, and FIG. 4 is a typical prior art motor drive circuit 14.
FIG. 5 is a waveform diagram of the stop signal S and drive signal applied to the motor drive circuit 14, and FIG. 6 is a diagram for explaining the operation of the motor drive circuit 14. 1... Protection circuit, 2... Motor drive circuit, 3...
Motor, 4, 6... Inverter, 5... AND circuit, 7... NAND circuit, 8... Integrating circuit, 9...
Comparator, 10... Latch circuit, 11... Abnormal current detection section, TRI. TR2...transuster, RS...resistance agent for current detection Patent attorney Number of strokes Keiichi 1 s Fig. 2 113 Fig. 4

Claims (1)

[Scope of Claims] A drive device driven by electric power; switching means provided in association with the drive device for driving/stopping the drive device; provided on the opposite side of the drive device with respect to the switching means; abnormal current detection means for detecting an abnormal current exceeding a certain level and deriving a signal at one level during that period; and switching control means for cutting off the switching means when the output from the abnormal current detection means changes to the one level. An overcurrent prevention circuit comprising: