JPS63167588A - Cryptographic information transmission system - Google Patents

Abstract

PURPOSE:To enhance the security against interception by using a converted data being the logical conversion of a transmission initial value data by means of a key data at an encoder side so as to apply actual scrambling to the transmitted information. CONSTITUTION:A transmission data processing means 11 inputs a source video signal 10 to apply scrambling. An initial value converting means 16 latches the initial value data generated precedingly in the timing when the new initial value data is generated from an initial value generating means 15, the latched output is subject to prescribed logical conversion and a source video signal inputted to a transmission data processing means 11 is scrambled in the timing of a random number signal 16a based on the converted data. The scramble video signal 19 from a transmission line 13 is fed to a reception data processing means 20, a data extraction means 21 and a transmission number count means 22. The initial value conversion means 23 outputs the same random signal 23a as that of the encoder side and the reception data processing means 20 outputs a descramble video signal.

Description

[Detailed Description of the Invention] [Objective of the Invention 9] (Industrial Application Field) This invention provides a subscriber broadcasting system using unidirectional communication, in which even if the key information for decoding the scramble added to the pay broadcasting signal is known, To provide an encrypted information transmission system capable of suppressing descrambling malfunctions to a minimum period even when the key information cannot be immediately descrambled and a synchronization signal cannot be normally separated due to noise in a transmission system.

(Prior Art) In subscriber broadcasting systems such as CATV systems, the broadcasting station charges for specific programs and scrambles the transmitted signal, so that subscribers other than those who have signed a contract with the broadcasting station Prevent eavesdropping by subscribers. Therefore, security against eavesdropping is provided by advanced scrambling (
The more encryption is performed, the more expensive it becomes, but on the other hand, there is a trade-off in that the exact timing of descrambling (plaintext) by a contract subscriber becomes 1 [i].

There are various methods of scrambling, but for example, in the case of video signals, synchronization compression is often performed in which AM-like modulation is applied to the synchronization signal at the baseband stage.

If synchronous compression is performed regularly, the accuracy of descrambling can be obtained, but it has the disadvantage that it can easily be used for surreptitious viewing. For example, in a system that emphasizes security, an M-sequence pseudo-random pulse generator (such as a PN signal) is used.
Usually, a random number generator (random number generator) is used to generate random timing. For example, in the case of a video signal, key data (random number initial value) for unscrambling is multiplexed in a predetermined horizontal scanning period in the vertical blanking period. - However, even if the paid broadcasting signal is concealed by random tamming and transmitted as described above, as long as the initial value data is transmitted, it is relatively easy for eavesdropping to occur. In particular, in the case of a unidirectional system, the receiving side cannot receive a response as to whether or not it has received the initial value data accurately without any errors, so the same initial value data must be transmitted many times, so it is difficult to manipulate eavesdropping. The disadvantage is that the security for

Therefore, in the case of the above-mentioned unidirectional system, the transmission initial value data is changed gradually, and the initial value data must be immediately decoded each time it is changed to prevent unauthorized viewing.

FIGS. 8 and 9 show an example of the configuration of a conventional encrypted information transmission system that transmits initial value data as described above.

Note that FIG. 8 shows the encoder side, and FIG. 9 shows the decoder side.

In FIG. 8, a source video signal from a source such as a VTR is led to a terminal 801.

The source video signal is input to a scrambling circuit 802, and a random timing signal 8 is output from a random number generator 803.
03a, the horizontal synchronizing signal is randomly compressed or uncompressed and supplied to the data superimposition circuit 804. The data superimposition circuit 804 is a circuit that superimposes initial value data required on the decoder side into the transmitted video signal.

A synchronization separation circuit 805 separates the source video signal into a horizontal synchronization signal Hsy and a vertical synchronization signal Vsy. Each synchronization signal) 1sy, VSV is timing generator 80
6, and are supplied to predetermined circuits as various timing signals. The timing pulse generator 806 drives the random number generator 803 with a drive pulse 806a, and
The vertical period pulse P1 and the signal 8078.807b from the transmission number control circuit 807 are connected to an AND gate AN.
1.

The output of the AND gate AN1 is supplied to the random number generator 803 as an initial value load pulse 806b, and the output of the AND gate AN2 is supplied to the initial value generation circuit 808 as an initial value change pulse 806c. The output of the initial value generation circuit 80 is used as one input data of the superimposed data creation circuit 809, and the output of the delay circuit 81
1 to the random number generator 803. The delay circuit 811 delays the initial value data 808a from the initial value generation circuit 808 by n field periods (nV) for transmitting the same initial value data.

As a result, the scrambled video signal based on the initial value data currently being transmitted will be transmitted after the n field period has elapsed.

The transmission number control circuit 807 has the function of counting a predetermined number of vertical synchronizing signals Vsy from the synchronization separation circuit 8.5 to control scrambling with the same initial value data and the number of transmissions thereof. Therefore, the initial value change pulse 806c output from the AND gate AN2 is (nV) in the delay circuit 8.
11, and signal 807a is used as a data switching control signal to superimposed data creation circuit 809. This superimposition data creation circuit 809 is a circuit that selects the output of the initial value generation circuit 808 and the output of the synchronization pattern generation circuit 810 and supplies it to the data superposition circuit 804.
The synchronization pattern signal is selected at timing 7a, and the initial value data 808a is selected during other periods.

FIG. 10 shows a timing chart of control operations performed by the transmission number control circuit 807, in which (a) shows transmission initial value data;
(b) shows the transmitted video signal, and (C) shows the load pulse to the random number generator.

As shown in this figure, the initial value data X newly generated at the timing of the initial value change pulse 806c is transmitted while being superimposed on the video signal scrambled with the previous initial value data generated before the nV period. I understand.

Next, the configuration on the decoder side will be explained.

The transmission signal from the data line is transmitted to terminal 90 in FIG.
Appears in 1. The signal at this terminal 901 is a baseband scrambled video signal that has passed through a tuner and an IF detection circuit (not shown), and is input to a descrambling circuit 902. A descrambling circuit 902 descrambles the synchronously compressed video signal at the timing of a random number signal from a random number generator 903 that generates random numbers that match those on the encoder side. The following configuration is a circuit that causes the random number generator 903 to generate random numbers whose timing matches that of the encoder side.

A signal from the terminal 901 is input to a data extracting circuit 904 and a synchronization separation circuit 907. The synchronous separation circuit 907 is
A horizontal synchronizing signal H3V and a vertical synchronizing signal Vsy are separated from the scrambled video signal and supplied to a timing pulse generator 908. The data sampling circuit 904 uses the timing pulse 908b from the timing pulse generator 908 to generate the vertical blanking line d! of the scrambled video signal! 1 Extract the data that was folded during the last period. The output of the data extraction circuit 904 is supplied to a synchronization pattern detection circuit 906 and a data determination circuit 905.

Further, the vertical synchronizing signal (Sy) from the synchronizing separation circuit 907 is counted and inputted to the transmission number counter 909. This transmission number counter 909 has a counter function that matches the number of transmissions of the transmission number control circuit 807 on the encoder side, and is reset by the AND output of the reset signal 906a from the synchronization pattern detection circuit 906 and a carry output (not shown). be done.

The synchronization pattern detection circuit 906 searches for a synchronization pattern in the data from the data sampling circuit 904 using the detection timing signal 908c from the timing pulse generator 908, and outputs a reset signal 906a when the retrieved data is a synchronization pattern.

The data determining circuit 905 is a circuit that determines the contents of initial value data transmitted n times (n is an integer of 1 or more) in units of bits, and for example, a majority circuit is used. The data determination circuit 905 transmits a bit comparison clock (as shown in the figure) for comparing each bit of the initial value data with the contents of the n-count decode output 909a from the number counter 909 and the bit synchronization output 908 of the timing pulse generator 908.
It is obtained by d. Further, when the data determining circuit 905 determines the data content and supplies the output 905a to the random number generator 903, a pulse 9 generated at the timing of the synchronization pattern is generated.
The counter of the majority circuit is cleared by a clear pulse (path shown) formed by 08e and the output 909a. A random number generator 903 generates random numbers based on data determined as initial value data by a data determining circuit 905.

Note that the random number generator 903 includes an AND gate 9 that inputs the final count decode output 909a and a predetermined timing pulse 908f from the timing generator 908.
The data from the data determination circuit 905 is loaded by the output 910a of 10.

In this way, in conventional subscriber broadcasting systems that use unidirectional communication, the deterioration of security for eavesdropping caused by transmitting initial value data multiple times in succession is prevented by periodically changing the initial value data. . The initial value data compares the contents of each bit of multiple received data and determines the correct data by majority vote, so in reality the decoder side can only obtain the initial value data once for multiple fields. I understand.

On the other hand, since the pulse 903a that drives the random number generator 903 on the decoder side is generated by the timing pulse generator 908 based on the synchronization signal from the synchronization separation circuit 907, noise may occur in the data line and the synchronization signal If there is a loss or increase in the number, correct drive pulses cannot be obtained, the random numbers will deviate from the encoder side, and there is a drawback that descrambling cannot be performed accurately.

Moreover, in the case of the above system, the initial value data is essentially obtained only once in multiple fields, so if the synchronization signal is not separated normally in one of the sections of the scrambled video signal based on the certain initial value data. , the video signal of the entire section is forced to be received on the screen due to a descrambling malfunction.

(Problem to be solved by the invention) In a conventional CATV system using unidirectional communication, the initial value data for descrambling that is transmitted multiple times is periodically changed, and the data determined from the transmitted data of multiple valves is As the initial value, the same random number as the encoder side is obtained at the timing of a predetermined timing signal generated based on the transmission synchronization signal, so if noise occurs in the transmission system, the synchronization signal for that period will not be obtained correctly. If there wasn't,
There was a circuit defect in that descrambling could not be performed accurately until at least the next initial value data was transmitted and the data contents were determined. For this reason, it is difficult for subscribers to obtain correct information, and there is a problem in that subscribers suffer losses due to countermeasures against eavesdropping.

This invention solves the above problems and provides extremely high-quality information to contract subscribers even when there is noise in the transmission system, while transmitting pay broadcasting signals with high security for non-contract subscribers. The purpose of this invention is to provide a scramble decoding information transmission system.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes an original initial value generating means for generating original initial value data for a random number generator on the encoder side, and a time-based method for converting the data generated by the original initial value generating means. a key data generating means that converts key data to @9 with key data that is changed; a means for generating driving information for driving the key data generating means; the driving information generated by the driving information generating means; and the original initial value. data, or original initial value-related data obtained by encrypting the same, and transmission information scrambled with random numbers generated by the random number generator using the original initial value data encrypted with the key data as an initial value, and transmitting the transmission information to the decoder side. means of transmission,
On the decoder side, an extraction means for extracting the transmitted original initial value data or original initial value related data and the drive information, and the drive information extracted by this extraction means is applied to generate corresponding key data on the encoder side. a random number generator that obtains an initial value of the random number generator on the encoder side by the key data generating means and generates a random number for descrambling the scrambled transmission signal; This system is designed to prevent unauthorized viewing using only the initial value data.

(Function) According to the present invention, the actual scrambling of the transmitted information is performed using conversion data obtained by logically converting the transmitted initial value data using key data on the encoder side, so that only the transmitted initial value data is decoded. In this case, it is impossible to obtain the correct descrambling timing.

In addition, since the decoder side can reproduce key data in synchronization with the encoder side without going through a transmission path, the timing of random number generation may shift due to an increase in missing synchronization signals, and the information for that information unit period may not be descrambled properly. Even in this case, if the content of the original initial value data changes, correct descrambling can be performed from that period. Conventionally, the timing of random number generation remained shifted until the initial value data change period had passed, but by changing the actual initial value using the above key data, the descrambling malfunction period can be kept to the minimum period. will be possible.

(Example) Hereinafter, the present invention will be explained with reference to the illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of an information transmission system according to the present invention, and FIGS. 2 and 3 show the configuration in detail.

In FIG. 1, the transmission data processing means 11 is a circuit that inputs a source video signal 1o and performs scrambling.
The output of the processing means 11 is guided to the transmission line 13 via the data superimposition means 12. The source video signal 10 is also supplied to the transmission number control means 14. Transmission frequency control means 1
4 counts the vertical synchronization signal of the source video signal and outputs signals 14a, 14b, 14 . It is outputting c. Of these, the signal 14a is a signal that is incremented every time the vertical synchronization signal is counted, and is input to the initial value conversion means 16. The output signals 14b and 14C of the transmission number control means 14 are signals that give the timing to change the initial value data. For example, when changing the initial value data every n fields, the maximum count value of the transmission number control means 14 is n. At this time, the signal 14b is output corresponding to the count value n. As a result, new initial value data is generated at the timing of the n count value output 14b, and the superimposed data creation means 17 outputs the synchronous pattern generation means 1 when the n count value is output.
8 is selected, and initial value data is selected for the other periods. Note that the initial value generating means 15 maintains new initial value data from count value n to n-1 of the next count period.

On the other hand, the initial value conversion means 16 converts the previously generated initial value data (in FIG. 10, the current transmission data into the data of Then, it has a function of latching and outputting data (corresponding to data A random number signal 16a based on the random number signal 16a is generated. Then, the source video signal input to the transmission data processing means 11 is scrambled at the timing of the output random number signal 16a.

In this way, a scrambled video signal is transmitted to the transmission line 13 using the converted data as an initial value.

The scrambled video signal 19 from the transmission path 13 is sent to the received data processing means 20. The data is supplied to data extraction means 21 and transmission count means 22. The received data processing means 20 is the transmission data processing means 11 on the encoder side.
This circuit performs the opposite process to descramble the scrambled video signal. Further, the data extraction means 21 is a circuit that extracts all initial value data superimposed over a predetermined period for each field.

The transmission number counting means 22 counts the vertical synchronization signal in the scrambled video signal, and outputs the count output 2.
2a is supplied to the initial value conversion means 23. In this case, when the synchronization pattern detection means 24 that searches for a synchronization pattern detects a synchronization pattern, the transmission count means 22 clears the counter value by a signal 24 indicating the timing thereof. As a result, the initial value conversion means 23 outputs the same random number signal 23a as that on the encoder side.
The received data processing means 20 outputs a descrambled video signal that has been accurately descrambled.

FIG. 2 is a block diagram showing the encoder side of the above configuration. Comparing FIG. 2 and FIG. 1, the transmission data processing means 11 is connected to the scrambling circuit 202, the data superimposition means 12 is connected to the data superimposition circuit 204, and the number of transmission times IIJII
The I means 14 includes a synchronous separation circuit 205, a field counter 213 . and an n-ary decoder 212, the initial value generating means 15 is an initial value generating circuit 208, the initial value converting means 16 is an initial value latch circuit 214. Initial value conversion circuit 2
15 and a random number generator 203, the superimposed data generating means 17 includes a data switching circuit 209. and a P/S (parallel/serial) converter 216, and the synchronization pattern generation means 18 corresponds to the synchronization pattern generation circuit 210, respectively. In addition, the field counter 21
8. The circuit 207 composed of the 3 and the n-ary decoder 212 corresponds to the transmission number control circuit 807 in FIG.

The details will be explained below.

A terminal 201 is an input terminal for a source video signal, and a signal from the terminal 201 is supplied to a data superimposition circuit 204 via a scrambling circuit 202. The signal from the terminal 201 is also input to the synchronization separation circuit 205, where the horizontal synchronization signal H8V and vertical synchronization signal vSy are separated. The timing pulse generator 206 inputs the basic clock signal and the horizontal synchronization signal Hsy, and is further reset by a pulse from a reset circuit 211 that generates an output at the timing of the vertical synchronization signal vSy.

The difference between the timing pulse generator 206 and the one in FIG. 8 is that the load pulse 206b to the random number generator 203 is
is outputted every field (conventionally, it was outputted only once every n fields). The reason why the load pulse 206b is supplied every field in this way is that the count output 207C from the transmission number control circuit 207 is supplied to the initial value conversion circuit 215 newly provided in the present invention, and the substantial initialization to the random number generator 203 is performed. This is because the value is changed for each field. This count output 207c corresponds to the signal 14a in FIG. Note that the timing pulse generator 206 generates pulses P2., which correspond to pulse P1 in FIG. and P/S for driving the P/S converter 216.
Generates an S conversion clock 206c and a load pulse 206d.

In the circuit 207, the field counter 213 is self-reset by the carry output CR. Also n
The decimal decoder 212 outputs n-1 count value decode 20
7b and n count value decode output 207a are output, and are supplied as one input to the AND gate AN3 and as a switching control signal for the data switching circuit 209, respectively. Pulse P2 is supplied to the other input of AND gate AN3, and as a result, AND gate AN3 causes the initial value generation circuit 208 to generate a new initial value at the timing of the n-1 count value decode output 207b, and also generates a new initial value. The obtained initial value data is latched into the initial value latch circuit 214.

The initial value data generated by the initial value generation circuit 208 is n
n count value decode output 207a of hex decoder 212
The data is output from the data switching circuit 209 at a timing other than the above. The data selectively output from the data switching circuit 209 is parallel data, which is converted into serial data by the P/S converter 216 and input to the data superimposition circuit 204.

On the other hand, the initial value latch circuit 214 latches the previous initial value data immediately before new initial value data is generated at the n-1 count timing, and outputs the next n-1 count output 207.
The initial value data is held until b arrives. In other words, each time new initial value data is generated, the initial value conversion circuit 2 holds the initial value data that was generated immediately before.
15. As a result, the initial value conversion circuit 2
15 supplies converted data 215a obtained by logically converting the data from the initial value latch circuit 214 to the random number generator 203 in accordance with the increment value of the signal 207C. The random number generator 203 can scramble the source video signal by outputting a random number signal 203a that randomly generates pulses according to the conversion data 215a.

FIG. 3 is a block diagram showing the configuration of the decoder. Comparing this FIG. 3 with FIG. 1, the received data processing means 20
is the descrambling circuit 302. and a random number generator 303, the data extraction means 21 includes a data extraction circuit 3.
04. In the circuit consisting of the S/P converter 313, the transmission number counter 22 includes a synchronous separation circuit 307. A circuit consisting of a field counter 312° and an n-ary decoder 311, a synchronization pattern detection circuit 306 for the synchronization pattern detection means 24, and a majority data determination circuit 305 for the initial value conversion means 23.
Initial value latch circuit 314. Each corresponds to a circuit consisting of the initial value conversion circuit 315.

A terminal 301 is a terminal to which a baseband scrambled video signal is guided. The signal from the terminal 301 is supplied to the descrambling circuit 302, and is also input to the synchronization signal separation circuit 307 to be horizontal.

and vertical synchronization signals H3V and VSV. The timing pulse generator 308 is connected to this synchronous separation circuit 307.
Drive pulse 308a to random number generator 303, load pulse 308f, S/P converter 3
13, a detection timing signal 308c to the synchronization pattern detection circuit 306, and pulses Ql and Q2 for outputting a bit comparison clock 308d, a clear pulse 308e, and a latch pulse 308g from AND gates AN4, AN5, and AN6, respectively.
.

Generates Q3. Pit comparison clock 308d.

The clear pulse 308e is supplied to the data determination circuit 305, which compares the data from the S/P converter 313 during the period from count value rOJ to In-IJ, and determines the count value rnJ.
Clear the data when.

Furthermore, the latch pulse 308Q is a pulse for latching the determined data into the initial value latch circuit 314 at the timing of the count value rnJ.

Now, the major difference between the timing pulse generator 308 and the conventional one is that the load pulse 30 of the random number generator 303
The reason is that 8f is generated every field. Correspondingly, the count output value from the field counter 312 is supplied to the value conversion circuit 315. As a result, the initial value conversion circuit 315 converts the conversion data 31 that changes every field.
5a can be supplied to the random number generator 303 as initial value data. Conventionally, as explained in FIG. 10, the initial value load pulse was applied to the random number generator only once when the initial value data was changed.

Note that the field counter 312 and the n-ary decoder 31
1 is a circuit corresponding to the conventional transmission number counter 909, but the field counter 312 is reset by the detection output 306a of the synchronization pattern detection circuit 306 and the carry (CR) output.

This invention is configured as described above, and as shown in FIGS. 4 and 5.
The figure is a circuit diagram showing an example of a specific configuration of the initial value conversion circuit 215 and the majority data determination circuit 305 used in the above configuration.

Figure 4 shows an initial value conversion circuit 215 using the encoder side as an example.
FIG. 1 is a circuit diagram. It goes without saying that the decoder side also has a similar circuit. In this example, the count output value of the field counter 213 consists of 4 bits, but since the initial value data is 8 bits, the obtained converted data 215a is 8 bits.

The random number generator 203 is composed of a digital circuit mainly including a shift register (random number generator 203) that generates M-sequence PN patterns among pseudo-random patterns, and the conversion data from the initial value conversion circuit 215 is loaded. The signals are input in parallel to the same shift register at the timing of pulse 206b.

The drive pulse 206a sequentially outputs the converted data 213a as the initial value data inputted in parallel in series at the timing of the horizontal synchronization signal. This output 203a is a signal that randomly exhibits pulses, and can perform scrambling, for example, by outputting a normal synchronization signal when there is no pulse, and compressing and outputting the synchronization signal when there is a pulse.

FIG. 5 is a circuit diagram showing a specific example of the majority data determining circuit 305. This example uses up counter 401. Comparator 402. It is also composed of a comparison value setting circuit 403. The number of each of these circuits is the same as the number of bits of initial value data.

The bit comparison clock signal 308d is sent to the S/P converter 313
are compared with each parallel bit from AND gate AN7 . . . , and the counter 401 counts the number of AND outputs when the logic is “1”.

The counter 401 performs the above counting every time data is sent from the S/P converter 313 and outputs a count value A. The output A is compared with the value B by the comparator 402.
The comparator 402 determines that the bit data that entered the counter 401 when B≦A is 1″,
It outputs it to the initial value latch circuit 314 as initial value data.

Here, A is an integer C that is 1 or more larger than the integer B, and B is the number of times the initial value data is transmitted on the encoder side (assumed to be an odd number), and if the judgment condition is that A is 1 or more larger, then (
n-2)/2. Specifically, when n=10,
B is set to 4, and when A becomes 5, data is determined and output.

Next, the operation of the above embodiment will be explained with reference to FIGS. 6 and 7.

FIG. 6 is a timing chart on the encoder side. (
a) is the vertical synchronization signal V separated by the synchronization separation circuit 205
sy, and (b) shows the counter value of the field counter 213. In this example, the vertical synchronization signal @ V sy is 1
The counter value is reset every time it counts 0. That is, field counter 213 is a decimal counter, and correspondingly, decoder 212 also uses a decimal decoder.

Now, after the counter 213 is reset, when the ninth vertical synchronizing signal Vsy is counted (field count value r8J), an output appears at the n-1 decode output terminal of the decimal decoder 212.

The output P2 of the timing pulse generator 206 is generated at a predetermined timing in every vertical scanning period, and when the n-1 count value decoded output is generated, the initial value shown in FIG. 6(C) is generated by the AND gate AN3. A modification pulse 214a is generated. The initial value generation circuit 208 generates new initial value data using the initial value change pulse 214a, but the initial value latch circuit 214 generates the previously generated initial value immediately before the new initial value data is generated. Latch data. This latched previous initial value data is then supplied to the initial value conversion circuit 215.

In this way, the initial value conversion circuit 215 changes the initial value data at the timing of the field count value "9". Therefore, the random number generator 203 converts data that changes every 10 fields (initial value data) and data that changes every field in the same pattern every 10 fields (output of the field counter 213). The actual transmission video signal is scrambled by inputting the data 215a in parallel every field using the load pulse 206b and generating random numbers using the drive pulse 206a. In this example, the interval from the count value "9" to the counter value "8" of the 10th field is
This is an interval in which the initial value data is the same.

On the other hand, the newly generated initial value data is transferred to the data switching circuit 2.
Supplied on 09.

Since the decimal decoder 212 generates an n count value decoded output during the count value "9" period, the data switching circuit 209 selects the synchronization pattern and outputs the P/S conversion circuit 2.
16. The P/S conversion circuit 216 takes in this synchronization pattern data at the timing of the load pulse 206d, converts it into serial data at the timing of the conversion clock, and sends it to the data superimposition circuit 204. Data switching circuit 20
9 is the count value “When the next vertical synchronization signal is counted,
0'', the newly generated initial value data is supplied to the data superimposition circuit 204 via the P/S modification circuit 216 at the stage of the count value "9". In this way, in the scrambled video signal, the information for decoding the scrambling performed in the next 10-field section is transmitted to the decoder side in the section 10 fields before the next 10-field section. This is similar to what was explained in FIG.

In FIG. 6, (d) shows the output of the P/S converter 216, (e) shows the timing of the load pulse to the random number generator 203, and (f) shows the timing of the drive pulse (shift pulse).

Next, FIG. 7 is a timing chart on the decoder side.

In FIG. 7, (a) is a data extraction pulse 308b given to the S/P converter 313.

The initial value data extracted by this pulse 308b is subjected to data determination by the majority decision circuit 305 as explained in FIG. 5. (e), (q)
is the bit comparison clock 30 necessary for this data determination process.
8d, clear pulse 308e. The pit comparison clock 308d does not occur during the insertion period of the synchronization pattern,
It can be seen that 3089 clear pulses are generated during the same period.

FIG. 7(b) shows the detection timing signal g308G to the synchronization pattern detection circuit 306. This timing signal 308G, like the load pulse 308f to the random number generator 303 shown in FIG. 7(h), is generated in every field and at the same time.

If the data detected by the detection timing signal 308C is a synchronous pattern, the synchronous pattern detection circuit 306 generates a signal 306a shown in FIG. 7(C). At this time, the count of the field counter 312 (
The direct timing is when the count value is "9", which is the same timing as the synchronization pattern is inserted on the encoder side. Further, the signal 306a is generated over one field period, and since the field counter 312 uses a synchronous reset counter, it is cleared at the rise of the vertical synchronization signal when the signal 306a is ``1''.
From the rising edge of the vertical synchronizing signal during the period in which the signal 306a is "1", the value changes from 1 to "o". Note that even if the synchronization pattern is not received, the field counter 312 returns from the counter value "9" to "0" by the self-resetting function (see FIG. 7d).

On the other hand, the data determining circuit 305 uses a clear pulse 308e.
Count value "4" in the initial value interval before the occurrence of
The data is determined when the value is 8. When the count value is "8", the field counter 31
Since this is the period in which the count value decoded output of n-1 of 2 appears, the determined data is immediately transferred to the initial value latch circuit 3.
14. Since the next n-1 count value decoded output appears after the 10th field, the data latched in the initial value latch circuit 314 is converted to an initial value from the count value "9" field to the 8th field of the next initial value interval. The signal is supplied to circuit 315. Then, in accordance with this initial value data, the initial value conversion circuit 315 has a count value "
Count data that changes sequentially from field to field from "9" to "8" is supplied.

The initial value conversion circuit 315 is a logic circuit with the same configuration as in FIG. 4, and if count data that changes at the same timing as the encoder side is supplied for the same initial value data as the encoder side, the encoder side conversion is performed. It is clear that the same transformed data 315a as the data 215a can be supplied to the random number generator 303. This allows the descrambling circuit 302 to perform correct descrambling.

The signal (i>) shown in FIG. 7 is a pulse 308a that drives the random number generator 303. Conventionally, when noise occurs in the transmission path, the number of pulses of this drive pulse 308a increases or decreases because the synchronization signal is not transmitted accurately. However, in this invention, a random number signal whose timing is shifted from that of the encoder side is generated, and it is not possible to perform descrambling with the correct timing until the initial value data is changed and the data is determined. Even if an increase or decrease in pulses causes a shift in output bits, the converted data 315a is input in parallel in the next field, so the shift in descrambling can be suppressed within that field.

Further, although the present invention continuously transmits the same initial value data for a plurality of periods, correct descrambling cannot be performed only with this transmitted initial value data. In other words, when attempting to eavesdrop on a video, malicious descrambling is impossible unless the timings of the field counters managed on both the encoder and decoder sides are synchronized.

Note that the above embodiment is just an example, and for example, the data for initial value conversion does not need to be the output of a field counter.

In short, it is sufficient if the output pattern changes sequentially over time according to a certain rule.

[Effects of the Invention] As described above, according to the present invention, security against eavesdropping is high, and the period of descrambling malfunction due to increased synchronization signal loss is suppressed to the minimum period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the encrypted information transmission system according to the present invention, FIGS. 2 and 3 are block diagrams of an encoder and a decoder that further embody the configuration of FIG. 1,
4 and 5 are circuit diagrams showing an example of a specific circuit used in this invention, FIGS. 6 and 7 are time charts for explaining the invention in detail, and FIGS. 8 and 9 are FIG. 10 is a block diagram showing a conventional system and a time chart showing the transmission timing of initial value data and video signals. 202... Scramble circuit, 204... Data superimposition circuit, 203... Random number generator, 215... Initial value conversion circuit, 207... Transmission number control circuit, 213... Field counter. 212... N-ary decoder, 302... Descrambling circuit, 303... Random number generator, 309... Transmission number counter 312... Field counter. 311...N-ary decoder, 315...Initial value conversion circuit, 207c, 312a...Field counter number (direct,
215a...conversion data, 315a...conversion data. Figure 1 Figure 5

Claims (1)

[Scope of Claims] A cryptographic information transmission system having a random number generator and an initial value generation means for scrambling and descrambling transmission information on an encoder side and a decoder side, respectively, wherein an original initial value for the random number generator on the encoder side is provided. an original initial value generation means for generating value data; a key data generation means for encrypting the original initial value data generated by the original initial value generation means with key data that changes over time; means for generating driving information for driving; and the driving information generated by the driving information generating means, the original initial value data, or the original initial value related data that is encrypted from the original initial value data, and the original initial value related data that is encrypted with the key data. a transmission means for transmitting transmission information scrambled using random numbers generated by the random number generator using the original initial value data as an initial value to a decoder side; extraction means for extracting data and the drive information; key data generation means for generating key data corresponding to the encoder side to which the drive information extracted by the extraction means is applied; A cryptographic information transmission system comprising: a random number generator that obtains an initial value of the random number generator on the encoder side and generates a random number for descrambling the scrambled transmission signal.