JPS63167529A - High frequency amplifier circuit - Google Patents

High frequency amplifier circuit

Info

Publication number
JPS63167529A
JPS63167529A JP31281786A JP31281786A JPS63167529A JP S63167529 A JPS63167529 A JP S63167529A JP 31281786 A JP31281786 A JP 31281786A JP 31281786 A JP31281786 A JP 31281786A JP S63167529 A JPS63167529 A JP S63167529A
Authority
JP
Japan
Prior art keywords
circuit
high frequency
frequency
frequency amplifier
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31281786A
Other languages
Japanese (ja)
Inventor
Rikiya Suga
力也 菅
Atsushi Kishiwada
岸和田 篤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toko Inc
Original Assignee
Toko Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toko Inc filed Critical Toko Inc
Priority to JP31281786A priority Critical patent/JPS63167529A/en
Publication of JPS63167529A publication Critical patent/JPS63167529A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Abstract

PURPOSE:To improve the image disturbing ratio by providing a trap circuit comprising a parallel resonance circuit in series with a high frequency transistor (TR) receiving an output from an antenna input stage of a high frequency amplifier circuit so as to make the reception sensitivity constant. CONSTITUTION:An output from the antenna input circuit is inputted to a terminal 1 and fed to a gate of an FET 3 of a high frequency amplifier circuit via a capacitor. A trap circuit 18 comprising a parallel resonance circuit consisting of a coil 16 and a capacitor 17 is connected to the source of the FET 3 and an image frequency f2 is trapped from the output of the FET 3 of the high frequency amplifier circuit. In using the high frequency amplifier for a front end part of the receiver, the image disturbing ratio is much improved in comparison with a conventional receiver and decreased to a degree nearly neglecting the image disturbance.

Description

【発明の詳細な説明】 〔発明の産業上の利用分野〕 本発明は、スーパーヘテロゲイン受信機の受信特性の改
善を計った高周波増幅回路に関するもので、殊に上側ヘ
テロダイン型の受信機に好適な高周波増幅回路である。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field of the Invention] The present invention relates to a high frequency amplifier circuit designed to improve the reception characteristics of a superheterodyne receiver, and is particularly suitable for an upper heterodyne type receiver. This is a high frequency amplification circuit.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第5図乃至第7図は、従来のスーパーヘテロゲイン受信
機に係り、その高周波増幅回路及び同調回路とを含むフ
ロントエンド部の概要を示した回路図である。図面を通
して、lはアンテナ入力回路からの入力信号が供給され
る端子、2は高周波増幅回路と同調回路を介して得られ
る出力を導出する出力端子、3は高周波増幅用の電界効
果型トランジスタ(以下、FETと称する。)、4.5
はコイルと可変容量ダイオード等の容量素子が並列に接
続された同調回路、6は同調電圧が印加される端子であ
る。第5図は、同調回路5の出力段にコイル7とコンデ
ンサ8からなる直列共振回路9が接続されており、第6
図は、信号入力段にコイル11とアンテナの容1110
とによって並列共振回路12が接続されている。第7図
は、同調回路5の出力段に抵抗13とコンデサ14から
なるフィルター回路15が接続されている。
FIGS. 5 to 7 are circuit diagrams schematically showing a front end section of a conventional superhetero gain receiver including a high frequency amplification circuit and a tuning circuit. Throughout the drawings, l is a terminal to which an input signal from the antenna input circuit is supplied, 2 is an output terminal that derives the output obtained via the high-frequency amplification circuit and the tuning circuit, and 3 is a field-effect transistor for high-frequency amplification (hereinafter referred to as , referred to as FET), 4.5
6 is a tuning circuit in which a coil and a capacitive element such as a variable capacitance diode are connected in parallel, and 6 is a terminal to which a tuning voltage is applied. In FIG. 5, a series resonant circuit 9 consisting of a coil 7 and a capacitor 8 is connected to the output stage of the tuned circuit 5.
The figure shows a coil 11 and an antenna capacity 1110 at the signal input stage.
A parallel resonant circuit 12 is connected by. In FIG. 7, a filter circuit 15 consisting of a resistor 13 and a capacitor 14 is connected to the output stage of the tuning circuit 5.

一般に、スーパーヘテロゲイン受信機に於いては、同調
回路の負荷QLは、受信周波数が高域になる程低下して
、イメージ妨害特性が悪化する欠点がある。又、一般に
高周波増幅回路の利得は、第4図の(イ)に示すように
同調回路4.5の周波数特性により高域で上昇して受信
周波数全域における利得を一定にできない特性を持って
いる。
In general, superhetero gain receivers have the disadvantage that the load QL of the tuning circuit decreases as the receiving frequency becomes higher, resulting in worsening of image disturbance characteristics. Additionally, as shown in Figure 4 (a), the gain of a high frequency amplifier circuit generally increases in the high range due to the frequency characteristics of the tuning circuit 4.5, making it impossible to maintain a constant gain over the entire receiving frequency range. .

因に、第4図の横軸は、受信周波数fを示し、縦軸が利
得を示している。第4図の(イ)から明らかなようにイ
メージ周波数f2の所で利得が上昇している為に不要な
イメージ周波数を増幅してイメージ妨害比が変化しSN
比が悪くなる欠点がある。
Incidentally, the horizontal axis in FIG. 4 shows the receiving frequency f, and the vertical axis shows the gain. As is clear from (a) in Figure 4, the gain increases at the image frequency f2, so the unnecessary image frequency is amplified and the image interference ratio changes.
The disadvantage is that the ratio is poor.

これらの問題点を改善する為に、第5図に示すように出
力段にコイル7とコンデンサ8からなる直列共振回路9
を具えることによってイメージ周波数をトラップして、
イメージ妨害比の改善を行いっている。第6図及び第7
図では入力段或いは出力段に並列・共振回路12或いは
フィルター回路15を具えることにより高周波増幅回路
の利得周波数特性を調整している。又、両方の特性を改
善しようとすると、第5図と第6図、或いは第7図の回
路を組み合わせねばならなく高周波増幅回路のフロント
エンド部の構成が複雑となり、部品数が多くなり高価と
なる欠点があった。
In order to improve these problems, a series resonant circuit 9 consisting of a coil 7 and a capacitor 8 is installed in the output stage as shown in FIG.
Trap the image frequency by providing
The image interference ratio has been improved. Figures 6 and 7
In the figure, the gain frequency characteristics of the high frequency amplifier circuit are adjusted by providing a parallel resonant circuit 12 or a filter circuit 15 at the input stage or the output stage. Also, if you try to improve both characteristics, you will have to combine the circuits shown in Figures 5 and 6 or 7, which will complicate the configuration of the front end section of the high frequency amplifier circuit, increase the number of parts, and make it expensive. There was a drawback.

〔発明の目的〕[Purpose of the invention]

本発明は、上述のごとき問題点を改善する為になされた
もので、その主な目的は、イメージ妨害比の改善と高周
波増幅回路に接続された同調回路の出力の受信周波数に
対する利得の均一化が容易になし得る筒便な回路からな
る高周波増幅回路を提供するものである。
The present invention has been made to improve the above-mentioned problems, and its main objectives are to improve the image interference ratio and to equalize the gain of the output of the tuning circuit connected to the high-frequency amplifier circuit with respect to the receiving frequency. The object of the present invention is to provide a high frequency amplification circuit consisting of a convenient circuit that can be easily implemented.

〔発明の実施例〕[Embodiments of the invention]

第1図及び第2図は、本発明に係る高周波増幅回路に同
調回路が接続された実施例を示す回路図であり、上側ヘ
テロゲイン方式のラジオ受信機に適するものである。ア
ンテナ入力回路からの出力が端子1に入力され、コイデ
ンサを介して高周波増幅回路のFET3のゲート電極に
供給される。
FIGS. 1 and 2 are circuit diagrams showing an embodiment in which a tuning circuit is connected to a high frequency amplifier circuit according to the present invention, and is suitable for an upper hetero gain type radio receiver. The output from the antenna input circuit is input to the terminal 1, and is supplied to the gate electrode of the FET 3 of the high frequency amplifier circuit via the co-capacitor.

第1図では、FET3のソース電極、或いは第2図の如
(FET3のドレーン電極にコイル16とコンデンサ1
7からなる並列共振回路からなるトラップ回路18が接
続され、高周波増幅回路のFET3の出力からイメージ
周波数f2をトラップするようになされている。尚、F
ET3の後段の同調回路4,5は、従来例に示した回路
と同様な構成となっているので説明を省略する。
In Fig. 1, the source electrode of FET 3 is connected, or as shown in Fig. 2 (the drain electrode of FET 3 is connected to the coil 16 and the capacitor 1).
A trap circuit 18 consisting of a parallel resonant circuit consisting of 7 is connected to trap the image frequency f2 from the output of the FET 3 of the high frequency amplification circuit. In addition, F
The tuning circuits 4 and 5 at the subsequent stage of the ET3 have the same configuration as the circuit shown in the conventional example, so a description thereof will be omitted.

さて、第3図と第4図の利得周波数特性を示す図によっ
て本発明の高周波増幅回路の利得周波数特性とイメージ
妨害比について説明する。
Now, the gain frequency characteristics and image interference ratio of the high frequency amplifier circuit of the present invention will be explained with reference to FIGS. 3 and 4 which show the gain frequency characteristics.

第3図は、同調回路を介して得られる出力端子2からの
出力の受信周波数fに対する利得周波数特性を示してい
る。図の横軸が周波数fを示し、縦軸が同調回路からの
出力の利得を示している。
FIG. 3 shows the gain frequency characteristic of the output from the output terminal 2 obtained through the tuning circuit with respect to the receiving frequency f. The horizontal axis of the figure shows the frequency f, and the vertical axis shows the gain of the output from the tuned circuit.

flが受信周波数、foが局部発振周波数、f2がイメ
ージ周波数である。第3図の(イ)は、第1図及び第2
図のFET3にトラップ回路18を付加しない場合の高
周波増幅回路の利得周波数特性を示す図であり、第3図
の(イ)から明らかなように高周波増幅回路がイメージ
周波数12をも増幅して、イメージ妨害比が悪いことを
示している。これに対してFET3に直列に並列共振回
路からなるトラップ回路18を具えることにより第3図
の(ロ)に示す如き利得周波数特性を得ることができる
。受信周波数f、から高域側の利得が従来のもの或いは
本発明のFET3からトラップ回路18を取り除いた回
路と比較して低減され、イメージ周波数f2を充分にト
ラップしていることを示している。従って11本発明の
高周波増幅回路を受信機のフロントエンド部に用いるこ
とによって、従来の受信機と比較して、極めてイメージ
妨害比が改善され、略イメージ妨害を無視できる程度に
低減されることが分かる。
fl is the reception frequency, fo is the local oscillation frequency, and f2 is the image frequency. Figure 3 (a) is the same as Figure 1 and 2.
This is a diagram showing the gain frequency characteristics of the high frequency amplifier circuit when the trap circuit 18 is not added to the FET 3 in the figure, and as is clear from (a) of FIG. 3, the high frequency amplifier circuit also amplifies the image frequency 12, This shows that the image interference ratio is poor. On the other hand, by providing a trap circuit 18 consisting of a parallel resonant circuit in series with the FET 3, a gain frequency characteristic as shown in FIG. 3(b) can be obtained. The gain on the high frequency side from the receiving frequency f is reduced compared to the conventional one or the circuit in which the trap circuit 18 is removed from the FET 3 of the present invention, indicating that the image frequency f2 is sufficiently trapped. Therefore, by using the high frequency amplification circuit of the present invention in the front end section of a receiver, the image interference ratio can be significantly improved compared to conventional receivers, and the image interference can be reduced to a negligible level. I understand.

更に、本発明に係る高周波増幅回路の出力の利得周波数
特性について説明する。第4図の(イ)は、第1図及び
第2図の実施例からトラップ回路18を除去した場合の
利得周波数特性であり、最高と最低の受信感度に差を生
じ、受信感度を悪化させるのに対して本発明の高周波増
幅回路は、第1図及び第2図に示すように高周波増幅回
路のFET3のソース及びドレーンの何れかに並列共振
回路からなるトラップ回路1日が具えられている。
Furthermore, the gain frequency characteristics of the output of the high frequency amplifier circuit according to the present invention will be explained. FIG. 4(a) shows the gain frequency characteristic when the trap circuit 18 is removed from the embodiments shown in FIGS. 1 and 2, which causes a difference between the highest and lowest receiving sensitivities and deteriorates the receiving sensitivity. In contrast, the high frequency amplifier circuit of the present invention is provided with a trap circuit consisting of a parallel resonant circuit at either the source or drain of FET 3 of the high frequency amplifier circuit, as shown in FIGS. 1 and 2. .

第4図の(ロ)に示す如きイメージ周波数f2を減衰す
る利得周波数特性を持っている。
It has a gain frequency characteristic that attenuates the image frequency f2 as shown in FIG. 4(b).

さて、並列共振回路からなるトラップ回路18のアドミ
タンスYは周知のように、コンデンサl7の容量をCと
し、コイル16をコイルの固有の直列抵抗rとインダク
タンスをLとすると、次のように表わされる。
Now, as is well known, the admittance Y of the trap circuit 18 consisting of a parallel resonant circuit is expressed as follows, where the capacitance of the capacitor l7 is C, the coil 16 has its own series resistance r, and the inductance is L. .

1−ω” Lc+jωrc r  +jωL −・−・・−・−・・・−・・−−−−−−(11イメ
一ジ周波数f2の共振周波数ω。で並列間tJJH路の
インピーダンスが最小となるように設定する。
1-ω” Lc+jωrc r +jωL −・−・・−・−・・・・・−−−−−−(11 At the resonance frequency ω of the image frequency f2. Set it as follows.

共振周波数ω。が(2)弐のとき、アドミタンYは、Y
 −−r  となり、イメージ周波数f2に於いて、イ
ンピーダンスが略最小値を示す。このようにイメージ周
波数f2を減衰する特性のトラップ回路18を持ってい
る。
Resonant frequency ω. When (2) is 2, Admitan Y is Y
--r, and the impedance shows a substantially minimum value at the image frequency f2. In this way, the trap circuit 18 has a characteristic of attenuating the image frequency f2.

本発明の如く、FET3に対して直列にトラップ回路1
8を接続することにより、受信周波「1より高域の利得
を減衰し、イメージ周波数f2を充分に除去した第3図
の(ロ)の如き利得周波数特性となるが、その高周波領
域の特性は、第4図の(ロ)の如き利得周波数特性によ
って決定されている。
As in the present invention, the trap circuit 1 is connected in series to the FET 3.
By connecting 8, the gain in the receiving frequency range higher than 1 is attenuated and the image frequency f2 is sufficiently removed, resulting in a gain frequency characteristic as shown in (b) in Fig. 3, but the characteristics in the high frequency region are as follows. , is determined by the gain frequency characteristics as shown in (b) of FIG.

又、FET3からの出力に第4図の(ロ)の如き受信周
波数の低域から高域に渡って利得を減衰して、イメージ
周波数f2を大きく減衰するような利得周波数特性を持
たせることによって同調回路からの出力、即ち出力端子
2からの出力の利得を、第4図の(ハ)に示すように受
信周波数に対して利得を均一なものとすることができる
。従って、本発明の高周波増幅回路を用いた受信機によ
れば、受信帯域の低域と高域で受信感度を均一にするこ
とができ、良好な受信特性を得ることができる。
Also, by attenuating the gain from the low to high frequencies of the receiving frequency as shown in (b) in Figure 4, the output from FET3 has a gain frequency characteristic that greatly attenuates the image frequency f2. The gain of the output from the tuning circuit, that is, the output from the output terminal 2, can be made uniform with respect to the receiving frequency, as shown in (c) of FIG. Therefore, according to the receiver using the high frequency amplifier circuit of the present invention, it is possible to make the reception sensitivity uniform in the low and high frequencies of the reception band, and to obtain good reception characteristics.

尚、高周波増幅回路のトランジスタは、実施例の如く電
界効果型、或いはバイポーラ型のトランジスタで構成す
ればよい。高周波増幅回路の後段の同調回路の構成は、
第5図乃至第7図の従来例と同様な構成となっているが
、高周波増幅回路及び同調回路の構成は、第1図及び第
2図の同調回路に限定するものではない。
Note that the transistors of the high frequency amplifier circuit may be constructed of field effect type or bipolar type transistors as in the embodiment. The configuration of the tuning circuit after the high-frequency amplifier circuit is as follows:
Although the configuration is similar to the conventional example shown in FIGS. 5 to 7, the configurations of the high frequency amplifier circuit and the tuning circuit are not limited to the tuning circuits shown in FIGS. 1 and 2.

〔発明の効果〕〔Effect of the invention〕

本発明の高周波増幅回路に依れば、高周波増幅回路のア
ンテナ入力段からの出力が供給される高周波用トランジ
スタに対して直列に並列共振回路からなるトラップ回路
を具えるのみで、高周波増幅回路の後段の同調回路から
の出力を低域から高域に亙たって利得を均一にして受信
感度を一定とすることと、イメージ妨害比の改善を同時
に満足させることができる。
According to the high frequency amplification circuit of the present invention, the high frequency amplification circuit only has a trap circuit made of a parallel resonant circuit in series with the high frequency transistor to which the output from the antenna input stage of the high frequency amplification circuit is supplied. It is possible to make the gain of the output from the subsequent tuning circuit uniform from the low frequency range to the high frequency range, thereby making it possible to make the receiving sensitivity constant and to improve the image interference ratio at the same time.

依って、本発明の高周波増幅回路を用いれば、良好な受
信特性を得る為に、従来より少ない部品数で達成され、
安価な受信機を提供することが可能である。
Therefore, by using the high frequency amplifier circuit of the present invention, good reception characteristics can be achieved with fewer parts than conventional ones.
It is possible to provide an inexpensive receiver.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の高周波増幅回路とその後段に同調回
路が接続された一実施例を示す回路図、第2図は、本発
明の高周波増幅回路とその後段に同調回路が接続された
他の実施例を示す回路図、第3図は、本発明を説明する
為の利得周波数特性を示す図、第4図は、受信周波数に
対する利得周数特性を示す図である。 1、Z、S:端子、   3:電界効果型トランジスタ
、3.4:同調回路、  16:コイル。
Fig. 1 is a circuit diagram showing an embodiment in which a high frequency amplification circuit of the present invention and a tuning circuit are connected to the subsequent stage, and Fig. 2 is a circuit diagram showing an embodiment in which the high frequency amplification circuit of the present invention and a tuning circuit are connected to the subsequent stage. FIG. 3 is a circuit diagram showing another embodiment, FIG. 3 is a diagram showing gain frequency characteristics for explaining the present invention, and FIG. 4 is a diagram showing gain frequency characteristics with respect to reception frequency. 1, Z, S: terminal, 3: field effect transistor, 3.4: tuned circuit, 16: coil.

Claims (1)

【特許請求の範囲】[Claims] アンテナ入力回路からの入力信号が供給される高周波増
幅回路が、所定の受信周波数に同調をとる同調回路を具
え、該アンテナ入力回路からの入力信号が供給される該
高周波増幅回路のトランジスタに対して直列に接続され
た並列共振回路を具えたことを特徴とする高周波増幅回
路。
The high frequency amplification circuit to which the input signal from the antenna input circuit is supplied includes a tuning circuit that tunes to a predetermined reception frequency, and the transistor of the high frequency amplification circuit to which the input signal from the antenna input circuit is supplied; A high frequency amplification circuit characterized by comprising parallel resonant circuits connected in series.
JP31281786A 1986-12-27 1986-12-27 High frequency amplifier circuit Pending JPS63167529A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31281786A JPS63167529A (en) 1986-12-27 1986-12-27 High frequency amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31281786A JPS63167529A (en) 1986-12-27 1986-12-27 High frequency amplifier circuit

Publications (1)

Publication Number Publication Date
JPS63167529A true JPS63167529A (en) 1988-07-11

Family

ID=18033768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31281786A Pending JPS63167529A (en) 1986-12-27 1986-12-27 High frequency amplifier circuit

Country Status (1)

Country Link
JP (1) JPS63167529A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0328837U (en) * 1989-07-28 1991-03-22

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54146908A (en) * 1978-05-10 1979-11-16 Hitachi Ltd High frequency amplifier circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54146908A (en) * 1978-05-10 1979-11-16 Hitachi Ltd High frequency amplifier circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0328837U (en) * 1989-07-28 1991-03-22

Similar Documents

Publication Publication Date Title
US4048598A (en) Uhf tuning circuit utilizing a varactor diode
US7999608B1 (en) Integrated RF notch filters
US3942120A (en) SWD FM receiver circuit
JPH0715245A (en) Amplifier
US3570005A (en) Radio receiver input circuit for reduced loading by capacitive antennas
US3959728A (en) Local oscillation circuit for tuner having reduced inter-channel deviation in AFC sensitivity
JPS63167529A (en) High frequency amplifier circuit
JPS6233383Y2 (en)
JPS636904Y2 (en)
JPS636906Y2 (en)
US2188964A (en) Image-frequency suppression system
JPS6148239A (en) Am receiver
EP0920735B1 (en) Receiver with a tunable parallel resonant circuit
JPS6133723Y2 (en)
KR890005515Y1 (en) Input circuit of uhf tuner
JPS6017933Y2 (en) Base grounded transistor amplifier circuit
JPS5827543Y2 (en) tuned circuit
JPS6143293Y2 (en)
JPS6022661Y2 (en) bandpass filter
US3716792A (en) Selective oscillator mixer for a superheterodyne receiver
KR950001643Y1 (en) Ti filter for tuner
KR101547250B1 (en) Image trap filter circuit of tuner
JP3539601B2 (en) Input tuning circuit of VHF tuner
JPS623948Y2 (en)
JPH0226420B2 (en)