JPS63165937A - Memory clearing method for semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the clearing time by using a detecting device which detects the drop of the DC power supply voltage of a semiconductor memory device. CONSTITUTION:When an instruction is received from a host device for start of a clearing action of an entire area after application of a power supply, an address '0', i.e., the initial value of an address of a memory part 3 is defined as a write address with a certain fixed data defined as the clear data respectively. Then each clearing interval is set at the value Smax that produces no DCLow by securing a clearing action even with the maximum loading of the memory part 3. Then the time obtained by multiplying the value Smax by a reference clock period tc is defined as the clear interval time and a clearing instruction is given to the part 3. Here it is decided whether the output of a DCLow detector 4 is set at a high or low level. Then -1 is set to the clear interval S to give a clearing instruction again with a high level of the output of the detector 4. Thus a clear interval where no eddy current is produced is obtained and hereafter the addresses of the part 3 are successively replaced as '1', '2' and so on. Then a clearing instruction is given to the part 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory clearing method for a semiconductor memory device.

(Prior Art) Nowadays, software operations are gradually becoming larger in scale, and the amount of data handled is also increasing significantly, and the storage capacity of semiconductor storage devices is also increasing year by year.

FIG. 2 shows a schematic block diagram of a conventional semiconductor memory device.

FIG. 2 shows that when the power supply section 1 of the device is turned on, DC power is supplied to the control section 2 and the storage section (inner cage group) 3, respectively, and the storage section (. This is a device for writing to and reading from the mother cage group) 3.

Next, FIG. 3 is a time chart of the operation when all contents of the storage section of the apparatus shown in FIG. 2 are cleared.

First, after the power is turned on, when an instruction to start clearing all areas is given to the host device (not shown), the controller 2 sets the "0" address, which is the initial value of the memory address, as the write address. , as clear data, certain fixed data is written into the storage unit 3 as write data.

Thereafter, the storage unit address is sequentially updated to 1'', 2'', . . . , and writing is performed up to the final address "m" of the final package in the storage unit.

When the writing to the final address "'m" is completed, the control unit 2 reports the completion of all area clearing to a higher level device (not shown), and the all area clearing operation is completed.

(Problems to be Solved by the Invention) As explained above, in the past, when clearing the entire contents of a storage unit, it was done by a write operation word by word. However, there was a drawback that the clearing time increased.

Therefore, the present invention has been made in view of the above points, and when clearing, the data to be cleared is fixed data. The purpose of the present invention is to provide a memory clearing method for a storage device.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention includes a detection device that detects a drop in the DC power supply voltage of a semiconductor storage device, and a clearing device that forcibly issues a write instruction to the storage device. When inputting an instruction signal to each storage device to clear the entire area of the semiconductor storage device, the clear instruction signal is first given at preset intervals, then the output of the detection device is detected, and a drop in the power supply voltage is detected. If not, the clear instruction signal is given again with a shortened interval, and if a drop in the power supply voltage is detected, the clear instruction signal is given at the interval set before that. be.

(Function) Since the memory clearing method for a semiconductor storage device of the present invention has the above-described configuration, the clearing time is shortened, and since a drop in the DC power supply voltage of the semiconductor storage device is detected, overcurrent is prevented. The device never loses power.

(Embodiment) FIG. 4 is a schematic block diagram of a semiconductor memory device according to the present invention. In the figure, 4 indicates that clearing several words at once will reduce the output voltage when an overcurrent condition occurs. This is a DCLovr detector that takes advantage of the drop.

FIG. 5 shows an example of the DC Low detector 4 shown in FIG.
For example, TI, 7705CP manufactured by TI.

FIG. 6 shows the internal configuration of the storage unit 3 shown in FIG.
This is a diagram showing a mother cage, and shows, for example, a storage unit made up of N packages.

FIG. 7 shows a schematic connection diagram between the control unit 2 and the storage unit 3 shown in FIG. FIG. 8 shows an example of a write signal generation circuit in each package 5 shown in FIG. 8 is an AND dart that makes the write instruction valid only when a package is selected, and 8 is an OR that generates a write signal when the own package is selected and a write instruction is given, or when a clear instruction is given. It's dirt.

FIG. 1 shows an operation flowchart for clearing all areas according to the present invention.

Next, one embodiment of the present invention will be described using FIG. 1 and FIGS. 4 to 8.

First, after the power is turned on, when an instruction to start clearing all areas is given to the device from a higher-level device (not shown), the controller 2 sets the initial value of the memory address, ``0'' address, as the write address, and writes Fixed data is cleared data, 1
The value Smax that does not become DCLow by clearing the clearing interval of the rotation shift even when the storage unit is installed to the maximum
Then, a clear instruction is given to the storage unit 3 by setting the time obtained by multiplying Smax by the reference clock cycle tc as the clear interval time.

At that time, it is determined whether the output of the DC Low detector 4 is High level or Low level. If it is High level, it means that no overcurrent condition has occurred and the output voltage has not decreased. Therefore, the clearing interval S is (
-1) L, issue a clear instruction again.

A clearing interval in which an overcurrent condition cannot occur is determined, and thereafter, the memory unit address is sequentially updated to 1'', '2'', etc., and a clear instruction is given to the memory unit 3.

Therefore, as shown in FIGS. 7 and 8, in the present invention, when a clear instruction is given, a write signal is generated for all of each package. This is an instruction to clear the address.

In order to clear the entire area, if you clear up to the final address "n" of each package, the entire area will be cleared.

(Effects of the Invention) As explained in detail above, the present invention is capable of clearing the same address of all packages with − times of clearing instructions, regardless of the number of packages that make up the storage unit. This has the advantage of providing a semiconductor memory device with shortened readout time.

Furthermore, although there is a risk that an overcurrent condition may occur by clearing several words at once, there is an advantage that the occurrence of an overcurrent condition can be prevented by determining the optimum clearing interval time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an operation flowchart for clearing all areas according to the present invention, FIG. 2 is a schematic block diagram of a conventional semiconductor memory device, and FIG. 3 is a diagram showing a clear operation in a conventional semiconductor memory device. A time chart, FIG. 4 is a schematic block diagram of a semiconductor memory device according to the present invention, and FIG. 5 is a DCLo
w A schematic block diagram of the detector, Fig. 6 shows the internal configuration of the storage section, Fig. 7 shows the schematic connection between the control section and the storage section, and Fig. 8 shows the writing in each package. FIG. 3 is a diagram showing an example of a signal generation circuit. l...power supply unit, 2...control unit, 3...storage unit, 4
...DC Low detector, 5... Storage package,
6...Comparator, 7...AND dart, 8...OR
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Claims (1)

[Scope of Claim] A method for clearing an entire storage area in a semiconductor memory device that is composed of a plurality of memory devices, one of which is selected by a selection signal to perform reading/writing, the semiconductor memory device comprising: a detection device that detects a drop in the DC power supply voltage of the semiconductor memory device, and inputs a clear instruction signal to each memory device to forcibly instruct the memory device to write, and when clearing the entire area of the semiconductor memory device, first Give the clear instruction signal at preset intervals, then detect the output of the detection device, and if no drop in power supply voltage is detected, shorten the interval for giving the clear instruction signal and issue the clear instruction signal again. 1. A memory clearing method for a semiconductor storage device, characterized in that when a drop in power supply voltage is detected, a clear instruction signal is given at a preset interval.