JP2707767B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus capable of performing a mask process on an arbitrary portion of binary image data obtained by binarizing a captured image of a work. Things.

(Prior Art) As a conventional image processing apparatus of this type, there is, for example, one shown in FIG. 6, in which 50 denotes a one-dimensional camera (video camera).

The one-dimensional camera 50 is connected to a camera interface circuit 51, and the camera interface circuit 51 is connected to a binarization circuit 52.
And an address control circuit 53, which is connected to comparators 54 and 55. Further, a mask ON address storage register 56 and a mask OFF address storage register 57 are connected to the comparators 54 and 55, respectively. The output terminals of the comparators 54 and 55 are the input terminal (S) and the input terminal (R) of the SR flip-flop 58, respectively. )It is connected to the. The output terminal (Q) of SR flip-flop 58 is a binarization circuit
Connected to the OR gate 59 with the output terminal of 52, the OR gate 59
Are connected to a normal image processing circuit (not shown).

An image signal (video image signal) from the one-dimensional camera 50 is input to a binarizing circuit 52 via a camera interface circuit 51, where it is binarized (the video image at this time and the binarized binary image thereof). An example of the voltage waveform of the value image is shown in FIGS. 7 (a) and (b). In synchronization with this, the address control circuit 53 generates a Y address corresponding to each scanning line and an X address corresponding to each bit of each scanning line, and inputs them to the comparators 54 and 55. The comparator 54, based on the video image, the binary image as shown in example Figure 8 (a), is inputted from the mask ON address storing register 56 which stores the address X _s should start masking and address X _s, by comparing the X address as described above, it sets the SR flip-flop 58 to high (1) when they match. Similarly, the comparator 55
Is input from the mask OFF address storing register 57, to low (zero) to reset the SR flip-flop 58 on the basis of a comparison of the X address and the address X _e should be terminated masking. As a result, the SR flip-flop 58
1 or 0 and the binary image (1 or 0) are logically operated by the OR gate 59 to output a final masked binary image as shown in FIG. Become. In this case X _e from X _s in the binary image with the mask
The range from (1) to (0) is masked to eliminate the drop from the first 1 to zero in FIG.

In the (0006) However, such conventional image processing apparatus, the mask start address X _s and mask end address X _e
Since only one set can be set, only one common location can be masked for each binary image. If masking is to be performed for a plurality of locations or a different range should be masked for each binary image of each scan line, It is necessary to provide a plurality of similar circuits, which leads to an increase in cost due to a complicated circuit configuration.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problem by writing mask data to a desired address of a memory having an address corresponding to each scan line and bit.

(Means for Solving the Problems) For this purpose, an image processing apparatus according to the present invention includes a binarization circuit for binarizing an image of a work imaged by an imaging unit, and a predetermined circuit for binarizing the obtained binary image data. An image processing apparatus comprising: a mask circuit that performs a mask process on an address;
A Y address memory having a Y address corresponding to each scan line, an X address corresponding to each bit of each scan line, and storing an X address memory and a preset Y address and X address to be masked If the scan line is a line of the Y address to be masked, the mask flag data is written to the Y address of the Y address memory, and the X bit of the line to be masked is to be masked. A data writing means for writing mask data to the X address of the X address memory, the mask flag data and the binary image data when the bit is an address, Configure the circuit,
Data in the X address including the X address, the mask flag data, and the binary image data in the X address memory is output.

(Operation) When scanning a certain bit on a line with a work,
Binary image data obtained by binarizing the image of the work is written to the X address of an X address memory having an X address corresponding to each bit of each scan line. If the scan line is a line of a Y address to be masked, mask flag data is written to the Y address of the Y address memory, and the bit is to be masked for the line to be masked. X
Address bits, the X address of the X address memory, the mask flag data,
Mask data (for example, 1) is written to the X address including the value image data, and the mask data is output from the X address memory.

Therefore, if the data written in the X address memory is sequentially read and arranged for one scanning line, a binary image with a desired mask added can be obtained.

In this way, an image processing apparatus that can set a plurality of masks on the same scanning line, set a mask at an arbitrary position for each scanning line, and easily change the mask once set is provided. In addition, compared to the case where the above-described mask function is realized by the configuration of the conventional example, the configuration can be made with an extremely simple circuit configuration, and the cost can be significantly reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the image processing apparatus according to the present invention, in which 10 denotes a one-dimensional camera (video camera).

The one-dimensional camera 10 sequentially captures an image of one scan line of a workpiece by a built-in one-dimensional line sensor, and the obtained video image is input to the camera interface circuit 11. The video image that has passed through the camera interface circuit 11 shows a voltage waveform in which the voltage sharply drops near both ends of the work viewed in the scanning line direction, as shown in FIG. Input to the conversion circuit 12. The binarization circuit 12 compares this voltage waveform with the threshold voltage shown in FIG. 1 to binarize the signal by setting a portion having a voltage higher than the threshold voltage to 1 and a portion having a voltage lower than the threshold voltage to zero. It is possible to obtain a binary image as shown in FIG.

On the other hand, the camera interface circuit 11 has a binarization circuit
An address control circuit 13 is connected together with 12, and a control signal is input to the address control circuit 13 in synchronization with the scanning of the one-dimensional camera 10. Address control circuit that receives this signal
13 generates a Y address corresponding to each scanning line and a Y address corresponding to each bit of each scanning line, and inputs them to the Y address memory 14 and the X address memory 15, respectively. Note that these memories 14 and 15 need to be able to write and rewrite data as described later.
-Access memory).

Here, the Y address memory 14 and the X address memory
An outline of writing data to 15 will be described. As shown in FIG. 2, when address data (YADO to YAD15) is input to the Y address memory 14 from the address control circuit 13 in 16 bits corresponding to A0 to A15, the Y address memory 14 is determined by the address data. The mask flag data (YD0 to YD2) is written to the Y address of the memory cell, and the mask flag data (YD0 to YD2) is input to the X address memory 15. In the X address memory 15, as shown in FIG.
The address control circuit 13 sends 12-bit address data (XA
D0 to XAD11) and the binary data BVD (1 or 0) from the binarization circuit 12, ｛(X
AD0 to XAD11), (3 bits of 1 or 0), BVD}
When the same 1 or zero as VD is written, and when the mask flag data (YD0 to YD2) is input from the Y address memory 14, X determined by {(XAD0 to XAD11), (YD0 to YD2), BVD} Mask data XD0 described later is written to the X address of the address memory 15, and this XD0 becomes the final binary image data with mask.

Data writing means 16 is provided for writing data to the X, Y address memory. The data writing means 16
When the same 1 or 0 as BVD is written to the X address determined by {(XAD0 to XAD11), (3 bits 1 or 0), BVD} of the address memory 15, and the scan line is a line to be masked Write 1 to at least one bit of the 3-bit data (YD0 to YD2) to be written to the Y address of the Y address memory 14 (if the line is not masked, write zero for all three bits). X when the corresponding bit of the power line is a bit to be masked.
@ (XAD0 to XAD11), (YD0 to YD) of address memory 15
2) It is assumed that 1 is written in the X address determined by BVD｝ (zero is written in the case of a non-masked bit), and the previously set line and bit to be masked are stored. The written data can be arbitrarily rewritten by data writing means.

An inspection stage that actually uses this image processing apparatus is configured as shown in FIG. That is, the cylindrical work 20 is rotatably supported by the work clamp device 21, and is rotated by the drive of the work rotating device 22 coupled to the lower end thereof. At this time, the one-dimensional camera 10 fixed to the jig 23 sequentially images the work side surface 20a illuminated by the illumination device 24 with the rotation of the work, and based on the obtained video image, a defect exists on the side surface of the work. Check whether or not. At this time, a hole is
If a range in which a notch or the like exists, that is, a range in which a binary signal “zero” exists in the work is known in advance, if a mask process is performed on the range, the hole, the notch, or the like is excluded from the determination target and the work is removed. Only the defect on the side surface is detected, which is useful for determining the defect of the work.

This mask processing is executed based on the flowcharts of FIGS. That is, first, address data (XAD0 to XAD11) is input from the address control circuit 13 to the bits indicated by A0 to A11 in FIG.
In step 102, a signal BVD (1 or 0) obtained by binarizing the input signal from the one-dimensional camera 10 by a binarizing circuit is input to a bit of the X address memory 15 indicated by A15 in FIG. Here, if BVD is zero, the control proceeds from Yes in step 103 to step 104, where ｛(X
AD0 to XAD11), (3 bits of 1 or 0), BVD}, write the same zero as BVD as XD0 to all X addresses. If BVD is 1, control is passed from No in step 103 to step 105. Proceed to the X address memory 15 (XAD0 to XAD
AD11), (3 bits of 1 or 0), and the same 1 as BVD is written as XD0 in all of the X addresses determined by BVD (this data writing is performed by the data writing means 16).

In the next step 106, address data (YAD0 to YAD15) is input from the address control circuit 13 to the Y address memory 14, and in step 107, the address data (YAD0 to YAD15) is input.
It is determined whether or not the scan line of the Y address determined by is a line to be masked. This determination is made by a data writing means storing a preset line and bit to be masked.
16 and if the scan line is a masking line, at step 108 at least one of the three bits
The mask flag data (YD0 to YD2) with the bit set to 1 is Y
If the line is not the line to be written and masked at the Y address of the address memory 14 and the mask flag data (YD0 to YD2) with all three bits set to zero is written at the Y address of the Y address memory 14 at step 109, Steps 110 and 111, which will be described later, are skipped, and the control is terminated as it is (this makes the mask processing more efficient). Then, the control proceeds from step 108 to step 110 to determine whether or not the bit is a bit to be masked (this determination is made by the data writing means 16 storing a preset masking line and bit). If yes, step 1
At 11 ｛(XAD0 to XAD11) and (YD0 to
YD2), mask data XD0 at the X address determined by BVD｝
Write = 1. In the case of No in step 110, step 111 is skipped.

The data XD0 thus written is read out according to the flowchart of FIG. That is, first, in step 121 of FIG. 5, based on the input signal from the one-dimensional camera 10, the address control circuit 13 stores the address data (YAD0 to YAD1).
5), (XAD0 to XAD11) are determined, and the address data (YAD0 to YAD1) in the Y address memory 14 is determined in step 122.
The data (YD0 to YD2) referenced in 5) is output to the X address memory 15. In the next step 123, the data XD0 referred to by the address data (XAD0 to XAD11) and the address data consisting of the data (YD0 to YD2) and BVD in the X address memory 15 is output as a final binary signal with a mask. (This output is input to a normal image processing circuit (not shown) at the subsequent stage, where image processing is performed).

Incidentally When a mask processing based on the flowchart of FIG. 4 and FIG. 5, for example of a binary image in the scan line shown in Figure 8 (a), while the X address X ₁ and X ₂ should masking In the case of the range, since BVD = 0, the data XD0 once set to XD0 = 0 by the writing of the data writing means 16 in step 104 of FIG.
By proceeding to 106-107-108-109-110-111, the mask data is written, XD0 = 1 is set and stored at the address, and by executing steps 121-122-123 in FIG. The corresponding binary signal XD0 with mask is read out, and as a result, a binary image with mask shown in FIG. 8B is obtained. Note that the writing and reading of data in the above mask processing are performed by identifying a scan line defined by a 16-bit Y address of (YAD0 to YAD15) in eight ways by a combination of 1 or zero of (YD0 to YD2). Can be performed every eight lines. In this example, “1” is written as the mask data. However, when “1” is used to check whether or not the work has a defect from the binary image, “0” is written. You can do it.

In this way, an image processing apparatus that can set a plurality of masks on the same scanning line, set a mask at an arbitrary position for each scanning line, and easily change the mask once set is provided. In addition, compared to the case where the above-described mask function is realized by the configuration of the conventional example, the configuration can be made with an extremely simple circuit configuration, and the cost can be significantly reduced.

In addition, since the mask can be set to only the minimum necessary address, the accuracy of inspecting a workpiece for defects from a binary image is also improved.

Further, by adjusting the setting of the mask, the binary image can be passed through with the original waveform as it is, or a part of the original waveform can be masked in common. By utilizing it as a generated pattern generator,
The operation of the device itself can be self-diagnosed.

(Effect of the Invention) As described above, the image processing apparatus of the present invention writes mask data at a desired address of a memory having an address corresponding to each scan line and bit. An image processing apparatus that can set a plurality of masks, set a mask at an arbitrary position for each scanning line, and can easily change a mask once set is provided by the above-described mask function with the conventional configuration. Can be configured with an extremely simple circuit configuration as compared with the case of realizing, and a significant cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the image processing apparatus of the present invention, FIG. 2 is a diagram for explaining the address configuration of X and Y address memories in the same embodiment, and FIG. FIG. 4 is a perspective view showing the configuration of an inspection stage using the image processing apparatus of the example. FIGS. 4 and 5 are flowcharts showing a control program for mask processing of the same example. FIG. 6 shows the configuration of a conventional image processing apparatus. 7 (a) and 7 (b) show a video image and its
FIGS. 8 (a) and 8 (b) are diagrams illustrating a binarized image and a masked binary image obtained by masking the binary image, respectively. 10: One-dimensional camera (video camera) 11: Camera interface circuit 12: Binarization circuit, 13: Address control circuit 14: Y address memory, 15: X address memory 16: Data writing means , 20 …… Work

Claims (1)

(57) [Claims] 1. An image of a work taken by an image pickup means is stored in two
An image processing apparatus comprising: a binarizing circuit for converting a value; and a mask circuit for performing a masking process on a predetermined address of the obtained binary image data. A Y address memory having a Y address corresponding to each scanning line; Having an X address corresponding to each bit of each scan line;
An X address memory in which the binary image data is written at each X address; a Y address and a X address to be masked which are set in advance;
If the line is an address line, the mask flag data is written to the Y address of the Y address memory. If the bit is a bit of the X address to be masked of the line to be masked, the X address is written. Data writing means for writing mask data at an X address of the memory comprising the X address, the mask flag data, and the binary image data, and the mask circuit is constituted by these means; An image processing apparatus for outputting data in an X address including an X address, the mask flag data, and the binary image data.