JPS63164761A - Vertical deflection circuit - Google Patents
Vertical deflection circuitInfo
- Publication number
- JPS63164761A JPS63164761A JP31500486A JP31500486A JPS63164761A JP S63164761 A JPS63164761 A JP S63164761A JP 31500486 A JP31500486 A JP 31500486A JP 31500486 A JP31500486 A JP 31500486A JP S63164761 A JPS63164761 A JP S63164761A
- Authority
- JP
- Japan
- Prior art keywords
- zener diode
- voltage
- smoothing capacitor
- feedback circuit
- vertical deflection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 18
- 238000009499 grossing Methods 0.000 claims abstract description 14
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
直流帰還回路を持つ垂直偏向回路において、直流帰還回
路を構成する平滑コンデンサを、容量を減少することな
く短時間に充電できるように構成することによって、垂
直偏向回路の立上がり時間を短縮した。[Detailed Description of the Invention] [Summary] In a vertical deflection circuit having a DC feedback circuit, the vertical deflection Reduced circuit startup time.
この発明はCR7表示装置に設けられる垂直偏向回路に
関するものである。The present invention relates to a vertical deflection circuit provided in a CR7 display device.
垂直偏向回路は垂直同期信号に同期したのこぎり波電圧
から垂直偏向電流を生成する装置であるが、特に図形表
示装置に用いるものにおいては。A vertical deflection circuit is a device that generates a vertical deflection current from a sawtooth voltage synchronized with a vertical synchronization signal, and is particularly used in graphic display devices.
表示図形の歪を減少することが非常に重要視されている
。Great importance is placed on reducing distortion of displayed graphics.
従来例の構成図を第3図に示す。図において。 A configuration diagram of a conventional example is shown in FIG. In fig.
1は電圧増幅部11と電流増幅部12とからなる増幅回
路。Reference numeral 1 denotes an amplifier circuit including a voltage amplification section 11 and a current amplification section 12.
2は抵抗R1と同R2とコンデンサCIとからなる直流
帰還回路。2 is a DC feedback circuit consisting of resistors R1 and R2 and a capacitor CI.
1は垂直偏向コイル(Lv) 、また5は交流帰還回路
である。1 is a vertical deflection coil (Lv), and 5 is an AC feedback circuit.
上記構成の垂直偏向回路では、電源投入の際。 In the vertical deflection circuit with the above configuration, when the power is turned on.
直流帰還回路2に含まれる平滑用コンデンサC1の充電
が終わり、この部分の電圧Vfが所定の値に達するまで
、約0.5〜1秒の間は垂直偏向がおこなわれないとい
う問題点がある。There is a problem in that vertical deflection is not performed for about 0.5 to 1 second until the smoothing capacitor C1 included in the DC feedback circuit 2 finishes charging and the voltage Vf in this part reaches a predetermined value. .
なお、この時間を短縮するには抵抗R1とコンデンサC
1とによって定まる時定数の値を減らすことも考えられ
るが、望ましい帰還信号を得るうえで好ましくない。In addition, to shorten this time, resistor R1 and capacitor C
Although it is possible to reduce the value of the time constant determined by 1, this is not preferable in terms of obtaining a desired feedback signal.
すなわち本発明の目的は、直流帰還回路の時定数を減少
することなく、電源投入の際の立上がり時間を短縮する
ことにある。That is, an object of the present invention is to shorten the rise time when power is turned on without reducing the time constant of the DC feedback circuit.
本発明による垂直偏向回路は、第1図の原理図に示すよ
うに。The vertical deflection circuit according to the present invention is shown in the principle diagram of FIG.
垂直同期信号に同期するのこぎり波を増幅して垂直偏向
コイルに供給する電流を生成する増幅回路1と。an amplifier circuit 1 that amplifies a sawtooth wave synchronized with a vertical synchronization signal and generates a current to be supplied to a vertical deflection coil;
垂直偏向コイル側から前記のこぎり波の入力側に直流信
号を帰還する直流帰還回路2と。a DC feedback circuit 2 that feeds back a DC signal from the vertical deflection coil side to the input side of the sawtooth wave;
直流帰還回路2を構成する平滑用コンデンサの高電位側
から正電源Va側に対し順方向に接続されるツェナーダ
イオード3とによって構成したものである。A Zener diode 3 is connected in a forward direction from the high potential side of the smoothing capacitor constituting the DC feedback circuit 2 to the positive power supply Va side.
直流帰還回路2に設けられている平滑用コンデンサの充
電を、ツェナーダイオード3を介し、その降伏電圧に達
するまで別の電源を利用しておこなうものである。The smoothing capacitor provided in the DC feedback circuit 2 is charged via a Zener diode 3 using another power source until its breakdown voltage is reached.
第2に実施例の構成図を示す。図中の符号は第1図・第
3図によって説明した通りであるから説明を省略する。Second, a configuration diagram of the embodiment is shown. The reference numerals in the drawings are the same as those described with reference to FIGS. 1 and 3, so their explanation will be omitted.
ツェナーダイオード3を介しコンデンサC1に接続する
正電源の電圧Vaは、ツェナーダイオード3の降伏電圧
をVzとし直流帰還回路2を構成する平滑用コンデンサ
の正常動作中の電圧をvfとするとき。The voltage Va of the positive power supply connected to the capacitor C1 through the Zener diode 3 is when the breakdown voltage of the Zener diode 3 is Vz and the voltage during normal operation of the smoothing capacitor constituting the DC feedback circuit 2 is Vf.
+ Va < Vz + Vf の関係にある値を用いる。+ Va < Vz + Vf Use values that are in the relationship.
電源を投入すると同時に、平滑用コンデンサC1には(
Va −Vz)の電圧が直接加えられる。At the same time as the power is turned on, the smoothing capacitor C1 (
A voltage of Va - Vz) is applied directly.
このため、平滑用コンデンサC1はツェナーダイオード
の降伏電圧に達するまで急速に充電され。Therefore, the smoothing capacitor C1 is rapidly charged until it reaches the breakdown voltage of the Zener diode.
ツェナーダイオード3がカントオフしてからvfに達す
るまでの間のみ帰還信号によって充電がおこなわれる。Charging is performed by the feedback signal only from the time when the Zener diode 3 cants off until it reaches vf.
その結果、電源を投入してから平滑用コンデンサの高電
位側の電圧が正常な値に達するまでの時間は0.1〜0
.2秒程度に短縮できる。As a result, the time it takes for the voltage on the high potential side of the smoothing capacitor to reach its normal value after turning on the power is 0.1 to 0.
.. It can be shortened to about 2 seconds.
以上説明したように1本発明の垂直偏向回路では、単に
1明のツェナーダイオードを追加するだけで、立上がり
時間を大幅に短縮することができる。As explained above, in the vertical deflection circuit of the present invention, the rise time can be significantly shortened simply by adding one Zener diode.
なお、ツェナーダイオードの追加が回路動作その他にあ
たえる悪影響はない。Note that the addition of the Zener diode does not have any adverse effects on circuit operation or other aspects.
第1図は本発明の原理図。 第2図は実施例の構成図。 第3図は従来例の構成図である。 図中。 1は増幅回路、 2は直流帰還回路。 3はツェナーダイオード。 4は偏向コイル、 5は交流帰還回路を表す。 FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a configuration diagram of the embodiment. FIG. 3 is a configuration diagram of a conventional example. In the figure. 1 is an amplifier circuit, 2 is a DC feedback circuit. 3 is a Zener diode. 4 represents a deflection coil, and 5 represents an AC feedback circuit.
Claims (1)
コイルに供給する電流を生成する増幅回路(1)と、 垂直偏向コイル側から前記のこぎり波の入力側に直流信
号を帰還する直流帰還回路(2)と、直流帰還回路(2
)を構成する平滑用コンデンサの高電位側から正電源側
に対し順方向に接続されるツェナーダイオード(3)と
を備えることを特徴とする垂直偏向回路。[Claims] An amplifier circuit (1) that amplifies a sawtooth wave synchronized with a vertical synchronization signal to generate a current to be supplied to a vertical deflection coil, and a DC signal is supplied from the vertical deflection coil side to the input side of the sawtooth wave. DC feedback circuit (2) to feed back and DC feedback circuit (2)
) and a Zener diode (3) connected in a forward direction from the high potential side to the positive power supply side of the smoothing capacitor forming the smoothing capacitor (3).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31500486A JPS63164761A (en) | 1986-12-26 | 1986-12-26 | Vertical deflection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31500486A JPS63164761A (en) | 1986-12-26 | 1986-12-26 | Vertical deflection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63164761A true JPS63164761A (en) | 1988-07-08 |
JPH044794B2 JPH044794B2 (en) | 1992-01-29 |
Family
ID=18060256
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31500486A Granted JPS63164761A (en) | 1986-12-26 | 1986-12-26 | Vertical deflection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63164761A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6529245B2 (en) | 1997-09-03 | 2003-03-04 | Hitachi, Ltd. | Display device also compatible with digital broadcasts |
-
1986
- 1986-12-26 JP JP31500486A patent/JPS63164761A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6529245B2 (en) | 1997-09-03 | 2003-03-04 | Hitachi, Ltd. | Display device also compatible with digital broadcasts |
Also Published As
Publication number | Publication date |
---|---|
JPH044794B2 (en) | 1992-01-29 |
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