JPS63164684A - Video signal recording and reproducing system - Google Patents

Abstract

PURPOSE:To record/reproduce an image of ordinary quality and that of high quality with simple constitution of the titled system by providing a first image pickup means and a second image pickup means disposed so that obtain a dot interlace picture element disposition, and switching and processing the signals that are outputted from the respective image pickup devices simultaneously every unit of two lined. CONSTITUTION:Two image pickup elements 12, 14 are both constituted of 600HX500V pieces of picture elements, and these constituent picture elements or dots are so disposed that they come in a dot interleaving relation. From the outputs 12a, 14a of the elements 12, 14, line signals that are to be included in the first field of an ordinary interlace video signal are outputted, and from the outputs 12b, 14b of then 12, 14, line signal to be included in the second field are outputted. Switches 18a, 18b, 18c ar switched associatively at every field by switch control signals from a clock generation circuit 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal recording and reproducing system, and more specifically to a recording and reproducing system capable of recording and reproducing high-quality video signals.

[Conventional technology and its problems]

Conventional home video systems consisting of a video tape recorder (VTR) and a video camera, such as a camera-integrated VTR, have VH3 format, β format, and 8.
Both millimeter systems have the disadvantage of lower resolution than broadcast video systems. However, in recent years, double-scan monitor devices have been developed that can display not only video signals with the standard number of lines (but also video signals with twice the standard number of lines), making it possible to display high-quality video even in ordinary homes. There are opportunities to have fun.

In addition, methods and devices for playing still images of moving images and viewing them as still images, as well as devices for making hard copies thereof, are being provided, and it is desirable to improve the image quality even in home video systems such as those mentioned above. It will be done.

Therefore, an object of the present invention is to provide a video signal recording and reproducing system capable of recording and reproducing not only the conventional standard number of lines but also high image quality.

(Means for Solving the Problems) A video signal recording and reproducing system according to the present invention includes a first imaging means disposed on an imaging plane, and a dot-interlaced pixel arrangement with the first imaging means. , a second imaging means disposed on a plane equivalent to the imaging plane, and switching between signals simultaneously output from the first imaging means two lines at a time and signals simultaneously output from the second imaging means two lines at a time. a recording system for simultaneously recording and processing the signals output from the switching means and recording two channels on a recording medium; and a reproducing system for simultaneously reproducing the two-channel recorded signals on the recording medium. , when reproducing the recorded signals of the two channels, each reproduced signal is time-compressed and then time-axis multiplexed.

[Effect]

The eleventh imaging means and the second imaging means arranged as described above make it possible to photograph and record a video signal having twice the normal number of lines, and by using only the recording signal of one channel, the normal line It can also be played back as multiple video signals.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 1A and 1B are block diagrams showing a configuration of an embodiment of the present invention. FIG. 1A shows a photographing/recording system, and FIG. 1B shows a reproduction system thereof.

In FIG. 1A, reference numeral 10 denotes an imaging lens of the photographic camera section. A two-dimensional image sensor 12 is arranged on the imaging plane of this lens 10, and a second imaging element 12 is arranged on a plane equivalent to the imaging plane formed by a half mirror 16. A two-dimensional image sensor 14 is arranged. The half mirror 16 is rotatably supported at its upper end and can take two positions: a position a shown by a solid line and a position a shown by a broken line. The two image sensors 12 and 14 both have 600 (
fl) x500 (V), and these constituent pixels or dots are arranged in a dot-interleaved relationship with each other as shown in Figure 2 in the image of the imaging plane. It is. In FIG. 2, ○ indicates, for example, the constituent pixels of the image sensor 12, and x indicates the image sensor 14.
The constituent pixels are shown.

The outputs 12a and 14a of the image sensor 12.14 output a line signal included in the first field of a normal interlaced video signal, and the outputs 12b and 14b output the second line signal.
The signal of the line included in the field is output. 18
a is a selector switch 18b for selecting either the output 12a of the image sensor 12 or the output 14a of the image sensor 14;
A switch 18c selects either the output 12b or the output 14b, and a switch 18c selects the output 12a or the output 12b. Switch 18a.

18b and 18c are switched in conjunction with each other field by a switching control signal from the clock generation circuit 20. Note that 22 is a drive circuit for the image sensor 12.14.

FIG. 3 shows the basic structure of the image sensor 12,14.

Vertical shift to extract signals from pixels in the same column.
Register 50 (50-1, 50-2, . . .

5 Q -600) and each vertical shift register 50
Two horizontal successive shift registers 52-1 and 52-2 are provided for horizontally reading out pixel signals from. Here, signals from pixels on odd-numbered lines are stored in a first horizontal successive shift register 52-1, and signals from pixels on even-numbered lines are stored in a second horizontal successive shift register 52-2. accommodate. Each pixel signal is the vertical clock CL
KV and gate control signal TG to the vertical shift register 50, and the signal of the vertical shift register 50 is transferred to the horizontal successive shift register 52-1, 52-2 by the horizontal clock CLK.

The signals of the horizontal successive registers 52-1 and 52-2 are shifted horizontally by appropriate lock signals, and the signals of the horizontal successive registers 52-1 and 52-2 are respectively
It is output from a (14a) and 12b (14b).

FIG. 4 shows the drum arrangement of the recording/reproducing head and its azimuth angle in this embodiment. Hl and H2 are head assemblies for high image quality, and the negative azimuth head assembly f(la, H2a) and the positive azimuth head assembly are shown in FIG. head H1b,
H2b.

H3 is a head assembly for normal image quality with negative azimuth, and H4 is a head assembly for normal image quality with positive azimuth. High image quality head assembly H1
, H2 head width is normal image quality head assembly H3
, H4. In other words, the head width of the positive azimuth heads H1a, H1b and the negative azimuth heads H2a, H2 of the high-quality head assembly.
The head width of b is normal image quality head assembly H3,
It is 1/2 of the head width of H4'. Also, like a conventional VTR, magnetic tape is wound around the drum over an angular range of 180° or more, and the drum rotates 1/2 revolution per field.

The operation when recording and reproducing in high image quality mode in the above configuration will be described. During recording in the high image quality mode, the half mirror 16 is placed at the solid line position a in FIG. 1A by a system controller (not shown), and the switch 19 and the switch 26 are both connected to the H side. In this state, the output signal of the switch 18a is subjected to well-known signal processing by the signal processing circuit 24a via the H side of the switch 19.
The signal is applied to the recording heads H1a and H2a through the H side of the signal line 6. Additionally, the output of the switch 18b is output from the signal processing circuit 24.
The signal is applied to the recording heads H1b and H2b via the signal line b. The signal processing circuit 24a is the same as the signal processing circuit 24b,
There are two parallel channels of signal processing systems for magnetic recording.

FIG. 5 shows the magnetic recording pattern in high image quality mode. If you want high-quality playback using interlaced scanning,
During recording, the switches 18a and 18b are connected to the outputs 12a and 12b of the image sensor 12 in the first field, and the switches 18a and 18b are connected to the outputs 14a and 14b of the image sensor 14 in the second field. Odd line signals are taken out from the outputs 12a and 14a of the image sensor 12.14, and even line signals are taken out from the outputs 12b and 14b. As for the recording order, for example, on track T, odd-numbered line signals from the image sensor 12 are recorded by the minus azimuth head H1a of the head assembly H1, and on track T'+z, the signals of odd lines are recorded by the minus azimuth head H1a of the head assembly H1. The negative azimuth head of the head assembly H2 is recorded on the 0th-order track T□ where even-numbered line signals from the image sensor 12 are recorded simultaneously with the track Tll by H1b. (Odd line signals from the image sensor 14 are recorded by 2a, and the plus azimuth head H is recorded in the track T'zz.
Track T by 2b! At the same time as I, even-numbered line signals from the image sensor 14 are recorded.

Next, the playback operation in high image quality mode will be explained. 1st
Switch 36 and switch 43 in Figure B are both connected to the H side by a system controller (not shown), and the reproduced signals from heads H1a and H2a are switched field by field by switch 34a and connected to the H side of switch 36. The reproduced signals from the heads H1b and H2b are switched for each field by a switch 34b and sent to the signal processing circuit 38b.
supplied to The signal processing circuits 38a and 38b convert the video signal into a signal format that can be output to a subsequent monitor device or the like.

The time axis compression circuits 40a and 40b are connected to the odd line signals output from the signal processing circuit 38a (see FIG. 6(a)).
) and the even line signal (shown in FIG. 6(b)) output from the signal processing circuit 38b are time-axis compressed to 1/2 and input to the serial conversion circuit 42. The serial conversion circuit 42 multiplexes the output signals of the time axis compression circuits 40a and 40b on the time axis as shown in FIG.
The signal is supplied to the output terminal 44 through the H-side terminal of No. 3. Therefore, if a double scan monitor or a high resolution monitor is connected to the output terminal 44, an interlaced display of 1051 lines can be realized, and an image with twice the resolution of the conventional display can be displayed.

Next, the operation in normal mode will be explained. When photographing and recording in the normal mode, the system controller (not shown) places the half mirror 16 at the dashed line position and connects the switches 19 and 26 to the N side. By switching the outputs 12a and 12b of the image sensor 12 for each field using the switch 18c, the interlaced output is supplied to the recording signal processing circuit 24a via the switch 19, where it is converted into a signal format suitable for magnetic recording. Ru. The output of the recording signal processing circuit 24a is applied to the head assemblies H3, H4 via the switch 26 and recorded on the magnetic tape.

During playback in normal mode, switches 36 and 43 are connected to the N side. The outputs of the head assemblies H3 and H4 are switched for each field by a switch 34c and supplied to a signal processing circuit 38a via a switch 36. The output signal of the signal processing circuit 38a is supplied to the output terminal 44 via the switch 43. It goes without saying that at this time, the switch 34c is switched in accordance with the trace timing of the head assemblies H3 and H4.

Such recording and reproduction in the normal mode is exactly the same as that of a conventional two-head helical scan VTR, and the illustrated embodiment can also perform recording and reproduction similar to that of a conventional VTR.

Finally, to explain the case where a signal recorded in high-quality mode is played back on a conventional 2-head helical scan VTR, the head assembly H3°H4 and the conventional VTR are used.
If the head widths are the same, one negative azimuth head will reproduce the track recorded by head H1a, and the other positive azimuth head will reproduce the track recorded by head H1a.
2b will be played back, and the first
The reproduced signal of the field is the odd line signal obtained from the image sensor 12, and the reproduced signal of the second field is the signal obtained from the image sensor 1.
This is the even line signal obtained from 4. That is, a recorded pattern such as that shown in FIG. 5 can be reproduced as a normal image quality signal by a conventional two-head helical scan VTR.

〔Effect of the invention〕

As can be easily understood from the above, according to the present invention, recording and playback of normal picture quality and recording and playback of high picture quality can be realized with an extremely simple configuration.

[Brief explanation of the drawing]

1A and 1B are block diagrams of the configuration of an embodiment of the present invention, FIG. 2 is a diagram corresponding to the pixel arrangement of the image sensor 12-14 in FIG. 1, and FIG. 3 is an example of the structure of the image sensor 12-14. , FIG. 4 is a diagram illustrating the arrangement of the recording/reproducing head of the circuit of FIG. 1 on a rotating drum and its agitation. 10...Imaging lens 12. 14-Image sensor 1
6-half mirror 18a, 18b...switch 20--clock generation circuit 22--imaging element drive circuit 24 a, 24 b--signal processing circuit 38a
, 38b --- signal processing circuit 40 a, 40
b1 Time axis compression circuit 42 -- Serial conversion circuit 4
4-・Output terminal 50 (50-1 to 600)・-Vertical shift register 52 (52-1, 52-2)-
・-Horizontal read shift register Hl, H2...-
Head assembly for high image quality mode) H3, H4...
−・Head assembly for normal mode

Claims (1)

[Claims] a first imaging means disposed on the imaging plane; a second imaging means disposed on a plane equivalent to the imaging plane so as to have a dot interlaced pixel arrangement with the first imaging means; A switch means for switching and outputting a signal simultaneously outputted from one imaging means two lines at a time and a signal simultaneously outputted two lines at a time from the second imaging means, and simultaneously recording and processing the signals outputted from the switching means. 2 on the recording medium
It is equipped with a recording system for channel recording and a reproduction system for simultaneously reproducing the two-channel recording signals of the recording medium, and when reproducing the two-channel recording signals, the respective reproduction signals are time-compressed and then time-axis multiplexed. A video signal recording and reproducing system characterized by: