JPS63164397A - Manufacture of multilayer printed interconnection board - Google Patents
Manufacture of multilayer printed interconnection boardInfo
- Publication number
- JPS63164397A JPS63164397A JP31075186A JP31075186A JPS63164397A JP S63164397 A JPS63164397 A JP S63164397A JP 31075186 A JP31075186 A JP 31075186A JP 31075186 A JP31075186 A JP 31075186A JP S63164397 A JPS63164397 A JP S63164397A
- Authority
- JP
- Japan
- Prior art keywords
- laminate
- multilayer printed
- solder resist
- circuit pattern
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims 1
- 238000003475 lamination Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層印刷配線板の製造方法に係り、特に予め最
外層に導体回路パターンを設けた外層基材の積層に好適
な多層印刷配線板の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer printed wiring board, and in particular, a multilayer printed wiring board suitable for laminating an outer layer base material in which a conductor circuit pattern is provided on the outermost layer in advance. Relating to a manufacturing method.
従来の多層印刷配線板の一般的な製造方法を第3図に示
す、これは予め導体回路パターン1を絶縁層2の両面に
形成した一対の積層板3を最外層に配し、その内側に予
め導体回路パターンを絶縁層5の両面に形成した内層の
積層板6と、プリプレグ7の層を介挿して積層構成とし
た後、その上下を直接積層金型8を用いて加熱加圧して
一体化成型するものである。しかし、これには積層時の
圧力が最外層の導体回路パターン1に集中し、第4図に
積層後の多層化基板30として示すように。A general manufacturing method for a conventional multilayer printed wiring board is shown in FIG. After interposing the inner layer laminate 6 with conductor circuit patterns formed on both sides of the insulating layer 5 in advance and a layer of prepreg 7 to form a laminate structure, the upper and lower parts are directly heated and pressed using a laminate mold 8 to be integrated. It is chemically molded. However, the pressure during lamination is concentrated on the outermost conductive circuit pattern 1, as shown in FIG. 4 as a multilayered substrate 30 after lamination.
積層板3を導体回路パターン1の厚さ分だけ波釘たせて
しまうという欠陥があった。There was a defect in that the laminate 3 was corrugated by the thickness of the conductive circuit pattern 1.
この対策としては、例えば特開昭60−241295号
公報に記載のように、被積層体の上下に。As a countermeasure against this, for example, as described in Japanese Patent Application Laid-open No. 60-241295, the upper and lower portions of the laminated body.
耐熱性ゴムシートを離型性フィルムに介挿した状態で配
置し、加熱加圧して一体化成型した後、耐熱性ゴムシー
トを離型性フィルムを除去する方法がある。There is a method in which a heat-resistant rubber sheet is inserted into a releasable film, and the heat-resistant rubber sheet is integrally molded by heating and pressurizing, and then the releasable film is removed from the heat-resistant rubber sheet.
前記耐熱性ゴムシートを介挿した離型性フィルムを使用
する方法は、接着前処理の不要な外層面まで処理(ソフ
トエツチング、酸化膜形成等)されるため、処理液を無
駄に消費してしまい液寿命を縮める問題がある。また、
離型性フィルム、耐熱性ゴムシートともに消耗品であり
、かつ、接着前後の介挿、除去という無駄な作業によっ
てコスト高を招く問題もある。In the method of using a releasable film with a heat-resistant rubber sheet interposed therein, the outer layer surface that does not require pre-adhesion treatment is processed (soft etching, oxide film formation, etc.), which wastes processing liquid. There is a problem of shortening the life of the sump liquid. Also,
Both the release film and the heat-resistant rubber sheet are consumables, and there is also the problem of increased costs due to the wasteful work of inserting and removing them before and after adhesion.
本発明は被積層体最外層の導体回路パターン上に予めソ
ルダーレジストを塗布し、該ソルダーレジスト塗布面を
外側に向けて配置して加熱加圧することを特徴とする。The present invention is characterized in that a solder resist is applied in advance on the conductor circuit pattern of the outermost layer of the laminated body, and the solder resist coated surface is placed facing outward and heated and pressurized.
予めソルダーレジストを被積層体最外層の導体回路パタ
ーン上に塗布することにより、接着前処理の必要な内層
面のみ処理されるため、処理液の無駄な消費がなくなり
寿命が延びる。また、直接積層プレス機を用いて被積層
体を加熱加圧して一体化しても、圧力が被積層体全面に
均等に伝わる。By applying a solder resist in advance on the conductor circuit pattern of the outermost layer of the laminated body, only the inner layer surface that requires pre-adhesion treatment is treated, thereby eliminating wasteful consumption of treatment liquid and extending the life. Further, even if the laminated bodies are integrated by heating and pressurizing them using a direct lamination press machine, the pressure is evenly transmitted to the entire surface of the laminated bodies.
これによって、最外層の積層板が波打つことを解消でき
るとへもに、耐熱性ゴムシートを離型性フィルムに介挿
したり除去する手間を省くことができる。This makes it possible to prevent the outermost layer of the laminate from waving, and also to save the effort of inserting and removing the heat-resistant rubber sheet from the release film.
(実施例〕
以下1本発明の一実施例を第1図及び第2図を参照して
説明する。(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
第1図は6層の印刷配線板の積層構成を示す断面図であ
る。まず、各絶縁層2および5の両面に導体回路パター
ン1および4を形成して積層板3゜6とした後、一対の
積層板3の外層面にスクリーン印刷法によりソルダーレ
ジスト9を塗布し乾燥させる1次に、積層板3および6
にソフトエツチング、酸化膜形成等の接着前処理を施す
、この場合、前処理が不要な外層面にはソルダーレジス
ト9が塗布されているため、内層パターンのみが処理さ
れる0次いで、すでに導体回路パターン4を形成した積
層板6を中央に、ソルダーレジスト9を塗布した一対の
積層板3を、ソルダーレジスト塗布面を外側に向けて配
置する。この状態で積層プレス機を用いて、直接、積層
全型8により加熱加圧し一体化成形する。FIG. 1 is a sectional view showing the laminated structure of a six-layer printed wiring board. First, conductor circuit patterns 1 and 4 are formed on both sides of each insulating layer 2 and 5 to form a laminate 3°6, and then solder resist 9 is applied to the outer layer surfaces of the pair of laminates 3 by screen printing and dried. First, laminates 3 and 6
In this case, since the solder resist 9 is applied to the outer layer surface which does not require pre-treatment, only the inner layer pattern is processed. A pair of laminate plates 3 coated with solder resist 9 are arranged with the laminate plate 6 on which the pattern 4 is formed in the center, with the solder resist coated surfaces facing outward. In this state, using a laminating press machine, the whole laminated mold 8 is heated and pressurized directly to integrally mold.
第2図は、積層後の多層化基板の断面図を示したもので
、多層印刷配線板20は、第4図に示した多層印刷配線
板30のような波打ち状態を解消することができ、最外
層の積層板3は平均に成型することができる。FIG. 2 shows a cross-sectional view of the multilayered board after lamination, and the multilayer printed wiring board 20 can eliminate the wavy state like the multilayer printed wiring board 30 shown in FIG. The outermost layer laminate 3 can be formed evenly.
(発明の効果)
以上の説明から明らかなように1本発明によれば、被積
層体最外層の導体回路パターン上に予めソルダーレジス
トを塗布することにより、ソフトエツチング、酸化膜形
成等の接着前処理は、それが必要な内層面のみ施こされ
るため、不必要な処理液の消費がなくなり、かつ、最外
層の積層板は平坦に成型することができる。(Effects of the Invention) As is clear from the above description, according to the present invention, by applying a solder resist in advance on the conductor circuit pattern of the outermost layer of the laminated body, it is possible to perform soft etching, oxide film formation, etc. before adhesion. Since the treatment is applied only to the necessary inner layer surfaces, unnecessary consumption of treatment liquid is eliminated, and the outermost layer of the laminate can be formed flat.
第1図は本発明による多層印刷配線板の積層構成を示す
断面図、第2図は第1図の積層後の多層化基板の断面図
、第3図は従来の多層印刷配線板の積層構成を示す断面
図、第4図は第3図の積層後の多層化基板の断面図であ
る。
1.4・・・導体回路パターン、 2,5・・・絶縁層
、3.6・・・積層板、 7・・・プリプレグ、8・・
・積層金型、 9・・・ソルダーレジスト。
第 1 図
第2図
9 yn−デーレジれストFIG. 1 is a cross-sectional view showing the laminated structure of the multilayer printed wiring board according to the present invention, FIG. 2 is a cross-sectional view of the multilayered board after lamination shown in FIG. 1, and FIG. 3 is the laminated structure of the conventional multilayer printed wiring board. FIG. 4 is a cross-sectional view of the multilayered substrate shown in FIG. 3 after lamination. 1.4... Conductor circuit pattern, 2,5... Insulating layer, 3.6... Laminate board, 7... Prepreg, 8...
・Laminated mold, 9...Solder resist. Figure 1 Figure 2 Figure 9 yn-day resist
Claims (1)
た一対の積層板のそれぞれ片面導体回路パターン上にソ
ルダーレジストを塗布した後、該ソルダーレジスト塗布
面を外側に向けて最外層に配置し、その内側に予め導体
回路パターンを形成した積層板とプリプレグ層を1組以
上介挿して積層構成とし、該積層体を加熱加圧して一体
化することを特徴とする多層印刷配線板の製造方法。(1) After applying a solder resist on the conductor circuit pattern on each one side of a pair of laminates having a conductor circuit pattern formed on at least one side in advance, place the solder resist coated side facing outside as the outermost layer, and place the solder resist on the outermost layer, and 1. A method for manufacturing a multilayer printed wiring board, which comprises interposing one or more sets of a laminate and a prepreg layer on which a conductive circuit pattern has been formed in advance to form a laminate structure, and integrating the laminate by heating and pressing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31075186A JPH0632377B2 (en) | 1986-12-26 | 1986-12-26 | Method for manufacturing multilayer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31075186A JPH0632377B2 (en) | 1986-12-26 | 1986-12-26 | Method for manufacturing multilayer printed wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63164397A true JPS63164397A (en) | 1988-07-07 |
JPH0632377B2 JPH0632377B2 (en) | 1994-04-27 |
Family
ID=18009043
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31075186A Expired - Lifetime JPH0632377B2 (en) | 1986-12-26 | 1986-12-26 | Method for manufacturing multilayer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0632377B2 (en) |
-
1986
- 1986-12-26 JP JP31075186A patent/JPH0632377B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0632377B2 (en) | 1994-04-27 |
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