JPS63164310A - Formation of compound semiconductor multiplayered film - Google Patents

Formation of compound semiconductor multiplayered film

Info

Publication number
JPS63164310A
JPS63164310A JP31146986A JP31146986A JPS63164310A JP S63164310 A JPS63164310 A JP S63164310A JP 31146986 A JP31146986 A JP 31146986A JP 31146986 A JP31146986 A JP 31146986A JP S63164310 A JPS63164310 A JP S63164310A
Authority
JP
Japan
Prior art keywords
semiconductor layer
substrate
compound semiconductor
reaction furnace
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31146986A
Other languages
Japanese (ja)
Inventor
Kazuhisa Fujita
和久 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP31146986A priority Critical patent/JPS63164310A/en
Publication of JPS63164310A publication Critical patent/JPS63164310A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enhance the steepness in compositional change as well as to contrive accomplishment of sharp improvement in characteristics by a method wherein, after a non-doped semiconductor layer has been formed in the reaction furnace in which films are formed using an organic metal heat decomposition method, said semiconductor layer is once moved to outside the reaction furnace, dopants to be used for formation of conductive type are ion-implanted, and the mixture of the raw gas to be used for the semiconductor layer formed subsequently can be prevented. CONSTITUTION:A p-type GaAs substrate 3 is placed on the surface of a susceptor 2, and after a reaction furnace 1 has been evacuated, a susceptor 2 and the substrate 3 are heated up to the prescribed temperature using a coil 4 to be used for high frequency heating. Then, arsine and trimethylgallium are introduced into the reaction furnace 1 respectively using hydrogen gas as carrier gas, and a non-doped GaAs semiconductor layer is deposited on the surface of the substrate 3. Subsequently, the substrate 3 is once picked out from the reaction furnace 1, and an ion-implanting operation is performed in the furnace to be used for other ion-implantation. The substrate 3 is brought back to the reaction furnace 1 again, and first, an annealing treatment is performed. After the annealing treatment is finished and the temperature of the substrate 3 has been dropped to the prescribed temperature, a p-type GaAlAs semiconductor layer 23 is grown. Through these procedures, the n-type semiconductor layer and the like of high steepness such as the current constriction layer and the like effectively used in a semiconductor layer can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は有機金属を原料としてGaAs等の基板上にG
aA I As等の化合物半導体層を気相成長させる化
合物半導体多層膜の形成方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is a method for producing G on a substrate such as GaAs using an organic metal as a raw material.
The present invention relates to a method for forming a compound semiconductor multilayer film in which a compound semiconductor layer such as aA I As is grown in a vapor phase.

〔従来技術〕[Prior art]

GaAs又はInP等の基板上に有機金属を原料として
エピタキシャル成長法によりGaA I As、GaA
 I AsP+InGaAsP等の化合物半導体層を形
成する有機金属熱分解法(MOCVIl法: Meta
l  Organic  ChemicalVapor
  旦eposition法)は膜厚の均一性、Ijl
厚の制御性、量産化の容易性等の優れた特性を有するこ
とからその実用化が研究されている。
GaA I As, GaA is grown on a substrate such as GaAs or InP by epitaxial growth using an organic metal as a raw material.
I Organometallic thermal decomposition method (MOCVI method: Meta
l Organic Chemical Vapor
The uniformity of film thickness, Ijl
Its practical application is being studied because it has excellent properties such as thickness controllability and ease of mass production.

第4図は従来のMOCVD法による化合物半導体多層膜
の形成態様を示す模式図であり、反応炉lの周囲に配設
した高周波加熱用のコイル4にて反応炉1内に配したサ
セプタ2上の基板3を所定温度に加熱しつつ、反応炉l
の一端に接続した供給管5カミら原料ガスを供給すると
共に、排気ポンプ6aを駆動して、反応炉1の他端に接
続した排気管6から排気を行い、反応炉1内で原料ガス
を白抜矢符方向に通流させ、基板30表面を通流する過
程で基板3の表面にGaAs等の化合物半導体層を気相
エピタキシャル成長させるようになっている。
FIG. 4 is a schematic diagram showing how a compound semiconductor multilayer film is formed by the conventional MOCVD method. While heating the substrate 3 to a predetermined temperature, the reactor l is heated.
The raw material gas is supplied through the supply pipe 5 connected to one end of the reactor 1, and the exhaust pump 6a is driven to exhaust the raw material gas from the exhaust pipe 6 connected to the other end of the reactor 1. A compound semiconductor layer such as GaAs is grown on the surface of the substrate 3 by vapor phase epitaxial growth in the process of flowing the current in the direction of the white arrow.

このような設備によって、例えば導電型がp型のGaA
s基板上にn型のGaAs半導体層、p型GaA IA
s層を積層形成してなる化合物半導体多層膜を形成する
場合、先ず水素をキャリアガスとしてアルシン(A31
3 )と、n型のドーパントであるH2Sと、水素をキ
ャリアガスとしてトリメチルガリウム(TMG )を反
応炉1内に導入してn型GaAs層を所要厚さに形成し
た後、アルシン及びp型のドーパントであるジメチル亜
鉛(DMZ )及びトリメチルアルミニウム(TMA 
)を反応炉l内に導入しp型のGaA I Asを成長
せしめて形成されている。
With such equipment, for example, GaA of p-type conductivity can be
n-type GaAs semiconductor layer, p-type GaA IA on s substrate
When forming a compound semiconductor multilayer film formed by laminating S layers, first, arsine (A31
3), H2S, which is an n-type dopant, and trimethylgallium (TMG) using hydrogen as a carrier gas are introduced into the reactor 1 to form an n-type GaAs layer to the required thickness. Dopants dimethylzinc (DMZ) and trimethylaluminum (TMA)
) is introduced into a reactor l and p-type GaAIAs is grown.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところでこのような従来のMOCVD法による化合物半
導体多層膜の形成方法ではガス状有機金属を熱分解する
ことによって化合物半導体層を成長させる構成となって
いるために、成長が熱平衡状態に支配され、原料ガスの
成分比、温度等の諸条件を基板全面にわたって均一にす
葛必要があり、特に成長初期、或いは例えばGaAs膜
上にGaA I AsN費を成長させる場合等における
切り換え時にコントローラ等の応答が遅いため原料ガス
成分の混合が避けられず、成分の急峻性が不十分となり
、製品特性に影響を及ぼすことが生じる等の問題があっ
た。
By the way, in the conventional MOCVD method for forming a compound semiconductor multilayer film, the compound semiconductor layer is grown by thermally decomposing a gaseous organic metal, so the growth is governed by a thermal equilibrium state, and the raw material It is necessary to make various conditions such as gas component ratio and temperature uniform over the entire surface of the substrate, and the response of the controller etc. is slow especially at the initial stage of growth or when switching, such as when growing a GaAsN film on a GaAs film. Therefore, mixing of the raw material gas components is unavoidable, resulting in insufficient steepness of the components, resulting in problems such as affecting product characteristics.

第5図は従来方法によって製造した化合物半導体多層膜
における各層のキャリア濃度プロファイルを示すグラフ
であって、横軸に層表面から深さ方向各部の寸法(μm
)を、また縦軸にはキャリア濃度(am −3”)をと
って示しである。このグラフから明らかなようにn型G
aAs層上に形成したp型GaA j! As層内には
n型GaAsのキャリアが混入していることが解る。
FIG. 5 is a graph showing the carrier concentration profile of each layer in a compound semiconductor multilayer film manufactured by a conventional method, and the horizontal axis shows the dimensions (μm) of each part in the depth direction from the layer surface.
), and the vertical axis shows the carrier concentration (am −3”).As is clear from this graph, the n-type G
p-type GaA j! formed on the aAs layer. It can be seen that n-type GaAs carriers are mixed in the As layer.

本発明はかかる事情に鑑みなされたものであって、その
目的とするところは相隣した状態で積層形成される層相
互の間におけるキャリアの急峻性を格段に高め得るよう
にした化合物半導体多層膜の形成方法を提供するにある
The present invention has been made in view of the above circumstances, and its object is to provide a compound semiconductor multilayer film that can significantly increase the steepness of carriers between layers formed in a stacked state next to each other. To provide a method for forming.

〔問題点を解決するための手段〕[Means for solving problems]

本発明方法にあっては有機金属熱分解法により成1欠を
行う反応炉内でノンドープの半導体層を形成した後、こ
れを一旦その反応炉外に移して、導電型形成のためのド
ーパントをイオン注入する。
In the method of the present invention, a non-doped semiconductor layer is formed in a reactor in which formation/destruction is carried out by an organometallic thermal decomposition method, and then this is temporarily transferred outside the reactor to add a dopant for forming a conductivity type. Implant ions.

〔作用〕[Effect]

本発明方法によってはこれによって反応炉内には先に形
成した半導体層に対するキャリアが存在せず、その後に
形成する半導体層の原料ガスとの′混合が生じず、成分
変化の急峻性を高め得る。
Depending on the method of the present invention, there are no carriers for the previously formed semiconductor layer in the reactor, and mixing with the raw material gas for the subsequently formed semiconductor layer does not occur, which can increase the steepness of the composition change. .

〔実施例〕〔Example〕

以下本発明方法について図面に基づき具体的に説明する
。第1図は本発明方法の実施状態を示す模式図であり、
図中1は反応炉、2はサセプタ、3は基板、4は高周波
加熱用のコイル、5は原料ガスの供給管、6は排気管、
6aは排気ポンプを示している。
The method of the present invention will be specifically explained below based on the drawings. FIG. 1 is a schematic diagram showing the implementation state of the method of the present invention,
In the figure, 1 is a reactor, 2 is a susceptor, 3 is a substrate, 4 is a high-frequency heating coil, 5 is a raw material gas supply pipe, 6 is an exhaust pipe,
6a indicates an exhaust pump.

反応炉lは内部に基板3の載置用のサセプタ2を備え、
また外部にサセプタ2の配設位置に対向させて、サセプ
タ2、基板3を加熱する高周波加熱用のコイル4が配設
され、更に一端部には原料ガスの供給管5が、また他端
部には排気ポンプ6aに連なる排気管6が夫々接続され
ている。
The reactor l is equipped with a susceptor 2 for placing a substrate 3 therein,
Further, a high-frequency heating coil 4 for heating the susceptor 2 and the substrate 3 is disposed outside facing the location of the susceptor 2, and furthermore, a source gas supply pipe 5 is provided at one end, and a source gas supply pipe 5 is provided at the other end. An exhaust pipe 6 connected to an exhaust pump 6a is connected to each of the exhaust pipes 6.

供給管5には流量コントローy 10a、 10b、1
0c・・・10gを夫々備えた管路11a、 llb・
・・l1gが夫々接続されている。管路11aの一端は
硫化水素(H2S )源に接続され、また管路11bの
一端はアルシン(Ad3)源に接続され、更に管路11
c〜l1gの一端はいずれも水素ガス(H2)源に接続
されている。
The supply pipe 5 has flow rate controllers 10a, 10b, 1
Pipe lines 11a, llb, each equipped with 0c...10g.
...l1g are connected respectively. One end of line 11a is connected to a source of hydrogen sulfide (H2S), one end of line 11b is connected to a source of arsine (Ad3), and one end of line 11b is connected to a source of arsine (Ad3).
One ends of c to l1g are all connected to a hydrogen gas (H2) source.

一方管路11a、 llb、 llcの(i端は相互に
合流せしめた状態で、また管路lidの他端は後述する
バプラ7.8.9の管路7a、8a、9aと合流させた
状態で、更に管路lie〜11.の他端はバプラ7.8
.9を介して管路lidの他端と合流させた状態で夫々
供給管5に接続されている。
On the other hand, the i ends of the pipes 11a, llb, and llc are in a state where they are merged with each other, and the other end of the pipe lid is in a state where they are joined with the pipes 7a, 8a, and 9a of the bubbler 7.8.9, which will be described later. Then, the other end of the pipe lie ~ 11. is a bubbler 7.8
.. They are respectively connected to the supply pipes 5 via pipes 9 in a state where they merge with the other end of the pipe lid.

パブラフには有機化合物として例えばトリメチルガリウ
ム(TMG )が、またバブラ8にはトリメチルアルミ
ニウムが、更にバブラ9にはジメチル亜鉛が夫々収容さ
れており、水素ガスをキャリアガスとして選択的に反応
炉1に供給されるようになっている。
The bubbler contains an organic compound such as trimethyl gallium (TMG), the bubbler 8 contains trimethyl aluminum, and the bubbler 9 contains dimethyl zinc. Hydrogen gas is used as a carrier gas to selectively enter the reactor 1. It is now being supplied.

次に上述した如き設備によって第2図に示す如く導電型
がp型のGaAs基板(Znトド−M: I XIO’
C1m−’) 21上に導電型がn型のGaAs半導体
層22を厚さ0.6μm1更にその上にp型のGaA 
I As半導体層23を厚さ0.2μmをこの順序に積
層形成した半導体装置をMOCVD法により製造する過
程について説明する。
Next, as shown in FIG. 2, a GaAs substrate (Zn TODO-M: I
C1m-') 21, a GaAs semiconductor layer 22 of n-type conductivity is formed with a thickness of 0.6 μm1, and a p-type GaAs
A process of manufacturing a semiconductor device in which IAs semiconductor layers 23 having a thickness of 0.2 μm are laminated in this order using the MOCVD method will be described.

先ずp型GaAs製の基板3をサセプタ2の表面に載置
し、排気ポンプ6a、排気管6を介して反応炉1から排
気した後、高周波加熱用のコイル4にてサセプタ2、基
板3を所定の温度に加熱する。
First, a p-type GaAs substrate 3 is placed on the surface of the susceptor 2, and after evacuating the reactor 1 through the exhaust pump 6a and exhaust pipe 6, the susceptor 2 and substrate 3 are heated using a high-frequency heating coil 4. Heat to the specified temperature.

次いで流量コントローラ10cにて制御された水素ガス
をキャリアガスとして流量コントローラ10bにて制御
されたアルシン及び流量コントローラ10eで制御され
た水素ガスをキャリアガスとしてバブラ7からトリメチ
ルガリウムを夫々反応炉1内に導入し、また同時に希釈
のために流量コントローラ10dにて制御された水素ガ
スを導入して基板3の表面にノンドープのGaAs半導
体層を堆積せしめる。所要厚さにノンドープのGaAs
半導体層を形成した後は各流量コントローラを閉じ、基
板3を反応炉1から一旦取り出し、他のイオン注入用の
炉内でイオン注入を行う。
Next, trimethylgallium is introduced into the reactor 1 from the bubbler 7 using hydrogen gas controlled by the flow rate controller 10c as a carrier gas and arsine controlled by the flow rate controller 10b and hydrogen gas controlled by the flow rate controller 10e as carrier gases. At the same time, a non-doped GaAs semiconductor layer is deposited on the surface of the substrate 3 by introducing hydrogen gas controlled by a flow rate controller 10d for dilution. Undoped GaAs to the required thickness
After forming the semiconductor layer, each flow controller is closed, the substrate 3 is temporarily taken out from the reactor 1, and ions are implanted in another ion implantation furnace.

イオン注入工程はn型ドーパントとして、例えば54を
用い、これを200keVのパワーのもとで2×lQ’
csi−’の割合で注入することにより行われる。
In the ion implantation process, 54, for example, is used as an n-type dopant, and it is irradiated with 2×lQ' under a power of 200 keV.
This is done by injecting at the rate of csi-'.

注入中は例えばイオン電流を検出しながら所定値に達し
たとき注入を終了する。再び基板3を反応炉lに戻し、
先ずアニール処理の工程を行う。アニール処理の条件は
、例えばアルシン雰囲気下で基板3をコイル4による高
周波加熱により800℃に30分加熱保持することによ
って行われる。アニール処理の終了後は基板3の温度が
所定温度にまで低下するのをまってp型GaA I A
s半導体層23の成長を行う。
During the implantation, for example, the ion current is detected and the implantation is terminated when the ion current reaches a predetermined value. Return the substrate 3 to the reactor l again,
First, an annealing process is performed. The conditions for the annealing treatment are, for example, such that the substrate 3 is heated and held at 800° C. for 30 minutes by high-frequency heating by the coil 4 in an arsine atmosphere. After the annealing process is completed, wait until the temperature of the substrate 3 drops to a predetermined temperature, and then heat the p-type GaA IA.
s semiconductor layer 23 is grown.

先ず流量コントローラ10bにて制御されたアルシンと
、流量コントローラ10f 、 Logにて制御された
水素をキャリアガスとしてバブラ8からトリメチルアル
ミニウムを、バブラ7からp型ドーパントであるジメチ
ル亜鉛を夫々反応炉1内に導入する。これによって、n
型GaAs半導体層23上にp型GaA I As半導
体層23が形成される。
First, arsine controlled by the flow rate controller 10b and hydrogen controlled by the flow rate controller 10f and Log are used as carrier gases, and trimethylaluminum is introduced from the bubbler 8, and dimethylzinc, which is a p-type dopant, is introduced into the reactor 1 from the bubbler 7. to be introduced. By this, n
A p-type GaA I As semiconductor layer 23 is formed on the GaAs-type semiconductor layer 23 .

このようにして製造した化合物半導体装置におけるキャ
リア濃度プロファイルは第3図に示す如(である。第3
図は横軸に表面から深さ方向各部までの寸法(μm)を
、また縦軸にキャリア濃度(C11−”)をとって示し
である。
The carrier concentration profile in the compound semiconductor device manufactured in this way is as shown in FIG.
In the figure, the horizontal axis represents the dimension (μm) from the surface to each part in the depth direction, and the vertical axis represents the carrier concentration (C11-'').

このグラフから明らかなようにn型GaAs半導体層と
p型GaA 1^S半導体層との界面におけるn型Ga
As半導体層のキャリア濃度は零となっており、その急
峻性は極めて良好であることが解る。
As is clear from this graph, the n-type Ga at the interface between the n-type GaAs semiconductor layer and the p-type GaA 1^S semiconductor layer
It can be seen that the carrier concentration of the As semiconductor layer is zero, and its steepness is extremely good.

このような急峻性の高いn型半導体層等は例えば半導体
レーザにおける電流狭窄層等として有効である。
Such a highly steep n-type semiconductor layer is effective as, for example, a current confinement layer in a semiconductor laser.

〔効果〕〔effect〕

以上の如(本発明方法に依る場合は相隣する眉間での界
面における成分の急峻性が高く、各種半導体装置の製造
に適用して特性の大幅な向上を図れる優れた効果を奏す
るものである。
As described above (in the case of the method of the present invention, the steepness of the components at the interface between adjacent eyebrows is high, and it has an excellent effect that can be applied to the manufacture of various semiconductor devices to significantly improve the characteristics. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方法の実施状態を示す模式図、第2図は
本発明方法により製造した半導体装置の断面構造図、第
3図は第2図に示す如き半導体装置におけるキャリア濃
度のプロファイル、第4図は従来方法に依る実施状態を
示す模式図、第5図は従来方法により製造した半導体装
置におけるキャリア濃度プロファイルである。
FIG. 1 is a schematic diagram showing the implementation state of the method of the present invention, FIG. 2 is a cross-sectional structural diagram of a semiconductor device manufactured by the method of the present invention, and FIG. 3 is a carrier concentration profile in the semiconductor device as shown in FIG. FIG. 4 is a schematic diagram showing an implementation state according to the conventional method, and FIG. 5 is a carrier concentration profile in a semiconductor device manufactured by the conventional method.

Claims (1)

【特許請求の範囲】 1、気相成長用の反応炉内で化合物半導体基板上に有機
金属熱分解法により複数の化合物半導体層を積層形成す
る過程において、前記反応炉内で化合物半導体層を形成
する工程と、前記反応炉外にて前記化合物半導体層に導
電型がp型又はn型のドーパントをイオン注入する工程
と、イオン注入後、前記反応炉内で半導体層にアニール
を施す工程とを含むことを特徴とする化合物半導体多層
膜の形成方法。 2、前記化合物半導体層は周期律表のIII−V族の化合
物である特許請求の範囲第1項記載の化合物半導体多層
膜の形成方法。 3、前記p型のドーパントはZn、Mg、Beである特
許請求の範囲第1項記載の化合物半導体多層膜の形成方
法。 4、前記n型のドーパントはSi、Te、Se、Sであ
る特許請求の範囲第1項記載の化合物半導体多層膜の形
成方法。 5、前記アニール工程は、前記反応炉内で原料ガス雰囲
気中で行われる特許請求の範囲第1項記載の化合物半導
体多層膜の形成方法。
[Claims] 1. In the process of stacking a plurality of compound semiconductor layers on a compound semiconductor substrate by an organometallic thermal decomposition method in a reactor for vapor phase growth, the compound semiconductor layer is formed in the reactor. a step of ion-implanting a dopant having a p-type or n-type conductivity into the compound semiconductor layer outside the reactor; and a step of annealing the semiconductor layer within the reactor after the ion implantation. A method for forming a compound semiconductor multilayer film, comprising: 2. The method for forming a compound semiconductor multilayer film according to claim 1, wherein the compound semiconductor layer is a compound of Group III-V of the periodic table. 3. The method for forming a compound semiconductor multilayer film according to claim 1, wherein the p-type dopant is Zn, Mg, or Be. 4. The method for forming a compound semiconductor multilayer film according to claim 1, wherein the n-type dopant is Si, Te, Se, or S. 5. The method for forming a compound semiconductor multilayer film according to claim 1, wherein the annealing step is performed in a source gas atmosphere in the reactor.
JP31146986A 1986-12-26 1986-12-26 Formation of compound semiconductor multiplayered film Pending JPS63164310A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31146986A JPS63164310A (en) 1986-12-26 1986-12-26 Formation of compound semiconductor multiplayered film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31146986A JPS63164310A (en) 1986-12-26 1986-12-26 Formation of compound semiconductor multiplayered film

Publications (1)

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JPS63164310A true JPS63164310A (en) 1988-07-07

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JP31146986A Pending JPS63164310A (en) 1986-12-26 1986-12-26 Formation of compound semiconductor multiplayered film

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63198317A (en) * 1987-02-13 1988-08-17 Nec Corp Forming method for p-n junction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63198317A (en) * 1987-02-13 1988-08-17 Nec Corp Forming method for p-n junction

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