JPS63164098A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To accelerate a sense action by providing a differential amplifier circuit which composes a sense amplifier with a switching element and a circuit element which works as a resistor means and respectively supplying an input signal and a reference voltage through this register means. CONSTITUTION:The sense amplifier SA is composed by an active load circuit consisting of a differential MOSFETQ 13 and Q 14, a power switch MOSFETQ 15, and P channel MOSFETQ 16 and Q 17. While the amplifier SA acts, the time which the input signal reaches the reference voltage can be substantially reduced zero by respectively supplying the input signal and the reference voltage through the register means consisting of the Q 16 and the Q 17. Therefore, the sense action can be accelerated. Unnecessary high voltage for a write action can be prevented to be supplied to the amplifier SA by switching transmission gates MOSFET 11 and 12, which transmit a read out signal and the reference voltage, to turn off the write action.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, for example, one that includes a sense amplifier that senses a read signal from a semiconductor memory element with reference to a reference voltage. It concerns techniques that can be effectively utilized.

[Conventional technology]

For example, EPROM (erasable programmable read only memory) devices that use semiconductor elements such as FAMO3 (floating avalanche injection MO3FET) as storage elements (memory cells) are known (for example, Japanese Patent Laid-Open No. 54-152933 (see publication). The FAMO3) transistor is made to have a high or low threshold voltage with respect to the selection level of the word line coupled to its gate by its write operation. That is, the stacked gate transistor is changed from a low threshold voltage to a high threshold voltage by writing.

[Problem that the invention seeks to solve]

The sensing operation of the read signal as described above is performed by a voltage comparison circuit that receives the read signal and a reference voltage. In this case, in a read operation in which the read signal changes from high level to low level or from low level to high level, relatively large Due to the presence of parasitic capacitance,
Changes in the read signal are slowed down. This hinders high-speed read operation (sense operation).

An object of the present invention is to provide a semiconductor integrated circuit device including a sense amplifier that operates at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the differential amplifier circuit constituting the sense amplifier is provided with a switch element that short-circuits a pair of inputs during its non-operating period, and is also provided with a circuit element that acts as a resistance means on the pair of inputs at least during its operating period. ,
An input signal and a reference voltage are respectively supplied through this resistance means.

[For production]

According to the above-mentioned means, since the pair of inputs of the differential amplifier circuit are temporarily short-circuited during the non-operating period by the switching element, the time required for the input signal to reach the reference voltage can be substantially reduced to zero. I can do it.

〔Example〕

FIG. 1 shows a circuit diagram of a main part of an embodiment in which the present invention is applied to an EPROM device.

Although not particularly limited, each circuit element in the figure may be a known CM.
With O3 (complementary MO3) integrated circuit manufacturing technology, 1
formed on a semiconductor substrate such as single crystal silicon. In the same figure, P channel MOS FET
is distinguished from an N-channel MOSFET by adding an arrow to its channel portion. In the following description, unless otherwise specified, the MOSFET is an N-channel MOSFET.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET consists of a source region, a drain region, and a polysilicon film formed on the semiconductor substrate surface between the large region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode like this. The P-channel MOS FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes a substrate cage for the P-channel MOS FET formed thereon. The substrate gate or N-type well region of the P-channel MO3FET is coupled to the power supply terminal Vcc of FIG.

Although not particularly limited, the EPROM device of this embodiment includes:
X supplied from an external terminal (not shown).

A complementary address signal formed through an address buffer receiving Y address signals AX and AY is supplied to an address decoder DCR. In the figure, the address buffer and address decoder are in the same circuit block XADB-DCR.
2YADB-DcR, respectively. Although not particularly limited, the above address buffers XADB, YA
DB is activated by an internal chip selection signal ce, takes in an address signal from an external terminal, and forms a complementary address signal consisting of an internal address signal in phase with the address signal supplied from the external terminal and an address signal in opposite phase. do.

Address decoder DCR(X) forms a selection signal for word line W of memory array M-ARY according to its complementary address signal.

Address decoder DCR(Y) forms a selection signal for the data line of memory array M-ARY according to its complementary address signal.

The memory array M-ARY includes a plurality of representative memory elements Ql-06 and word lines Wl, W2.
and data &*Dl to Dn. The memory elements Q1 to Q6 are MOSFETs having a control gate and a floating gate, and charge is injected into the floating gate to store information in the form of charge (hereinafter, the memory elements Q1 to Q6 are referred to as stacked gate transistors). ). Memory array M-ARY
, the control gates of the stacked gate transistors Ql to Q3 (Q4 to Q6) arranged in the same row are connected to the corresponding word line Wl (W2), respectively, and the stacked gate transistors Ql, Q3 arranged in the same column are connected to the corresponding word line Wl (W2), respectively. The drains of Q4 to Q3 and Q6 are connected to corresponding data lines D1 to Dn, respectively. The common source line C8 of the stacked gate transistors is grounded via a depressing type MO3FET QIO that receives the write signal we, although this is not particularly limited.

The conductance of this MO3FET QIO is made relatively small by the low level of the internal control signal we during writing. As a result, the potential of the common source line CS is made relatively high by making the conductance of MO3FETQ10 relatively small. When the potential of this common source gIIsC3 is made relatively high, the threshold voltage of the stacked gate transistor is made relatively high. Therefore, by supplying a high write voltage to the data line and making the word line non-selected, the effective threshold voltage of the non-selected stacked gate transistor is increased, reducing the leakage current flowing thereto. can. Thereby, the write current supplied from the external terminal is efficiently supplied to the selected stacked gate transistor, so that an efficient write operation can be performed. Note that during the read operation, the high level of the control signal we causes the MOS FETQ to
The conductance of the IO is made relatively large.

This increases the read speed.

Each of the data lines D1 to Dn is connected to the address decoder O.
Through column selection switches MO3FETQ7 to Q9 that receive the selection signal formed by CR(Y),
Connected to common data line CD. Each of the 0 or more MOS FETs to which the output terminal of the write data input circuit DIB that receives the write signal input from the external terminal I10 is connected to the common data line CD is an N-channel MO5F.
It is composed of ET.

In this embodiment, the following sense amplifier SA is used to speed up the read operation, in other words, to speed up the sensing operation of the information stored in the stacked gate transistor.

Sense amplifier SA consists of differential MO3FETs Q13 and Q14.
, a power switch MOSFBTQ15 provided between the common source of these MO3FBTQ13 and Q14 and the ground potential point of the circuit, and the MOSFETQ13. Q1
The active load circuit consists of P-channel MO5FETs Q16 and Q17 arranged in a current mirror configuration.

At the gate of the power switch MO3FETQ15,
A sense amplifier operation timing signal SaC is supplied. The read signal from the common data line CD is supplied to the gate of one differential MO3FET Q13 via a transmission gate MO3FET QI1 which receives a timing signal sas. Further, the reference voltage Vr generated by a reference voltage generation circuit (not shown) is applied to the other differential MO3F via the transmission gate MO3FETQ12 which receives the control signal saa.
Supplied to the gate of ETQ14. These differential MO5F
An inverted timing signal sac of the timing signal sac is supplied between the gates of ETQI 3 and Q14, so that the power switch MO3FETQ15
The switch MO5FETQ1 is turned on complementary to
8 is provided.

That is, this switch MO3FETQI8 is turned on during the non-operation period of the sense amplifier SA. Above transmission gate MOSFET QII and Q12
acts as a resistance means when the switch MOS FETQ18 is on, and the differential MO3FETQ
I 4 (7) The gate voltage Vr° and the gate voltage of the differential MO3FETQ13 to which the input signal is supplied are mutually changed so that they become the same potential.

Further, a capacitor C is provided at the gate of the differential MO3FET QI4. As a result, the above MO3F
The voltage Vr' supplied to the gate of the MO3FETQI 4 remains unchanged even if the sense amplifier SA starts operating due to the high level of the timing signal SaC.
According to the time constant of the capacitor C and the capacitor C, the potential changes relatively smoothly to the reference voltage Vr.

Although not shown, the reference voltage generation circuit includes, for example, a dummy stacked gate transistor connected in series, a dummy MO corresponding to a column switch MO3FET, etc.
It consists of 3FET and suitable means. Above dummy M
The OS FETs each consist of a stacked gate transistor of the same size as the stacked gate transistor Q1 etc. that constitutes the memory cell, and are made to have a relatively low threshold voltage by not being written to. . By connecting the two dummy MO3FETs in series, the combined conductance thereof is made to have approximately half the conductance of the stacked gate transistor that is not written. Thereby, it is possible to form a reference voltage necessary for a read operation of the stacked gate transistor, which has a relatively low threshold voltage or a relatively high threshold voltage depending on the presence or absence of writing. The dummy MOS FET for forming the reference voltage Vr may be provided corresponding to each word line of the memory array M-ARY. In this case, the gate of the dummy MO3FET is connected to the corresponding word line. is combined with And dummy M
The drain of O3FET is coupled to a dummy data line, and this dummy data line is connected to the dummy column switch MO3F.
By providing ET, a series circuit similar to the above can be configured to form the reference voltage Vr.

A timing signal 3as generated prior to the sense amplifier operation timing signal sac is supplied to the gates of the transmission gates MO3FETQI1 and Q12.

That is, the timing signal asa is set to a high level immediately upon entering the read mode. This is mainly because a high voltage for writing is supplied to the common data line CD during writing, so the MOS F
ETQll is turned off and disconnected from the common data line CD of the sense amplifier during a write operation to prevent undesired high voltage from being supplied to the input of the sense amplifier SA. Therefore, if another switch MOS FET is provided to prevent the supply of the write high voltage, the M
The power supply voltage Vcc may be constantly supplied to the gates of the O3FETs QI1 and Q12 to simply operate as a resistance means.

The output signal of this sense amplifier SA is the data output circuit D.
It is sent from the external terminal I10 via OB. Although not shown, the data output circuit DOB has a built-in flip-flop circuit for receiving the output from the sense amplifier SA and storing the information signal. As a result, the sense amplifier SA is activated only when reading information from the memory, and after storing the information in the flip-flop circuit,
It becomes possible to inactivate the sense amplifier SA and reduce power consumption.

The control circuit C0NT connects external terminals GE, OB, PG
Chip enable signal provided to M and vpp.

An internal control signal ce is generated in response to an output enable signal, a program signal, a high voltage for writing, and an output signal φ from a pulse generation circuit PG, which will be described later.

Timing signals such as we, sas, sac, and sac, as well as read low voltage Vcc/write layer high voltage vpp, etc., which are selectively supplied to the address decoder are formed.

An example of the operation of this embodiment circuit will be explained with reference to the timing diagrams shown in FIGS. 2 and 3.

As shown in FIG. 2, if the chip enable signal CE is at a low level, the output enable signal 0E is at a low level, and the program signal PGM is at a high level, the read mode is set and the internal signals we and ce are set at a high level. . In such a read mode, address decoder circuits XDCR, YDCR and data input circuit D
A power supply voltage Vcc is supplied to the high voltage circuit of IB.

As a result, the selection level of the word line is set to the power supply voltage V
It is set to a relatively low level such as cc. If the threshold voltage of the selected stacked gate transistor is lower than the selection level of the word line, the selected stacked gate transistor is turned on; if it is higher than the selection level of the word line, the selected stacked gate transistor is turned on. In this case, the selected stacked gate transistor is turned off and read out.

When the read mode is determined, the timing signal SaS is immediately set to a high level. As a result, the transmission gate MO3FETs QI1 and Q12 are turned on, and the gates of the differential MO3FETs QI3 and Q14 are short-circuited. Therefore, as shown by the solid line in FIG. 3, if the potential Vs of the common data line CD is low level in the previous read operation, the shorting MO3FET
8 is raised to the reference potential Vr side. On the other hand, the gate voltage Vr' of the MO3FET QI 4 is lowered to the low level side in accordance with the low level of the voltage Vs, as shown by the dotted line in the figure, and the high voltages Vs and Vr' mutually change and become equal. Becomes electric potential.

Waiting for the word line selection operation, the operation timing signal SaC of the sense amplifier SA is set to high level. As a result, the short circuit MO5FETQI8 is switched from the on state to the off state, and the power switch MO3F
ETQI 5 turns on and differential amplifier MO3FE
An operating current necessary for the amplification operation is passed through TQI 3 and Q14. If the stacked gate transistor selected according to the word line selection operation is in an off state, its read signal is set to a high level. The high level of this read signal VS changes from the voltage determined by the short circuit operation to the high level. At the same time, the gate voltage Vr' of MO3FETQ14 also changes to a voltage according to the reference voltage Vr. However, the above capacitor C and MO3FE
Since TQI2 changes relatively slowly, at the same time as the sense amplifier SA starts operating, a minute read signal from the selected stacked gate transistor appears at the gates of both differential MO3FF': TQ13 and Q14. . Thereby, an amplified signal according to the read signal from the selected stacked gate transistor can be obtained from the output of the sense amplifier SA.

Note that if the selected read signal is at low level, the voltage Vs changes from the short circuit voltage to low level. By providing the short MO3FET Q1B and the transmission gates MO3FET QI 1 and Q12 as described above, the read operation of the low level to low level (or high level to high level) is delayed accordingly. However, it is not delayed by the inversion read time such as the above-mentioned high level/low level (or low level/high level), and there is no substantial problem.

The effects obtained from the above embodiments are as follows. That is, (1) a differential amplifier circuit constituting the sense amplifier is provided with a switch element that short-circuits a pair of inputs during its non-operation period, and a circuit element that acts as a resistance means on the pair of inputs at least during its operation period; By providing an input signal and supplying the reference voltage through this resistance means, the time required for the input signal to reach the reference voltage can be reduced to substantially zero, thereby increasing the speed of sensing operation. The effect is that it is possible to achieve the following.

(2) Transmission game that transmits the read signal and reference voltage) MO
By switching the SFET to turn off the write operation, it is possible to prevent an undesired write high voltage from being supplied to the sense amplifier.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the sense amplifier may be in the form of a latch in which its input and output are cross-connected. In this case, by turning off the transmission gate MO3FET QI 1 and C12 at the timing when the read signal necessary for the sensing operation is taken in, the load capacitance can be reduced, thereby achieving further speedup. It is something. The reference voltage of the sense amplifier may be anything, such as using a dummy MO3FET (stacked gate transistor) whose size is about half that of the stacked gate transistor constituting the memory cell.

Furthermore, in an EPROM device that writes/reads memory data consisting of multiple bits in parallel, by providing a plurality of memory arrays M-ARY shown in FIG. 1, sense amplifiers, data output buffer sofas, data input buffers, etc. Can be configured.

In the above explanation, the invention made by the inventor of the present application was mainly applied to an EPROM device, which is the technical field behind the invention, but the invention is not limited to this (EEFROM (Erasable & Electrical FROM)) It can also be used in various semiconductor memory circuits including sense amplifiers that use reference voltages, such as ROMs and mask ROMs, and these memory circuits are built into digital integrated circuits such as one-chip microcomputers. You can.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, in the differential amplifier circuit that constitutes the sense amplifier,
A switch element is provided to short-circuit the pair of inputs in the non-operating state, and a circuit element is provided that acts as a resistance means on the pair of inputs at least in the operating state, and the input signal and the reference voltage are connected via the resistance means. By supplying each of them, the time it takes for the input signal to reach the reference voltage can be made substantially zero, thereby increasing the speed of the sensing operation.

[Brief explanation of the drawing]

FIG. 1 is a main circuit diagram showing an embodiment of an EPROM device to which the present invention is applied, FIG. 2 is a timing diagram for explaining an example of its operation, and FIG. 3 is an example of its operation. FIG. 2 is a waveform diagram for explaining. XADB-DCR, YADI3-DCR...address buffer/address decoder, M-ARY...memory array, DIB...data input circuit, DOB...data output circuit, C0NT...control circuit, SA...sense amplifier. 7 v51 diagram

Claims (1)

[Claims] 1. A switch element that short-circuits a pair of input terminals during its non-operating period is provided, and at least during its operating period, an input signal is connected to the pair of input terminals via a circuit element that acts as a resistance means. 1. A semiconductor integrated circuit device comprising a sense amplifier comprising a differential amplifier circuit to which a reference voltage is respectively supplied. 2. The semiconductor integrated circuit device according to claim 1, wherein a capacitor means is added to the input terminal to which the reference voltage of the differential amplifier circuit is supplied. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the input signal is a read signal of a memory element constituting a semiconductor memory circuit.