JPS63163564U - - Google Patents

Info

Publication number
JPS63163564U
JPS63163564U JP11200287U JP11200287U JPS63163564U JP S63163564 U JPS63163564 U JP S63163564U JP 11200287 U JP11200287 U JP 11200287U JP 11200287 U JP11200287 U JP 11200287U JP S63163564 U JPS63163564 U JP S63163564U
Authority
JP
Japan
Prior art keywords
switch
voting
terminal
flip
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11200287U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11200287U priority Critical patent/JPS63163564U/ja
Publication of JPS63163564U publication Critical patent/JPS63163564U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例が適用された投票機
の全体を示すブロツク図、第2図は第1図の各部
の波形信号の一例を示すタイムチヤートである。 1……選出スイツチ、S1……投票用スイツチ
FIG. 1 is a block diagram showing the entire voting machine to which an embodiment of the present invention is applied, and FIG. 2 is a time chart showing an example of waveform signals of each part of FIG. 1. 1... Selection switch, S1... Voting switch.

Claims (1)

【実用新案登録請求の範囲】 (1) それぞれが、第1及び第2の固定接点およ
び常時は第1の固定接点側に接続される可動接点
からなる押ボタンスイツチ(手動操作自動復帰切
換スイツチ)で構成され、かつ1つの押ボタンス
イツチの第1の固定接点が隣接する押ボタンスイ
ツチの可動接点に接続されると共に、末端の押ボ
タンスイツチの可動接点が固定電位に接続されて
いる複数の投票用スイツチと、 第1ないし第3の入力端子を有し、前記各投票
用スイツチの第2の固定接点に生じた信号に基づ
く信号が、それぞれの第1の入力端子に供給され
る複数のアンド回路からなる選出信号発生回路と
、 その出力端子が前記各アンド回路の第2の入力
端子に接続されているフリツプフロツプと、 前記フリツプフロツプのセツト端子に接続され
ている確定用スイツチと、 予定の周波数で読出タイミングパルスを前記各
アンド回路の第3の入力端子に供給する読出タイ
ミングパルス発生回路と、 前記各アンド回路に対応して、それぞれのアン
ド回路の出力を計数するように設けられた複数の
カウンタとを具備したこと を特徴とする投票機用登算装置。 (2) 複数の投票用スイツチに対応して設けられ
、前記複数の投票用スイツチの各第2の固定接点
とそれらの各セツト端子が接続され、かつそれら
の各出力端子が選出信号発生回路を構成する各ア
ンド回路の第1の入力端子と接続されている複数
のフリツプフロツプを具備したことを特徴とする
前記実用新案登録請求の範囲第1項記載の投票機
用登算装置。 (3) 投票用スイツチのオン状態に応じて一旦全
てのフリツプフロツプがリセツトされることを特
徴とする前記実用新案登録請求の範囲第2項記載
の投票機用登算装置。
[Claims for Utility Model Registration] (1) A push button switch (manually operated automatic return changeover switch) each consisting of first and second fixed contacts and a movable contact that is normally connected to the first fixed contact side. and a first fixed contact of one pushbutton switch is connected to a movable contact of an adjacent pushbutton switch, and a movable contact of the terminal pushbutton switch is connected to a fixed potential. a voting switch, and a plurality of AND terminals having first to third input terminals, and a signal based on a signal generated at the second fixed contact of each voting switch is supplied to each first input terminal. a selection signal generation circuit consisting of a circuit; a flip-flop whose output terminal is connected to the second input terminal of each of the AND circuits; a confirmation switch connected to the set terminal of the flip-flop; a read timing pulse generation circuit that supplies a read timing pulse to a third input terminal of each of the AND circuits; and a plurality of counters that are provided to correspond to each of the AND circuits and count the outputs of the respective AND circuits. A registration device for a voting machine, characterized by comprising: (2) Provided corresponding to a plurality of voting switches, each second fixed contact of the plurality of voting switches is connected to each set terminal thereof, and each output terminal thereof is connected to a selection signal generation circuit. 2. The registration device for a voting machine according to claim 1, further comprising a plurality of flip-flops connected to the first input terminal of each AND circuit constituting the registration device. (3) The registration device for a voting machine as set forth in claim 2 of the utility model registration claim, wherein all flip-flops are reset once in response to the ON state of a voting switch.
JP11200287U 1987-07-23 1987-07-23 Pending JPS63163564U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11200287U JPS63163564U (en) 1987-07-23 1987-07-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11200287U JPS63163564U (en) 1987-07-23 1987-07-23

Publications (1)

Publication Number Publication Date
JPS63163564U true JPS63163564U (en) 1988-10-25

Family

ID=30992458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11200287U Pending JPS63163564U (en) 1987-07-23 1987-07-23

Country Status (1)

Country Link
JP (1) JPS63163564U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5652486A (en) * 1979-10-04 1981-05-11 Nippon Signal Co Ltd Election vote device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5652486A (en) * 1979-10-04 1981-05-11 Nippon Signal Co Ltd Election vote device

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