JPS6316282Y2 - - Google Patents

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Publication number
JPS6316282Y2
JPS6316282Y2 JP18573780U JP18573780U JPS6316282Y2 JP S6316282 Y2 JPS6316282 Y2 JP S6316282Y2 JP 18573780 U JP18573780 U JP 18573780U JP 18573780 U JP18573780 U JP 18573780U JP S6316282 Y2 JPS6316282 Y2 JP S6316282Y2
Authority
JP
Japan
Prior art keywords
ceramic dielectric
ceramic
elements
voltage
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18573780U
Other languages
Japanese (ja)
Other versions
JPS57108636U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18573780U priority Critical patent/JPS6316282Y2/ja
Publication of JPS57108636U publication Critical patent/JPS57108636U/ja
Application granted granted Critical
Publication of JPS6316282Y2 publication Critical patent/JPS6316282Y2/ja
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案はサージ吸収器の中でも電子機器の電源
線や信号線などから侵入する線間サージ〔誘導
雷,誘導性負荷の開閉など〕および電圧レベルは
低いが機器の誤動作の原因になり得る線間や線−
アース間のノイズを抑制するためのサージ吸収器
に関し、その目的とするところは小形でかつ単一
部品で提供することにある。
[Detailed description of the invention] This invention is a surge absorber that can handle line-to-line surges (induced lightning, switching of inductive loads, etc.) that enter from the power lines and signal lines of electronic equipment, and can cause equipment malfunctions even though the voltage level is low. Between lines and lines that can cause
Regarding a surge absorber for suppressing ground-to-ground noise, the objective is to provide it in a small size and in a single component.

従来、電子機器が線間および線−アース間のノ
イズで誤動作するのを防止するために、第1図に
示すような回路が、コンデンサ1数個を使つたり
又は単一部品として使用されている。また線間の
サージノイズ吸収用としては、第2図に示すよう
に酸化亜鉛バリスタ等の電圧依存性非直線抵抗素
子2にコンデンサ1を並列接続されて使用され
る。しかしこのようなものは取付スペース及び工
数等に問題があり、充分な効果を示していない場
合が多い。
Conventionally, in order to prevent electronic equipment from malfunctioning due to line-to-line and line-to-ground noise, a circuit like the one shown in Figure 1 has been used using a few capacitors or as a single component. There is. For absorbing surge noise between lines, a capacitor 1 is connected in parallel to a voltage-dependent nonlinear resistance element 2 such as a zinc oxide varistor, as shown in FIG. 2. However, such devices have problems with installation space and man-hours, and often do not have sufficient effects.

これに対して本考案は上記問題点を回避できる
ものであつて、以下本考案の実施例を第3図〜第
6図に基づいて説明する。
In contrast, the present invention can avoid the above-mentioned problems, and embodiments of the present invention will be described below with reference to FIGS. 3 to 6.

3,4,5は第1,第2,第3のセラミツク誘
電体素子で、第4図に示すように円板状で両端面
に電極6を有する。7は酸化亜鉛バリスタ素子
で、第1,第2,第3のセラミツク誘電体素子
3,4,5と同様に円板状で両端面に電極を有す
る。8,9,10は外部接続端子としての第1,
第2,第3のリード線である。第1,第2,第3
のセラミツク誘電体素子〔以下第1,第2,第3
のセラミツク素子と称す〕3,4,5と酸化亜鉛
バリスタ素子〔以下バリスタ素子と称す〕とは第
3図のように配設されてサージ吸収器を構成して
いる。
Reference numerals 3, 4, and 5 designate first, second, and third ceramic dielectric elements, each having a disk shape and having electrodes 6 on both end surfaces, as shown in FIG. Reference numeral 7 denotes a zinc oxide varistor element, which, like the first, second, and third ceramic dielectric elements 3, 4, and 5, has a disk shape and has electrodes on both end surfaces. 8, 9, 10 are the first external connection terminals,
These are the second and third lead wires. 1st, 2nd, 3rd
Ceramic dielectric element [hereinafter referred to as 1st, 2nd, 3rd]
The ceramic elements 3, 4, 5 and the zinc oxide varistor element (hereinafter referred to as varistor element) are arranged as shown in FIG. 3 to constitute a surge absorber.

先ず第1,第2,第3のセラミツク素子3,
4,5を並設し、バリスタ素子7を第1と第2の
セラミツク素子3,4の間に介装し、第1,第
2,第3のセラミツク素子3,4,5の電極面お
よびバリスタ素子7の電極面は、対向する隣接素
子の電極面が互いに接続され、バリスタ素子7の
第1のセラミツク素子3側の電極面と第1のセラ
ミツク素子3のバリスタ素子7側の電極面との接
続部と第3のセラミツク素子5の第2のセラミツ
ク素子4とは反対側の電極面とをリード線〔又は
リード板〕11によつて接続し、バリスタ素子7
の第2のセラミツク素子4側の電極面と第2のセ
ラミツク素子4のバリスタ素子7側の電極面との
接続部と第1のセラミツク素子3のバリスタ素子
7とは反対側の電極面とをリード線〔又はリード
板〕12によつて接続し、前記第1のリード線8
は第1のセラミツク素子3のバリスタ素子7とは
反対側の電極面に接続され、第2のリード線9は
第3のセラミツク素子5の第2のセラミツク素子
4とは反対側の電極面に接続され、残る第3のリ
ード線10は第2のセラミツク素子4と第3のセ
ラミツク素子5との接続部に接続されている。な
お第1,第2,第3のセラミツク素子3,4,5
の電極面およびバリスタ素子7の電極面の対向す
る隣接素子の電極面との接続は、リード線によつ
て接続するかあるいは各電極面にクリーム半田を
塗布して第1,第2,第3のセラミツク素子3,
4,5およびバリスタ素子7を第3図のように積
み重ねて各電極面が直接あるいは前記リード線1
1,12等を介して当接させることによつて接続
する。接続後は耐候性能を向上させるために樹脂
塗装が施こされる。
First, the first, second and third ceramic elements 3,
4 and 5 are arranged in parallel, and the varistor element 7 is interposed between the first and second ceramic elements 3, 4, and the electrode surfaces of the first, second, and third ceramic elements 3, 4, and The electrode surfaces of the varistor element 7 are such that the electrode surfaces of opposing adjacent elements are connected to each other, and the electrode surface of the varistor element 7 on the first ceramic element 3 side and the electrode surface of the first ceramic element 3 on the varistor element 7 side are connected to each other. and the electrode surface of the third ceramic element 5 on the opposite side from the second ceramic element 4 are connected by a lead wire [or lead plate] 11, and the varistor element 7
The connection portion between the electrode surface on the second ceramic element 4 side and the electrode surface on the varistor element 7 side of the second ceramic element 4 and the electrode surface on the opposite side from the varistor element 7 of the first ceramic element 3. Connected by a lead wire (or lead plate) 12, the first lead wire 8
is connected to the electrode surface of the first ceramic element 3 opposite to the varistor element 7, and the second lead wire 9 is connected to the electrode surface of the third ceramic element 5 opposite to the second ceramic element 4. The remaining third lead wire 10 is connected to the joint between the second ceramic element 4 and the third ceramic element 5. Note that the first, second, and third ceramic elements 3, 4, 5
The electrode surfaces of the varistor element 7 and the electrode surfaces of the opposing adjacent elements can be connected to the electrode surfaces of the opposing adjacent elements by connecting with lead wires or by applying cream solder to each electrode surface. ceramic element 3,
4, 5 and the varistor element 7 are stacked as shown in FIG.
1, 12, etc., and are connected by abutting each other. After connection, a resin coating is applied to improve weather resistance.

このように構成したため、サージ吸収器は単一
部品で提供でき、しかも電気的等価回路は第5図
のように第2のセラミツク素子4と第3のセラミ
ツク素子5との直列回路と第1のセラミツク素子
3とバリスタ素子7とを並列接続したものとな
り、第1,第2のリード線8,9の一端8a,9
aを電源線や信号線の線間に接続し、第3のリー
ド線10の一端10aを被保護機器のシヤーシや
アース等に接続して使用すると、線間に侵入する
サージ,ノイズで,電圧,電流値の大きいものは
バリスタ素子7で吸収し、バリスタ素子7の動作
電圧以下のものについては第1のセラミツク素子
3がバイパス効果を示し、線−アース間に侵入す
るノイズに対しても第2,第3のセラミツク素子
4,5がバイパス効果を示す。このように広い範
囲のサージ,ノイズに対して有効なサージ吸収器
となる。またバリスタ素子7によつて電圧は低く
抑制されるため、第1,第2,第3のセラミツク
素子3,4,5の耐電圧は低いものでよく、コン
パクトにサージ吸収器を実現できる。
With this configuration, the surge absorber can be provided as a single component, and the electrical equivalent circuit consists of a series circuit of the second ceramic element 4 and the third ceramic element 5, and a series circuit of the first ceramic element 4 and the third ceramic element 5, as shown in FIG. The ceramic element 3 and the varistor element 7 are connected in parallel, and one ends 8a, 9 of the first and second lead wires 8, 9
If the third lead wire 10 is connected between the power supply line and the signal line, and one end 10a of the third lead wire 10 is connected to the chassis, ground, etc. of the protected equipment, the voltage may be reduced due to surges or noise that enters between the lines. , large current values are absorbed by the varistor element 7, and for currents below the operating voltage of the varistor element 7, the first ceramic element 3 exhibits a bypass effect, and the first ceramic element 3 exhibits a bypass effect against noise that enters between the line and the ground. The second and third ceramic elements 4 and 5 exhibit a bypass effect. In this way, it becomes an effective surge absorber for surges and noise over a wide range. Further, since the voltage is suppressed to a low level by the varistor element 7, the withstand voltage of the first, second, and third ceramic elements 3, 4, and 5 may be low, and a compact surge absorber can be realized.

なお上記実施例において第1,第2の外部出力
端子として各1本ずつの第1,第2のリード線
8,9を設けたが、これは第6図に示す電気的等
価回路となるように、第1,第2の外部出力端子
として各2本づつの端子を設けることもできる。
In the above embodiment, one each of the first and second lead wires 8 and 9 were provided as the first and second external output terminals, but these were designed to form the electrical equivalent circuit shown in FIG. Additionally, two terminals each may be provided as the first and second external output terminals.

以上説明のように本考案によると、極めて有効
なサージ吸収効果を示すサージ吸収器を単一部品
で提供することができ、また非常にコンパクトで
プリント基板等への挿入が簡単であるため、従来
のように取り付けに際して工数が増加することも
ない。
As explained above, according to the present invention, it is possible to provide a surge absorber that exhibits an extremely effective surge absorption effect as a single component, and it is also extremely compact and easy to insert into a printed circuit board, etc. There is no increase in the number of man-hours required for installation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図と第2図は従来のサージ吸収回路図、第
3図〜第6図は本考案の実施例を示し、第3図は
本考案のサージ吸収器の構造説明図、第4図はセ
ラミツク誘電体素子の正面図、第5図は第3図の
電気的等価回路図、第6図は他の実施例の電気的
等価回路図である。 3,4,5……第1,第2,第3のセラミツク
誘電体素子、6……電極、7……酸化亜鉛バリス
タ素子〔電圧依存性非直線抵抗素子〕、8……第
1のリード線〔第1の外部接続端子〕、9……第
2のリード線〔第2の外部接続端子〕、10……
第3のリード線〔第3の外部接続端子〕。
Figures 1 and 2 are conventional surge absorbing circuit diagrams, Figures 3 to 6 show embodiments of the present invention, Figure 3 is an explanatory diagram of the structure of the surge absorber of the present invention, and Figure 4 is A front view of the ceramic dielectric element, FIG. 5 is an electrical equivalent circuit diagram of FIG. 3, and FIG. 6 is an electrical equivalent circuit diagram of another embodiment. 3, 4, 5...first, second, third ceramic dielectric elements, 6...electrode, 7...zinc oxide varistor element [voltage dependent nonlinear resistance element], 8...first lead Wire [first external connection terminal], 9... Second lead wire [second external connection terminal], 10...
Third lead wire [third external connection terminal].

Claims (1)

【実用新案登録請求の範囲】 1 両端面に電極を有する平板状の第1,第2,
第3のセラミツク誘電体素子を並設し、第1,
第2のセラミツク誘電体素子の間に、両端面に
電極を有する平板状の電圧依存性非直線抵抗素
子を介装し、第1,第2,第3のセラミツク誘
電体素子および前記電圧依存性非直線抵抗素子
の対向する電極面を互いに接続すると共に、第
2と第3のセラミツク誘電体素子の直列回路と
第1のセラミツク誘電体素子と前記電圧依存性
非直線抵抗素子とを並列接続し、この並列接続
された並列回路の両端に導通する第1,第2の
外部接続端子および第2のセラミツク誘電体素
子と第3のセラミツク誘電体素子との接続部に
導通する第3の外部接続端子を設けたことを特
徴とするサージ吸収器。 2 第1,第2の外部接続端子を、それぞれ2本
ずつのリード線で構成したことを特徴とする実
用新案登録請求の範囲第1項記載のサージ吸収
器。
[Claims for Utility Model Registration] 1. First, second, flat plate having electrodes on both end faces.
A third ceramic dielectric element is arranged in parallel, and the first,
A flat voltage-dependent nonlinear resistance element having electrodes on both end faces is interposed between the second ceramic dielectric element, and the first, second, and third ceramic dielectric elements and the voltage-dependent Opposing electrode surfaces of the nonlinear resistance elements are connected to each other, and a series circuit of second and third ceramic dielectric elements, the first ceramic dielectric element, and the voltage-dependent nonlinear resistance element are connected in parallel. , first and second external connection terminals conductive to both ends of the parallel circuit connected in parallel, and a third external connection conductive to the connection portion between the second ceramic dielectric element and the third ceramic dielectric element. A surge absorber characterized by having a terminal. 2. The surge absorber according to claim 1, wherein the first and second external connection terminals each include two lead wires.
JP18573780U 1980-12-23 1980-12-23 Expired JPS6316282Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18573780U JPS6316282Y2 (en) 1980-12-23 1980-12-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18573780U JPS6316282Y2 (en) 1980-12-23 1980-12-23

Publications (2)

Publication Number Publication Date
JPS57108636U JPS57108636U (en) 1982-07-05
JPS6316282Y2 true JPS6316282Y2 (en) 1988-05-10

Family

ID=29987056

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18573780U Expired JPS6316282Y2 (en) 1980-12-23 1980-12-23

Country Status (1)

Country Link
JP (1) JPS6316282Y2 (en)

Also Published As

Publication number Publication date
JPS57108636U (en) 1982-07-05

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