JPS63161392U - - Google Patents
Info
- Publication number
- JPS63161392U JPS63161392U JP1987053388U JP5338887U JPS63161392U JP S63161392 U JPS63161392 U JP S63161392U JP 1987053388 U JP1987053388 U JP 1987053388U JP 5338887 U JP5338887 U JP 5338887U JP S63161392 U JPS63161392 U JP S63161392U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- microphone
- analog
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electric Clocks (AREA)
Description
第１図は本考案の一実施例の時計の平面図、第
２図は本考案の一実施例の動作を示すブロツク図
である。
４……マイク、１１……アナログ、デジタル変
換回路、１２……記憶回路、１４……比較回路、
１６……コントロール回路、２１……カウンター
回路。
FIG. 1 is a plan view of a timepiece according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the operation of an embodiment of the present invention. 4...Microphone, 11...Analog, digital conversion circuit, 12...Memory circuit, 14...Comparison circuit,
16...control circuit, 21...counter circuit.
Claims (1)
するアナログ―デジタル変換回路、該アナログ―
デジタル変換回路によつてデジタル信号化された
言葉を記憶する記憶回路、及び、マイクから音声
言語が入力された時に前記記憶回路に収納されて
いる言語とを比較し一致した時に信号を発生する
比較回路を有する時計に於て、該比較回路からの
不一致信号の回数を計数するカウンター回路と、
該カウンター回路から一定回数以上連続して不一
致信号を受け取つた時に出力信号を発生して時計
回路の動作をコントロールするコントロール回路
を設けた事を特徴とする音声入力電子時計。 Analog-to-digital conversion circuit that converts the audio input from the microphone into a digital signal, the analog-
A memory circuit that stores words converted into digital signals by a digital conversion circuit, and a comparison that generates a signal when a spoken language is input from a microphone and is compared with the language stored in the memory circuit. In a clock having a circuit, a counter circuit counts the number of times a mismatch signal is received from the comparison circuit;
A voice input electronic timepiece characterized in that it is provided with a control circuit that controls the operation of the timepiece circuit by generating an output signal when a mismatch signal is continuously received from the counter circuit a certain number of times or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987053388U JPS63161392U (en) | 1987-04-10 | 1987-04-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987053388U JPS63161392U (en) | 1987-04-10 | 1987-04-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63161392U true JPS63161392U (en) | 1988-10-21 |
Family
ID=30879407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987053388U Pending JPS63161392U (en) | 1987-04-10 | 1987-04-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63161392U (en) |
-
1987
- 1987-04-10 JP JP1987053388U patent/JPS63161392U/ja active Pending