JPS6316079B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides that the color signal obtained by a demodulator from a modulated color carrier is delayed by one horizontal scan line duration by a delay line configured as a charge transfer circuit, and then A color difference signal is formed from the delayed signal and the non-delayed signal in a functional summing stage, in which case the delay line, the demodulator and the summing stage are constructed on a semiconductor chip using integrated technology. or
This invention relates to a color decoder for a SECAM color television receiver.

In a known arrangement for the demodulation of a PAL color carrier, the color carrier is delayed by one scan line duration in a glass ultrasonic delay line, and in two summing stages the delayed color carrier is 180 degrees in phase with the undelayed color carrier. .degree. changed specific delay color carrier wave. This results in both carrier frequency components (RY) and (BY)
Signal division is performed. The (BY) component is demodulated in the first demodulator using a reference carrier generated from a reference carrier oscillator. The (RY) component, which varies by 180° in phase from scan line to scan line, is demodulated in a second demodulator using a reference carrier that is rotated by 90° in phase and varies by 180° from phase to scan line. Ru. In this way, both video frequency color difference signals (B-
Y)' and (RY) are formed. This type of decoding has the disadvantage that glass delay lines are required, which cannot be integrated into current semiconductor circuits.

Magazine Funkteichnique, 1971, No. 6, No. 195
Pages 1 to 198 show that two bucket-to-chain circuits are used in the PAL decoder rather than glass delay lines. Because the bucket-to-chain circuit has low-pass characteristics, only the video frequency signal is delayed. In the case of this known decoder, the color carrier is therefore divided into two video frequency signals (B-Y) in two synchronous demodulators.
and (RY). These signals are then passed through each delay line, which is configured as a shift register for the analog signal.
Delayed by one scan line duration. By adding the undelayed signal and the correspondingly delayed signal, two color difference signals (BY)' and (RY) are formed in the respective summing stage. Next, both color difference signals (B
-Y)' and (RY) are led in a predetermined ratio to another summing stage which is used as a matrix. This addition stage converts this signal into a color difference signal (G
-Y)' is formed. This decoder has the disadvantage of requiring many parts.

The object of the invention is to provide a color decoder for a color television receiver that is completely integrable and operates with as little power consumption as possible.

This problem is solved according to the invention in a color decoder for color television receivers of the type mentioned at the outset, in that in addition to the delay line, the synchronous demodulator and summing stage are also used as charge transfer circuits. The charge of the modulated color carrier wave is sampled and transferred from the first electrode to the second electrode at predetermined equidistant times for synchronous demodulation, and this transfer causes the second electrode to receive the RY signal. or by causing a charge to be formed corresponding to the B--Y signal, and by conducting the charges of both signals to two separate electrodes for addition and further transferring them from these electrodes to a common third electrode. It has been resolved by. Furthermore, the above problem has been solved as follows. That is, in a color decoder for a color television receiver of the type mentioned at the outset, in addition to the delay line, a synchronous demodulator and a summing stage are also configured as charge transfer circuits, and furthermore, for synchronous demodulation, predetermined equidistant time points are provided. The charge of the modulated color carrier wave is sampled and transferred from the first electrode to the second electrode, and this transfer causes a signal or a charge corresponding to the signal to be formed in the second electrode. directing the charges of both signals to two separate electrodes and further transferring them from these electrodes to a common third electrode;
Furthermore, the charge transfer circuit is configured as a unit using CCD technology, in which case each input side electrode of the two adder stages is connected to the respective (B-Y) or (R-Y).
The third summing stage is divided into two equally sized electrodes with a size ratio of 1:1 and is used as a color difference signal (G-Y) matrix. This problem is solved by dividing the input side electrode into two electrodes each having a size corresponding to a predetermined size ratio in order to be supplied with a color difference signal. Advantageous embodiments of the invention are indicated in the dependent claims.

The basis of the understanding of the present invention is that the charge transfer circuit, which itself is used for signal delay,
The present invention is intended to be used also for constructing demodulation and addition stages in a color decoder. The advantage of this is that the elements that substantially constitute the color decoder, such as delay lines, demodulators and summing stages,
All can be implemented using the same circuit technology. This greatly simplifies the production of this type of decoder as an IC on a single semiconductor chip. Due to the same circuit technology for all these circuit stages, this IC is manufactured with great technical advantages. Since this circuit part consumes only a small amount of power, further amplifiers, pulse shapers, frequency converters and/or inversion circuits are mounted on the same semiconductor chip, which is preferably realized in MOS technology. As a result, only a few external terminals are required for this type of integrated component. The decoder of the invention can be used both for decoding PAL color carriers and for decoding SECAM color carriers.

This decoder is advantageously constructed as a single unit as a charge transfer circuit. Specifically for this purpose CCD technology (charge-coupled device technology)
is suitable. Due to the unique structure of the input side electrode of this charge transfer circuit, this charge transfer circuit is not only used for the scanning line of the signal generated in the synchronous demodulator as in the present invention, but also for weighting of the input signal. It is also used for addition of unweighted and weighted quantities. For example, since the input electrode is divided into two electrodes of equal size, this type of addition stage is suitable for adding a non-delayed signal and a delayed signal. In this case, this summing stage uses upstream delay lines, for example for the signal (B
-Y) to the phase-averaged color difference signal (B-
Y)' can be formed. However, if the input side electrodes are divided in the gray signal according to the ratio of the color difference signals, this type of charge transfer circuit
The signal (B
-Y)' and (RY) to generate the signal (G-Y)'. Summing stages and synchronous demodulators of this type have only a few clock pulse electrodes. This adder stage and synchronous demodulator are constructed in the same manner as the CCD delay line except for the input side electrodes, so the components are simple and can be manufactured at low cost.

According to claim 10 of the invention, the summing stage used as a matrix adds the color difference signals in the normalized case to form the color difference signal (GY)'.

The color carrier wave in a color television receiver is approximately
4MHz, and the upper cutoff frequency of the video frequency color signal is 1MHz. According to sampling theory, twice the upper cutoff frequency of the signal to be sampled can therefore be selected as the sampling frequency. This is used in the decoder of the present invention, ie, 1/2 of the color carrier frequency is used as the sampling frequency of the charge transfer circuit. The advantage of this reduction in sampling frequency without compromising quality is that the power consumption in the charge transfer circuits is significantly reduced and that more components can be included on the semiconductor chip since less power is dissipated. It is what happens.

Next, embodiments of the present invention will be described with reference to the drawings.

The circuit parts shown in the dashed block 1 in FIG. 1 are provided on a single semiconductor chip, for example a P-type silicon substrate. All components are realized using MOS technology.

The decoder receives color difference signals (B-Y)', (R-Y) and (G-
Y)'. The color carrier wave F is demodulated in a synchronous demodulator 12, 22, which is connected upstream of an amplifier 11 to 21, respectively. This allows both video frequency color signals (B
-Y) and (RY) are formed. Each of both color signals is then delayed in delay lines 13-23 by one horizontal scan line time, or 64 μs. The two undelayed signals and the respective delayed signal are added in a summing stage 14 to 24. As a result of this addition, both color difference signals (BY)' and (RY) are available at the outputs of adder stages 14 and 24. Both color difference signals are further led to a summing stage 31 which is used as a matrix. This addition stage weights and adds these two color difference signals according to the color television standard, thereby producing a color difference signal (GY)' at its output. An inversion stage 32 generates the correct polarity for the color difference signal (GY)'. The synchronous demodulators 12 and 22, the delay lines 13 and 23, the addition stages 14 and 24, and the addition stage 31 used as a matrix are configured as a charge transfer circuit. The charge transfer clock pulses are derived from a reference carrier generated at the receiver.

When using the decoder as a PAL decoder, a reference carrier wave generated by a local oscillator and having a frequency of 4.43361875 MHz is introduced to the input side FB for forming a color difference signal. Another input FR is provided because the (RY) component of the color carrier is shifted in phase by 180° from horizontal scan line to horizontal scan line. A reference carrier wave whose phase is shifted by 90° and whose phase is changed by 180° per horizontal scanning line is introduced into this input side. Pulse shaping stages 41 and 51
, 1 from each period of the respective reference carrier wave.
Two pulses are generated. The number of pulses per unit time is divided by half in frequency dividers 42 to 52. The pulses obtained in this way therefore have half the frequency of the color carrier.

The non-alternating pulse train is hereinafter referred to as a first pulse train. This first pulse train is used in the CCD synchronous demodulator 12 for sampling the modulated color carrier. Through this sampling, the output side of the synchronous demodulator 12 receives a color signal (B-Y).
occurs.

The alternating reference carrier waves are hereinafter referred to as a second pulse train. This second pulse train has a phase difference during the duration of one horizontal scan line when compared to the first pulse train.
90° to 270° shifted, therefore synchronous demodulator 2
2, the (RY) component of the modulated color carrier is sampled.

In order to be able to use the same pulse train for charge transfer for another signal processing, a temporary storage 221 formed as a capacitor is provided between the synchronous demodulator 22 and the delay line 23. ing. This temporary memory is stored in the synchronous demodulator 2
The signal sent to the output of 2 is held for a duration of approximately 1 μs. As a result, the amplitude of the signal is read into the input of the delay line 22 and the summing stage 24 at the clock of the first pulse train. For this purpose, it is advantageous to form the output of the synchronous demodulator 22 as a source follower. The downstream charge transfer circuits 23, 24, 31 are all clocked by the first pulse train.

In order to delay the signal by one horizontal duration, the delay lines 13, 23 must each have 142 stages since the scanning frequency _A = F/2.
In this case F=color carrier frequency. CCD
The realization of a delay line as a shift register is described, for example, in the magazine Vac.Sci.Technol, Vol. 9, No. 4 (1972).
Shown on pages 1166-1181.

According to an embodiment of the invention, adder stages 14, 24, 3
1 has a divided input side electrode. The division ratio of this input electrode corresponds to the weight of the signals to be added.

As shown in FIG.
It is divided into. On the other hand, the subsequent clock pulse electrode and the subsequent electrode are not divided, so that the sum of the charges of the input electrodes is supplied.

On the other hand, the addition stage 31 used as a matrix outputs color difference signals (B-Y) and (R-
Y) at a ratio of 11:30 and then the sum signal is 41/59.
must be reduced to According to the invention, this can be accomplished by adding stage 31 as shown in FIG.
This is achieved by dividing the input side electrode into two parts. (B-Y) The electrode portion to which the signal is led is the clock electrode 90 of the addition stage 31.
The electrode portion to which the (RY) signal is led is formed to be 30/59ths of the length.

This split electrode technique can also be advantageously used on the output side of a CCD circuit. Synchronous demodulator 1
If the output side electrode of 2 is divided into two parts of equal size, one part is directly connected to the divided input side electrode of the adder stage 14, and the other part is connected to the input side of the delay line 13. Directly connected.

When the output side electrode of the addition stage 14 is divided into two parts, the color difference signal (B-
Y)' can be led to the output side of block 1,
The other part can be part of the input side electrode of the summing stage 31. The same applies to the connection of adder stage 24 and adder stage 31. The charge transfer circuitry of the decoder shown in FIG. 1 can be constructed as a single unit, allowing for space-saving integration.

The decoder described above can also be configured as a SECAM decoder. For this purpose, a modulated SECAM carrier is applied to the input F in FIG. 1, and a color carrier is applied to the inputs FB and FR alternately for each scanning line. Furthermore, frequency 1/2 divider 4
On the output side of 2, the line is separated at point A, and at this point, the sampling frequency obtained from the color carrier wave and divided into 1/2 frequency is transferred as a transfer pulse to the delay lines 13, 23 and the addition stage 14,
24, 31. The pulse shaper 43 and 1/2 frequency divider 44 required for this purpose are:
As shown in FIG. 1, they can likewise be integrated together in a semiconductor chip 1. A continuous color carrier frequency is therefore supplied to the input side B.

When the line is disconnected at point A, the decoder for SECAM is controlled via terminals F, FB, FR and B, and the decoder for PAL is controlled via terminals F, FB and FR.
Control via. In the latter case, terminal B is terminal FB
Connect with.

Since the addition stage 31 is configured as a charge transfer circuit, the signal (G-
Y)' has a slight phase shift compared to the other two color difference signals. According to an embodiment of the invention, therefore, the clock pulse lines of summing stages 14 and 24 are made to increase by the same number of clock pulse lines as summing stage 31 has, so that the terminals for the input side of summing stage 31 However, addition stage 14,2
Form 4 taps. Phase shifts between the color difference signals sent out from the decoder are avoided. As is known in color television, the color channel has a narrower bandwidth than the luminance channel. This means that the transit time of the signal in the color channel is greater than the transit time in the luminance channel. The signals from the color channel and the luminance channel must eventually be brought together again simultaneously at their correct time positions on the cathode ray tube. In color television receivers, an additional delay must therefore be provided in the line of the luminance channel. In practice, this is usually accomplished by means of delay lines. This delay line is formed from a series-connected inductance and a parallel capacitance connected in a distributed manner. A delay line of this kind is shown, for example, in German Patent No. 1204349. The delay time of the signal delay in the luminance channel is now on the order of 500 ns compared to the longer transit time of the signal in the color channel.

If demodulation and addition in a color decoder are performed by a charge transfer circuit, additional time is required for this charge transfer. This firstly means that the delay time acting on the lines of the color decoder is increased compared to conventional color decoders. Therefore, the line delay of the luminance signal must also be increased accordingly.

Figures 4 to 9 show embodiments of decoders in which the aforementioned delays are kept as small as possible. In this embodiment, for example for demodulator action and adder action, the unique arrangement of the electrodes relative to each other ensures that the signal transit times occurring in the case of such actions are kept to a minimum. For this purpose, the signals reach the circuit stage which ultimately takes care of the formation of the color difference signals for the control of the picture tube, either directly on the one hand or delayed by one horizontal scanning line duration on the other hand, as quickly as possible. In this case a delay by the horizontal duration is still provided, since this delay is desirable for averaging value formation in the PAL decoder.

FIG. 4 shows a rectangular electrode on a semiconductor chip. Charge exists under each of these electrodes, and charge is transferred between the electrodes. The numbers shown inside the rectangles represent the ratio of the lengths of these electrodes. Lowercase letters a to d in FIGS. 4 and 5 indicate the progress of charge transfer.
FIG. 5 shows these developments for a sine wave of an unmodulated color carrier, ie a sine wave of a reference carrier of constant frequency and phase generated by a local oscillator. In this case, a standardized color carrier frequency of 4.43361875MHz is used. This frequency corresponds to one cycle period of the color carrier, approximately 226 ns.

Next, using FIGS. 4 and 5, the synchronous demodulator 1 configured as the charge transfer circuit shown in FIG.
As operations 2 and 22, individual operations of the PAL decoder based on charge transfer will be explained. A synchronous demodulator is implemented using electrodes 3, 4, and 19.

1 (RY) Demodulation (RY) demodulation is performed using electrodes 3 and 4.

The modulated color carrier wave F is transferred from terminal 2 to electrode 3
reach. Time point b corresponding to the maximum value of the function cosωt
At , charge is transferred from electrode 3 to electrode 4 . This is indicated by arrow b in Figures 4 and 5. This corresponds in practice to the sampling of the modulated color carrier at a given point in time, so that this forms a synchronous demodulator in the RY direction. Therefore, a charge having a value corresponding to the value of the (RY) signal is generated under the electrode 4. This charge transfer takes place at equidistant points in FIG. 5, ie at point b in each case. Only each second period of the color carrier is scanned as shown. This is sufficient, because the color carrier frequency is 4.4M
Hz, and the cutoff frequency of the color signal is only about 1 MHz. In summary, the modulated color carrier wave applied at the point designated F in FIG. 1 is transferred to another electrode at the corresponding time point shown in FIG. This refers to sampling the modulated color carrier at predetermined points in time. These points in time are indicated in FIG. 5 by vertical lines and lower case letters as described above.
This type of carrier sampling at a predetermined point in time of the carrier frequency represents synchronous demodulation. This is because the amplitude value of the carrier wave is determined at a predetermined point in the carrier wave period.

2 Input coupling to the delay line At time c, only half of the charge present under electrode 4 is transferred to electrode 5. This electrode 5 also forms the input side electrode of the delay line. Electrode 5
A plurality of electrodes having the same shape are arranged in succession along the path 7. The point where the charge transfer direction is reversed at the right end of the path 7 is achieved in the semiconductor chip by appropriate arrangement of electrodes or by diffusion so that the direction is reversed.
Electrode 8 is the last electrode of a delay line for a horizontal scan line period formed by a plurality of electrodes 6 along path 7. Therefore, a demodulated (R-Y) signal appears on electrode 4, and a demodulated (R-Y) signal delayed by the horizontal scanning line period appears on electrode 8.
Y) A signal appears. The transfer of charge from one electrode to the next in dashed line 7 takes place overall from electrodes 6 to 8 at the time d in each case, for example at d+226 ns., which has advanced by two phases. The number of stages is selected accordingly to provide the desired delay by the horizontal scan line period.

3. Average value formation of undelayed (RY) and delayed (RY) signals.

An electrode 9 is provided between the electrode 4 and the electrode 8. Due to the applied clock frequency, between the individual electrodes, on the one hand, 1/4 of its charge from electrode 4 reaches electrode 9, ie a non-delayed (RY) signal is reached. On the other hand, half of the charge on electrode 8 reaches charge 9 due to the applied clock frequency, ie the (RY) signal is delayed by the horizontal scan line period. Therefore, electrode 9 has no delay (R
-Y) signal and delayed (R-Y) signal
A PAL average value is formed. As a result, a signal (RY) averaged over twice the time of the horizontal scanning line is supplied to the terminal 10.

4 Consideration of PAL switching operation As is well known, the (R-
The Y) axis is varied by 180° for each horizontal scan line. This must be taken into account in the case of synchronous demodulation. Therefore, in each second horizontal scan line the charge transfer b
is shifted by 180° of the color carrier period. This is indicated by b' in FIG. Therefore, the time point of charge transfer is switched back and forth between b and b' for each horizontal scanning line. Therefore, charge transfer b and subsequent charge transfer c
The time interval between the horizontal scan lines has a different length for each horizontal scan line.

5 (BY) Demodulation (BY) demodulation is performed using electrode 3 and electrode 19.

The demodulation of the color carrier F at terminal 2 is carried out by electrode 3.
in the form of a charge under , which is carried out by the charge transfer at time a, ie according to the quadrature two-phase modulation of the color carrier, is shifted relative to b by 90° of the color carrier period. This corresponds to synchronous demodulation of the modulated color carrier in the axial (BY) direction. Another transfer takes place at time c as described above. Other paths can be compared to (RY) demodulation. Demodulated (B-
Y) The signal accordingly runs along the dashed line 15. Therefore, the electrode structure is symmetrical with respect to the signals RY and BY. In this case only the length of the electrodes has the different dimensions shown, so as to correspond to the amplitude evaluation of this signal. In the case of (BY) demodulation, there is no need to consider PAL switching changes because the (BY) axis remains constant and does not change. Charge transfer a therefore takes place at the same point in time relative to the color carrier period. Therefore, just as an averaged (RY) signal is generated at electrode 9, a signal (BY)' is generated at electrode 16, which is averaged over twice the time of the scan line. This signal is at terminal 17
taken from.

6. Formation of the (G--Y)' signal In the known circuit, the (G--Y)' signal is formed by matrixing the signals at terminals 10, 17 in FIG. However, in the decoder of FIG. 4, the (GY)' signal is formed in another way. That is, a (G-Y)' signal is formed at electrode 18. This electrode is connected to electrode 4 on the upper left side.
is supplied with an undelayed signal (RY) from electrode 8, and on the upper right side is a delayed signal (RY) from electrode 8.
The lower left side is supplied with a delayed signal (B-Y) from the electrode 19, and the lower right side is supplied with a delayed signal (B-Y) from the last electrode of the delay path 15.
Y) is supplied. Therefore, the signal (GY)' is formed according to the following equation, unlike in the case of known circuits.

(G-Y)'=-[30/59・1/2・(RY) ^* _o+1 +30/59・1/2・(RY) ^* _o +11/59・1/2・( B-Y) ^* _o+1 +11/59・1/2・(B-Y) ^* _o
] The amplitude constants given are taken into account by the longitudinal dimensions of the individual electrodes, which are shown in FIG.

FIG. 6 shows a block diagram of the decoder of FIG. 4 and a particularly novel method of forming the (GY)' signal.

The assignment of charge transfer in FIG. 4 is again shown by arrows ad in the block diagram of FIG. The summing stage 35 corresponds to the electrode 9 in FIG. 4, and the summing stage 36 corresponds to the electrode 16 in FIG. As shown, the (GY)' signal is formed from a total of four signals, namely the respective input and output signals of both delay lines.
This is illustrated by summing stage 38. The four inputs of this summing stage are marked with their amplitudes accordingly. The four input sides are thus formed by electrodes 4, 8, 19 and 28 of FIG. 4, and the output side is formed by electrode 18.

It is clear that with the arrangement of the electrodes as in FIG. 4, a very rapid charge transfer takes place without unavoidable detours or delays. The charge is therefore transferred each time to the next electrode with a very small delay, and in this way the charge is transferred to the next electrode with a very small delay.
signals (RY), (B-Y)' and (G-
Y)' can now be obtained.

Figure 7 is a partial extraction of the diagram in Figure 5, and shows (R-Y) in the case of b corresponding to cosωt.
Showing charge transfer for demodulation. The maximum delay time occurring in the signal path between charge transfer for synchronous demodulation and charge transfer to the delay line is in this case 113 ns. This corresponds to a clock period of 8.8MHz.
The clock pulse for a delay of one horizontal scan line period is 2.2 MHz. The written character b,
c, d correspond to the charge transfer between the electrodes shown in FIG.

Figure 8 is a part of Figure 5 (B-Y)
Showing charge transfer for demodulation. In this case, the maximum delay time is only 56 ns, which corresponds to a clock frequency of 17.6 MHz. The charges transferred at different times b and a are therefore transferred further at the same time c in each case. If a clock frequency of 17.6 MHz were actually implemented, the charge would remain under the electrode unnecessarily long between points b and c in FIG. 7.

FIG. 9 shows the clock pulses for charge transfer. In this case each charge transferred is individually 17.6MHz
The clock frequency allows the fastest transmission. Overall, in the circuits of FIGS. 4 and 5, charge transfers a, b, b' take place at three different times in the case of synchronous demodulation. In FIGS. 7 and 8, for these three charge transfers at different times, the subsequent charge transfer c always takes place at the same time with respect to the color carrier period. In FIG. 9, this charge transfer c takes place immediately after each charge transfer b', b and a, each at an interval of 56 ns. The relationship between both charge transfers is shown by square brackets. The charge transferred from electrode 3 to electrode 4 at time b' in FIG. 5 is not transferred further to electrode 5 only at time c as in FIG. 5, but already at time c.
Immediately after the charge transfer b' at , the transfer takes place as long as the amplitude height of the clock pulse period present at this moment is sufficient for the transfer.

Since the respective summation of the signals of the nth horizontal scan line and the n+1th horizontal scan line takes place at precise delay clock pulse intervals, the inherent delay line is only 140.5 stages long instead of 141.5 stages long. It becomes the length. Furthermore, in the minimum case, i.e. the distance between d and c, i.e. charge transfer from electrode 5 to electrode 6, for example,
This becomes a 1/4 delayed clock pulse. As a result, the total delay time is 141.75・1/1/2・4.43317MH=63.949
μs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a decoder according to the invention;
Figure 2 shows the dimensions of the electrodes of the CCD summing stage used as a matrix for the addition of equal quantities; Figure 3 shows the dimensions of the electrodes of the CCD summing stage used as a matrix for the addition of unequal quantities; Figure 4 shows the dimensions of the electrodes of the CCD summing stage used as a matrix for addition of unequal quantities; 5 is a diagram illustrating the operation of the decoder of FIG. 4, and FIG. 6 is a diagram illustrating the addition stage forming the signal (GY)' The block diagrams, FIGS. 7, 8 and 9 show diagrams for explaining the charge transfer in the embodiment of FIG. 4 and the different clock pulse periods occurring in this case. 11,21...Amplifier, 12,22...Synchronous demodulator, 13,23...Delay line, 14,24,3
1, 35, 36, 38... Addition stage, 32... Inversion stage, 41, 51... Pulse shaping stage, 42, 44,
52...1/2 frequency divider, 43...pulse shaping stage.

Claims (1)

[Claims] 1. Color signals (BY, RY) obtained from the modulated color carrier wave F by the demodulators 12, 22 are transmitted to the delay lines 13, 23 configured as a charge transfer circuit.
is delayed by one horizontal scan line duration, and then a summing stage 14 with matrix action,
24, a color difference signal [(B-Y)', (RY)'] is formed from the delayed signal and the non-delayed signal, and in this case, the delay lines 13, 2
3. The demodulators 12, 22 and addition stages 14, 24 are constructed on a semiconductor chip using integrated technology.
In a color decoder for a PAL or SECAM color television receiver, the delay line 1
3, 23 as well as synchronous demodulators 12, 22 and summing stages 14, 24 as charge transfer circuits; The charge is sampled and transferred from the first electrode 3 to the second electrodes 4, 19, and as a result of this transfer, the second electrodes 4, 19 receive a (RY) signal or a (B-) signal.
Y) causing a charge corresponding to the signal to be formed;
Further, for addition, the charges of both signals are guided to two separate electrodes 61 and 62, and further transferred from these electrodes to a common third electrode 70.
Color decoder for PAL or SECAM color television receivers. 2 As the sampling frequency of the charge transfer circuit,
2. The color decoder according to claim 1, wherein a frequency that is 1/2 of the color carrier frequency is used. 3 Demodulator output side electrodes 4, 19 and delay line 1
The electrodes 9, 3 and 23, respectively, form the output electrodes 8 and 28 of the adding stages 14 and 24.
Claim 1 provided on both sides of 16
Color decoder described in section. 4 A plurality of electrodes 6, 29 forming the delay lines 13, 23 are provided along the lines 7, 15 returning to the starting point, respectively, and the input side electrodes and output side electrodes of the delay lines 13, 23 are closely spaced. A color decoder according to claim 1, wherein the color decoders are arranged side by side and adjacent to each other. 5. The first electrode 3 that guides the modulated color carrier wave F, the second electrodes 4, 19 that form the output side of the demodulator, and the third electrodes 5, 26 that form the input side of the delay line are provided directly adjacent to each other. A color decoder according to claim 1. 6 The times a and b of the charge transfer from the first electrode 3 to the second electrodes 4, 19 are offset from each other by a time interval corresponding to 90° of the color carrier period in both demodulators, and (RY 6. A color decoder according to claim 1, wherein the color carrier period is varied by 180° for each horizontal scanning line in the demodulator. 7 From the second electrodes 4 and 19 in both demodulators to the third
Claim 1, wherein the charge transfer to the electrodes 5, 26 takes place at the same time c after the last charge transfer a, b from the first electrode 3 to the second electrode 4, 19. color decoder. 8. The time interval of charge transfer from one electrode to the next is made approximately equal to the duration of a quarter color carrier period or an integer multiple of said quarter. The color decoder described in item 1. 9 the first electrodes 3 individually in the signal path;
Following the charge transfer b', b, a from the second electrode to the second electrode 4, 19, the charge transfer from the second to the third electrode 5, 26 occurs for a short period of 56 ns, corresponding to approximately 90° of the color carrier period. , 17.6 MHz clock pulse period). 10 Modulated color carrier wave F to demodulators 12, 22
The color signals (B-Y, R-Y) obtained by the delay lines 13 and 2 configured as a charge transfer circuit
3 by one horizontal scan line duration and then a summing stage 1 with matrix action.
4, 24, a color difference signal [(B-Y)', (R-Y)] is obtained from the delayed signal and the non-delayed signal.
is formed, in which case the delay lines 13,
23, the demodulators 12, 22 and addition stages 14, 24 are constructed on a semiconductor chip using integrated technology.
In a color decoder for a PAL or SECAM color television receiver, the delay line 1
3, 23 as well as synchronous demodulators 12, 22 and summing stages 14, 24 as charge transfer circuits; The charge is sampled and transferred from the first electrode 3 to the second electrode 4, 19, and as a result of this transfer, the second electrode 4, 19 receives a (RY) signal or a (B-
Y) causing a charge corresponding to the signal to be formed;
Furthermore, for addition, the charges of both signals are guided to two separate electrodes 61 and 62, and further transferred from these electrodes to a common third electrode 70, and a charge transfer circuit is configured as a unit using CCD technology. In this case, two adder stages 14, 2
In order for each input electrode of 4 to be supplied with the respective (B-Y) or (RY) non-delayed signal and delayed signal, two electrodes of equal size with a 1:1 dimension ratio are used. 61 and 62, and the third one is used as a color difference signal (G-Y)' matrix.
The input side electrode of the addition stage 31 receives the color difference signal (B-Y)'
PAL or SECAM type color television receiver characterized in that the electrodes 81 and 82 are divided into two electrodes 81 and 82 of a size corresponding to a predetermined size ratio in order to be supplied with and (RY). A handy color decoder. 11 The lengths of the divided input side electrodes of the third addition stage 31 have a ratio of 11/59:30/59,
11. A color decoder according to claim 10, wherein the distance between the two electrodes is 18/59 of the length of the clock pulse electrode of the adder stage. 12 (RY) signal, (G-Y)' signal, (B-
Y)' output side electrodes 9, 18 of the addition stage for the signal
11. The color decoder according to claim 10, wherein the color decoders 16 are arranged in a line. 13 Output side electrode 18 for (G-Y)′ signal
is provided between both output side electrodes 9, 16 for the (RY) signal and the (BY)' signal. 14 On both sides of the output side electrode 18 of the addition stage for the (G-Y)' signal, a part of the output side electrode 4 of the (RY) demodulator, and the output side electrode 8 of the (RY) delay line.
, (BY) a part of the output side electrode 19 of the demodulator, and (BY) the output side electrode 28 of the delay line.
11. The color decoder according to claim 10, wherein a portion of the color decoder is provided respectively.