JPS6316067B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electromagnetic deflection amplification circuit for a cathode ray tube used, for example, in an electronic printer, for deflecting and scanning an electron beam of the tube.

In recent years, electronic printers, such as non-impact type plain paper printers that pursue high speed, are using corona discharge on photosensitive drums made of highly insulating optical semiconductors such as selenium (Se) and cadmium sulfide (CdS). Therefore, uniformly charge it in advance,
The photosensitive drum is sequentially exposed optically using a cathode ray tube, such as an optical fiber recording tube (hereinafter referred to as OFT), and a developer is attached to the electrostatic latent image formed on the photosensitive drum. The electrostatic latent image is visualized, and then this visualized electrostatic latent image on the photosensitive drum is transferred to plain paper being transported by an electrode of opposite polarity, and the transferred image on this plain paper is fixed. I try to fix it by using a container.

(1) By the way, as an application form of such a non-impact type plain paper printer, there is a kanji output terminal printer that has been attracting attention recently. This Kanji output terminal printer is equipped with a character generator composed of, for example, a dot matrix, and when the OFT starts horizontal scanning in response to a first deflection synchronization signal, for example a horizontal synchronization signal,
All the first dots of the corresponding Chinese character group from the character generator are supplied as video signals to the cathode of the OFT. and,
When the next horizontal scan of the OFT begins, all the second dots of the corresponding Chinese character group from the character generator are similarly supplied as video signals to the cathode of the OFT. Thus, horizontal scanning is repeated in the OFT, and when horizontal scanning is performed as many times as the number of vertical dots in the character generator, 1
A line of Kanji text is formed as an electrostatic latent image on the photoreceptor drum. In such a kanji output terminal printer, if you want to change the size of kanji without changing the dot matrix configuration of the character generator, you can change the lateral size of kanji by connecting the character generator to the OFT cathode. In order to change the oscillation frequency of the supplied video signal and also to change the vertical size of the Chinese characters, a method is used to change the output interval of the horizontal synchronizing signal.

FIG. 1 shows a schematic configuration of an OFT, a drive circuit for deflecting and scanning an electron beam of this OFT, and a video amplification circuit. Reference numeral 1 denotes a drive circuit, which includes a sawtooth wave generation circuit 2, a horizontal position adjustment circuit 3, a linearity corrector 4, and an electromagnetic deflection amplification circuit 5. The above sawtooth wave generation circuit 2 is
It converts a horizontal synchronizing signal as shown in FIG. 2a, which is supplied from a control circuit (not shown), into a sawtooth-wave deflection voltage signal as shown in FIG. 2b. In this case, in the horizontal synchronization signal shown in FIG. 2a, the period a of high potential corresponds to the horizontal scanning period of OFT6, which will be described later, and the period b of zero potential corresponds to the horizontal scanning stop period of OFT6, which will be described later. ing. Furthermore, the horizontal position adjustment circuit 3 inverts and level-shifts the sawtooth wave deflection voltage signal supplied from the sawtooth wave generation circuit as shown in FIG. 2c. In this case, assuming that horizontal scanning of the OFT 6, which will be described later, is performed from the left end to the right end of the fluorescent surface 6 ₂ in the figure, the point f of the positive potential in the deflection voltage signal in FIG. 2c is the fluorescent surface 6 ₂ . The zero potential point g corresponds to the scanning position at the center of the fluorescent surface 6 ₂ in the drawing, and the negative potential h point corresponds to the rightmost scanning position of the fluorescent surface 6 ₂ in the drawing. I'm starting to do that. Further, the linearity corrector 4 is
Since the deflection angle of the electron beam of the OFT 6, which will be described later, is approximately proportional to the deflection voltage, the deflection voltage signal supplied from the horizontal position adjustment circuit 3 is corrected so that the amount of movement of the spot on the fluorescent surface ₆₂ is constant. It is something to do. The electromagnetic deflection amplifier circuit 5 converts the deflection voltage from the linearity corrector 4 into a current, that is, a deflection current, and supplies it to the deflection yoke 6 ₁ of the OFT 6 . Note that a video signal as shown in FIG. 2d, which is supplied from a control unit (not shown) in synchronization with the horizontal scanning of the OFT 6, is now supplied to the cathode of the OFT 6 via the video amplifier circuit 7. There is. In this case, the photosensitive drum (not shown) is exposed when the video signal of FIG. 2d is at zero potential.

Therefore, when changing the size of the kanji as described above, the horizontal scanning stop period b in the horizontal synchronization signal in FIG. 6 ₂
A state is reached in which a deflection current corresponding to the scanning position at the left end in the figure continues to flow through the deflection yoke 6 ₁ of the OFT 6 . In addition, the same state is maintained even when the horizontal synchronization signal is not supplied to the sawtooth wave generator 1, so power consumption is higher during non-printing (when OFT 6's deflection scanning is stopped) than during printing. This is an extremely uneconomical situation. In other words, it is necessary to reduce the power consumption when the cathode ray tube stops deflection scanning.

(2) In addition, these non-impact type kanji output terminal printers are superior to impact type ones in that they can vary the printing speed and font size, but as mentioned above, they do not print kanji in dot-to-point format. Since it is composed of tux, it is inferior in terms of legibility of characters.
However, in order to improve the legibility of characters,
It is necessary to increase the density of dots that make up kanji. Therefore, in order to increase the dot density of kanji and print kanji that are more similar to the Mincho font without changing print speed, font size, print density, or resolution, it is necessary to shorten the horizontal scanning time of OFT6 and This will increase the number of scans. However, when the number of horizontal scans is increased, the amount of movement of the spot on the fluorescent surface ₆₂ of the OFT 6 increases, resulting in a decrease in the amount of light per unit area on the fluorescent surface ₆₂ .
This results in a decrease in print density. Therefore, the cathode current of the OFT 6 is increased to prevent a decrease in print density, but an increase in the cathode current adversely affects the life of the cathode.

Here, FIG. 3 shows an example of the circuit configuration of the electromagnetic deflection amplifier circuit 5 and the deflection yoke ₆₁ . That is, the deflection voltage signal supplied to the input terminal i is supplied to the inverting input terminal (-) of the operational amplifier 11 via the resistor 10. In this case, the non-inverting input terminal (+) of the operational amplifier 11 is grounded via the resistor 11 ₁ .
The output of the operational amplifier 11 is supplied to a compensatory symmetric circuit including transistors 12 and 13, DC voltages 14 and 15, and a resistor 16. Thus, a deflection current is supplied to the deflection yoke 6 ₁ from the connection point j of the compensatory symmetrical circuit. Furthermore, a resistor 17 is connected in series to the deflection yoke 6 ₁ , and the voltage generated at the connection point k is applied to the inverting input terminal (-) of the inverting amplifier 11 via the resistor 18 .
They are now being returned to Japan. Therefore,
During actual horizontal scanning of the OFT6, for example, in order to reduce power consumption during non-printing, which is the problem in item (1) above, the deflection voltage during non-printing is maintained near zero potential. When a deflection voltage as shown in _FIG . Therefore, the waveform becomes as shown in FIG. 4b. In this case, in the deflection voltage signal of FIG. 4b, the period 1 corresponds to the retrace period during which horizontal scanning is not possible, and the period m corresponds to the valid horizontal scanning period. Therefore, in order to suppress the cathode current, it is necessary to shorten the deflection retrace period l and lengthen the horizontal scanning effective period m by that amount.

That is _, when the deflection voltage signal shown in _FIG .
flows to By the way, since the deflection yoke ₆₁ includes inductance and resistance components, the inductance is L, the resistance is r, and the resistance is 1.
The resistance value of 7 is R, the electromotive force of the power supply 14 is e,
Furthermore, if the voltage at the connection point k at the time when feedback is applied is R・Ip to be equal to the input voltage to the input terminal i, then the retrace period l is as follows: l=L/R+r・log [1/1−Ip(R+
r)/e](sec). Therefore, the smaller the inductance L of the deflection yoke 6 ₁ and the larger the electromotive force e of the power source 14, the shorter the blanking period l can be. In other words, the horizontal scanning valid period m
can be made longer. However, reducing the inductance L increases the deflection current, and increasing the electromotive voltage e increases the collector loss of the transistor 12. Therefore, in addition to the mere power loss, it is necessary to supplement circuit components such as a heat sink for the transistor 12. Therefore, it becomes difficult to downsize and reduce the cost of the drive circuit. Therefore, in order to eliminate this inconvenience and shorten the retrace period l (lengthen the effective horizontal scanning period m), it is conceivable to increase the electromotive force e of the power supply 14 by the retrace period l. .

(3) Furthermore, Fig. 5 shows the above-mentioned sawtooth wave generation circuit 2.
This figure shows an example of a circuit configuration. That is, 20 is an integrating circuit, which consists of an operational amplifier 21, resistors 22, 23, and a capacitor 24. This integrating circuit 20 integrates the DC voltage -e supplied from the DC power supply 25 to its input terminal n and outputs the integrated signal. In this case, the integrating circuit 2
The output voltage of 0 is equal to the voltage across the capacitor 24. The collector and emitter of an NPN transistor 27 are connected in parallel to the capacitor 24 via a resistor 26, and the base of the transistor 27 serves as the output terminal p of the integrating circuit 20. . Further, the output terminal of the integrating circuit 20 (the output terminal of the operational amplifier 21) is the output terminal q of the integrating circuit 20. However, in Figure 5,
When a horizontal synchronizing signal as shown in FIG. 6a is input to the input terminal p, when the signal is at a high potential, the transistor 27 is turned on and the charge in the capacitor 24 is discharged, and when the signal is at zero potential, the capacitor is 24 is now being charged. In this case, if the electromotive force of the power supply 25 is e, the resistance value of the resistor 22 is r, and the capacitance of the capacitor 24 is c, then when the transistor 27 is off, the voltage Vq obtained at the output terminal q is Vq = -1/ rc∫(-e)dt, resulting in an integral waveform with good linearity as shown in FIG. 6b. Therefore, by inputting the horizontal synchronization signal to the input terminal p, it is possible to repeatedly obtain a sawtooth deflection voltage signal, thereby making it possible to perform horizontal scanning of the OFT 6.

By the way, if the transistor 27 is destroyed due to some kind of failure and becomes open, or if a low potential signal is constantly input to the transistor 27 and the transistor 27 continues to be cut off, the voltage obtained at the output terminal q has a value close to the operating power supply voltage of the operational amplifier 21, and the corresponding deflection current increases power loss, and there is a possibility that the transistor in the electromagnetic deflection amplifier circuit 5 may be destroyed.
Therefore, in order to solve this problem, the output voltage of the sawtooth wave generation circuit 2 is detected, and when the detected voltage becomes larger than the value corresponding to the normal horizontal scanning of the OFT 6, the horizontal scanning of the OFT 6 is stopped. There is a need to.

(4) By the way, simply stopping the horizontal scanning risks burning out the fluorescent surface ₆₂ of the OFT 6 while a video signal is being supplied to the cathode of the OFT 6. For this reason, conventionally,
Measures have been taken to detect whether or not the horizontal scanning of the OFT 6 has stopped, and to protect the video signal in accordance with this detection result. However, the anode of OFT6 typically has about 12kV or
Since a 15kV high-voltage power supply is used, the output stage buffer of the video amplifier circuit 7 is destroyed by the induced voltage when the high-voltage power supply is turned on and off, and as a result, the fluorescent surface ₆₂ of the OFT 6 is burnt out. You may end up doing this. Therefore, even if the output stage buffer of the video amplifier circuit 7 is destroyed, the expensive
It is desirable to reliably prevent burnout of the fluorescent surface ₅₂ of the OFT 5.

This invention was made in view of the above-mentioned circumstances, and its purpose is to shorten the retrace period in deflection scanning of the electron beam of a cathode ray tube without increasing power loss. The present invention provides an electromagnetic deflection amplification circuit for a cathode ray tube with excellent performance.

An embodiment of the present invention will be described below with reference to the drawings. In this case, the same parts as in FIG. 1, FIG. 3, and FIG. 5 are given the same reference numerals, and detailed explanation thereof will be omitted. In FIG. 7, a deflection synchronization signal, such as a horizontal synchronization signal, is supplied to the input terminal s from a control section (not shown). This input terminal s is grounded through a series resistor 30 and a resistor 31, and the base of an NPN transistor 32 is connected to the connection point between the resistor 30 and the resistor 31. A DC voltage +V is supplied between the collector and emitter of this transistor 32 via a resistor 33. Further, the collector of the transistor 32 is connected to the input end of the sawtooth wave generation circuit 2 via a resistor 34.

A horizontal position adjustment circuit 3 is connected to the output terminal q of the sawtooth wave generation circuit 2 described above. This horizontal position adjustment circuit 3 includes an operational amplifier 40, resistors 41, 4
2, 43, 44, 45, and a variable resistor 46, and the variable resistor 46 is supplied with a DC voltage -V. That is, this horizontal position adjustment circuit 3 is a so-called summing and inverting amplifier circuit, which levels-shifts the deflection voltage supplied from the sawtooth wave generation circuit 2 using the voltage generated at the variable output terminal u of the variable resistor 46. , which is inverted.

Therefore, the collector of the transistor 32 is grounded through a series resistor 50 and a resistor 51, and the connection point between the resistor 50 and the resistor 51 is
The base of an NPN type transistor 52 is connected. In other words, when the horizontal synchronizing signal is not input to the input terminal s of this transistor 52,
Alternatively, the horizontal synchronizing signal input to the input terminal s is turned on during the horizontal scanning stop period (zero potential). And this transistor 52
A DC voltage +V is supplied between the collector and the emitter of the transistor via a resistor 53. Furthermore, the collector of the transistor 52 has
The base of a PNP type transistor 57 is connected via inverter circuits 54, 55 and a resistor 56 in series. This transistor 57
A resistor 58 is connected between the base and emitter of the transistor, and a DC voltage +V is supplied to the collector. Further, the connection point between the inverter circuits 54 and 55 is grounded via a series resistor 59 and a resistor 60, and the base of an NPN transistor 61 is connected to the connection point between the resistors 59 and 60. . And this transistor 6
The emitter of No. 1 is grounded, and a series body of resistors 62 and 63 is connected between the collector and the collector of the transistor 57, and the connection point of the resistors 62 and 63 is connected to the It is connected to connection point t. Therefore,
When the horizontal synchronizing signal supplied to the input terminal s is in a horizontal scanning stop period, a predetermined signal voltage is supplied to the connection point t. In other words, the portion of the deflection voltage signal obtained at the output terminal w of the horizontal position adjustment circuit 3 corresponding to the horizontal scanning stop period is suppressed to a predetermined value.

Further, the output terminal q of the sawtooth wave generation circuit 2 is connected to a Zener diode 64 and resistors 65 and 6 in the opposite direction.
6 in series to ground, and the base of an NPN type transistor 67 is connected to the connection point between the resistors 65 and 66. This transistor 67
Its collector is connected to the collector of the transistor 52, and its emitter is grounded. Therefore, when the deflection voltage signal outputted from the sawtooth wave generation circuit 2 exceeds the threshold level of the Zener diode 64, the transistor 67 is turned on, and thereby a predetermined voltage is applied to the connection point t in the horizontal position adjustment circuit 3. The signal is now being supplied. That is, the voltage level of the deflection voltage signal is sequentially detected, and the deflection voltage signal is suppressed below the set voltage level according to the detection result.

Further, the output of the horizontal position adjustment circuit 3 is passed through the linearity corrector 4 to the electromagnetic deflection amplifier circuit 5 of the present invention.
It is now being supplied to This amplifier circuit 5
, a series body of a diode 70 and a resistor 71 is connected between the output terminal of the operational amplifier 11 and the base of the transistor 12. Further, a diode 72 is connected between the bases of the transistors 12 and 13, and a series body of resistors 73 and 74 is connected. A connection point between the resistors 73 and 74 is connected to a connection point j. Further, the base of the transistor 13 and the negative electrode of the power supply 15 are connected through a resistor 75. A diode 76 is connected between the positive electrode of the power supply 14 and the collector of the transistor 12.
The anode of 6 is grounded through a resistor 77 and connected to the base of a PNP transistor 80 through a diode 78 and a resistor 79 in series. The emitter and base of this transistor 80 are connected through a resistor 81. moreover,
The emitter of the transistor 80 is connected to the positive pole of a DC power supply 82, and the negative pole of this power supply 82 is grounded. Further, the collector of the transistor 80 is
Transistor 1 via diode 83 in the forward direction
The anode of the diode 83 is connected to the base of the transistor 12 via a resistor 84. On the other hand, the positive terminal of the power supply 82 is connected to the emitter of a PNP type transistor 85 and to the base of the transistor 85 via a resistor 86. The collector of this transistor 85 is connected to the base of the transistor 80. Further, the cathode of the diode 76 is connected to the base of an NPN type transistor 88 via a diode 87, and the collector of this transistor 88 is connected to the base of the transistor 85 via a resistor 89. Furthermore, the transistor 88
The base and emitter are connected through a resistor 90, and the emitter is connected to the base of an NPN transistor 93 via a resistor 91 and a diode 92 in series. The base and emitter of this transistor 93 are connected through a resistor 94, and the positive electrode of a DC power supply 95 is connected to the emitter. The negative electrode of this power supply 95 is grounded. in this case,
A DC voltage +V is supplied to the connection point between the transistor 88 and the resistor 91. The output end of the operational amplifier 11 is connected to the connection point between the resistor 91 and the diode 92 via a diode 96 in the opposite direction. In this way, the transistor 93 serves as a detection unit that detects whether or not a potential difference has occurred between the deflection voltage from the linearity corrector 4 input to the operational amplifier 11 and the feedback voltage from the connection point k. There is. In other words, if there is a potential difference between the two voltages, the output of the operational amplifier 11 becomes a positive potential and the transistor 93 turns on.
As the transistor 80 turns on accordingly, the electromotive voltage of the power supply 82 is applied to the collector of the transistor 12.

Further, a terminal n is connected to the collector of the transistor 52, and a second grid voltage control circuit 1 for the OFT 6 as shown in FIG.
00 is connected. This second grid voltage suppression circuit 100 includes an NPN type transistor 101,
102, DC power supply 103, diode 104 and resistors 105, 106, 107, 108, 10
9, 110, 111, and 112, and are supplied with a DC bias voltage of +300 [V]. Further, FIG. 9 shows the first grid voltage control circuit 120. The first grid voltage control circuit 120 includes a PNP transistor 121, a Zener diode 122, and a DC power supply 12.
3. Resistance 124, 125, 126, 127, 12
8, DC bias voltage -110 [V]
are now being supplied.

Next, the operation in the above configuration will be explained.

() Now, when a horizontal synchronizing signal as shown in FIG. 10a is input to the input terminal s, when the horizontal synchronizing signal is at zero potential (period b), the transistor 32
is turned off, the transistor 27 is turned on, and the output of the sawtooth wave generation circuit 2, that is, the deflection voltage obtained at the output terminal q becomes zero potential. Furthermore, when the horizontal synchronizing signal is at a high potential (period a), the transistor 32 is turned on and the transistor 27 is turned off, and the deflection voltage obtained at the output terminal q is as shown in FIG.
This results in an integral waveform with good linearity like . Conventionally, the output of the sawtooth wave generating circuit 2 is inverted and level-shifted by a horizontal position adjuster so as to correspond to horizontal scanning, so that when the horizontal synchronizing signal is at zero potential, the fluorescent surface 6 of the OFT 6 ₂
The scanning was made to wait at the left end position of the OFT 6, but here the scanning is made to wait at the center position of the fluorescent surface ₆₂ of the OFT 6.

That is, in the horizontal position adjustment circuit 3, resistors 43 and 46 are used to simplify the input/output relationship.
The resistance value of resistors 41 and 42 is r/
2. If the input voltage (voltage at connection point q) is _V1 , the voltage at connection point u is _V2 , and the voltage at connection point w is _V0 , then _V0 = _{-V1 -V2} . Therefore, when the variable resistor 46 is variably adjusted to match the voltage _V2 at the connection point u with the negative voltage of the peak value |Vh| in the deflection voltage signal in FIG. light surface 6 ₂
A deflection voltage signal having zero potential at the center position is obtained. Furthermore, if the voltage at the connection point t is _V3 , then _V0 = _-2V3 - _V2 . Therefore, in period b of the horizontal synchronizing signal in Fig. 10a, in order to set V ₀ = O [V] (to wait for scanning at the center position of the fluorescent surface of OFT), V ₃ = Vh/2. Bye.

Therefore, the horizontal synchronizing signal in FIG.
When the transistor 32 is turned off, the transistors 52, 57, and 61 are turned on. In this case, the resistance value of resistor 62 is
If r ₁ and the resistance value of the resistor 63 are r ₂ , then the connection point t
The voltage V ₃ becomes V ₃ ≒ (+V)·r ₂ /r ₁ +r ₂ . However, the resistance value r ₁ of resistors 62 and 63,
r ₂ is sufficiently smaller than the resistance value r/2 of the resistors 41 and 42, and the voltage drop across the resistors 62 and 63 is sufficiently larger than the collector-emitter voltage of the transistor 57 and the collector-emitter voltage of the transistor 61. shall be taken as a thing. Therefore, if the values of the resistors 62 and 63 are selected so that the value of the voltage _V3 at the connection point t matches the value of Vh/2, then when the horizontal synchronizing signal in FIG. 10a is in the period b, the horizontal position Output of adjustment circuit 3, that is, connection point w
The deflection voltage signal obtained at this point is at zero potential.

Further, when the horizontal synchronizing signal in FIG. 10a is in period a, transistor 32 is turned on, and transistors 52, 57, and 61 are respectively turned off. At this time, the deflection voltage signal supplied from the sawtooth wave generation circuit 2 to the horizontal position adjustment circuit 3 by turning on the transistor 32 is inverted and level-shifted by the horizontal position adjustment circuit 3. In this way, a deflection voltage signal as shown in FIG. 10d is obtained at the output of the horizontal position adjustment circuit 3, that is, at the connection point w. The output of the horizontal position adjustment circuit 3 is then supplied to the linearity corrector 4, where
The amount of movement of the spot on the fluorescent surface ₆₂ of OFT 6 is corrected to be constant, as shown in Fig. 10e.
The waveform becomes as follows and is supplied to the electromagnetic deflection amplifier circuit 5.

() And the electromagnetic deflection amplifier circuit 5 of this invention
The voltage waveform at the connection point j is shown in FIG. 10f, and the current waveform supplied to the connection point k is shown in FIG.
It is shown in Figure g. First, let the current required for the deflection angle θ [rad] of the electron beam of OFT6 be I [A] (θ = α・I, α: constant), and then the time required for the deflection current to become O [A] as shown in Fig. 10g. When t=t ₁ in the waveform, the deflection current Im(t) is required to be Im(t) = 1/αtan ⁻¹ [−α·I ₀ /t ₁ (t−t ₁ )]. However, I ₀ is the current before correction when t=t ₀ , -αI ₀ /t ₁ is the deflection current “0” [A]
The slope of the current waveform in the vicinity, ta ^-1 [-αI ₀ /t ₁ (t-
t ₁ )] is a value corrected so that the amount of spot movement on the flat tube surface 6 ₂ of the OFT 6 is constant. In other words, for the deflection yoke 6 ₁ , Im(t)=1/
In order to flow a current of α・tan ⁻¹ [−αI ₀ /t ₁ (t−t ₁ )], the resistance values of resistors 10, 17, and 18 are set to r ₁ , r ₂ , r _{3 ,} respectively, at the connection point x. Then, Vx(t)=
r ₂・r ₁ /α・r ₃・tan ^-1 [−αI ₀ /t ₁・(t−t ₁ )]
The voltage is corrected by the linearity corrector 4 so that it is input to the electromagnetic deflection amplifier circuit 5.

In the electromagnetic deflection amplifier circuit 5, the power supply 95 turns on the transistor 93 when the output of the operational amplifier 11 becomes a positive potential, and turns on the resistor 17.
Deflection voltage Vx(t) to which the voltage generated at is input
When feedback starts to be applied corresponding to (when the connection point y is "0" [V]), the transistor 9
3 is selected as the electromotive voltage that turns off. Power supply 1
4 and 15, when the connection point y is “0” [V],
The voltage required to drive the deflection yoke ₆₁ is selected, and the power source 82 is connected to the power source 14,1.
The electromotive voltage is higher than that of 5.95, and the 4th
This is a power supply that is supplied to shorten the retrace period l in the signal shown in FIG.

By the way, the time t shown in the signal in Fig. 10g =
When −t ₀ , the electromagnetic deflection amplifier circuit 5 has Vx (−t ₀ )=r ₂・r ₁ /α・r ₃ tan ⁻¹ [−αI ₀ /t ₁ (
−t ₀ −t ₁ )], the voltage generated across the resistor 17 is increased by the inductance of the deflection yoke 6 ₁ to Vx
As a result, a potential difference occurs between the input terminals of the operational amplifier 11, and the output voltage of the operational amplifier 11 has a value close to the positive operating power supply voltage. Therefore, the transistors 93, 80, and 12 are conductive, the diodes 96, 70, and 76 are non-conductive, and the diode 83 is conductive, and a voltage close to the electromotive voltage of the power supply 82 is output to the connection point j. In this case, it is assumed that the collector-emitter saturation voltage of transistors 80 and 12 and the voltage drop of diode 83 are sufficiently smaller than the electromotive voltage of power supply 82. When the electromotive voltage of the power supply 82 is output to the connection point j, the current _I1 shown in FIG. Point y is “0” [V]
) The electromotive voltage of the power supply 82 is input to the connection point j. The point at which voltage-current conversion becomes stable is t
= 0, and if the deflection current at that time is i ₀ , then the retrace period l is: l=0-(- _t1 )=L/R+r・log[1
/1−i ₀ (R+r)/E ₃ ]. In this case, R is the resistance value of resistor 17, L
is the inductance component of the deflection yoke 6 ₁ , r is the resistance component of the deflection yoke 6 ₁ , and E ₃ is the electromotive force of the power source 82 . In other words, the power supply 82 is used only during the retrace period l.
By supplying an electromotive voltage of , the retrace period l is shortened.

After that, feedback is applied so that the connection point y becomes "0" [V], so the output of the operational amplifier 11 is the deflection current Im(t), Im(t) = I/αtan ^-1 [-αI ₀ /t ₁ (t-t ₁ )], and the transistor 9
3, 80 are non-conductive, diodes 96, 70, 7
6 becomes conductive and the diode 83 becomes non-conductive, and a voltage close to the electromotive voltage of the power supply 14 is supplied to the collector of the transistor 12. This means that t=t ₁ ,
This continues until im=“0” [A], and the current I ₁ shown in FIG. 3 flows. Also, from t=t ₁ to t=t ₂
Until then, transistor 12 is off, transistor 13 is on, and current I ₂ shown in FIG. 3 flows. Now, in order to output the deflection current Im(t)=I/αtan ^-1 [-αI ₀ /t ₁ (t-t ₁ )] to the deflection yoke 6 ₁ , the following voltage is applied to the connection point j. Is required. That is, if the voltage at connection point j is Ej (t), then Ej (t) = LdIm (t) / dt + (R + r) Im (t) =
-L・I ₀ /t ₁ /1 + [αI ₀ /t ₁ (t-t ₁ )] ² + (R+r) / αtan ^-1 [-αI ₀ /t ₁ (t-t
₁ )] is maximum when t = “0”, and t
= t ₂ (see signal in FIG. 10f). In other words, the electromotive voltage of the power supply 14 is “Ej(o)+
The deflection yoke 6 ₁ can be driven if the voltage between the collector and emitter of the transistor 12 + the forward voltage of the diode 76 is higher than the voltage.
If the electromotive voltage of the power supply 15 is greater than "Ej(o) + collector-emitter voltage of the transistor 12 + forward voltage of the diode 76", the deflection yoke 6 ₁
can be driven. Further, if the electromotive voltage of the power supply 15 is equal to or less than "Ej (t ₂ ) - the collector-emitter voltage of the transistor 13", the deflection yoke 6 ₁ can be driven.

Regarding the electromotive force of the power supply 95, when the deflection current starts to have a feedback corresponding to the input terminal voltage Vx (t), the output of the operational amplifier 11 is "Ej (o) + the base-emitter voltage of the transistor 12 + the resistance. 71+forward voltage of diode 70", the transistor 93 is cut off at this time, and the transistor 93 is cut off during the retrace period (when the output of the operational amplifier 11 is a positive operating power supply voltage).
is held to keep it on.

Here, the electromotive force of the power source 15 is E ₂ , and the voltage of the power source 82 is E 2 .
The electromotive voltage of the power source 14 is E ₃ , the electromotive force of the power source 14 is E ₄ ,
The relationship among E ₂ , E ₃ , and E ₄ will be specifically shown.

First, set the effective scanning period of OFT6 to 210 [mm] (however, deflection angle θ = ±0.45 [rad]), and set the scanning period to
800 [μs] (t ₁ = 400 [μs] t ₂ = 800 [μs])
,
The inductance component of deflection yoke 6 ₁ is 400
[μH], the resistance component of the deflection yoke ₆₁ is 0.6 [Ω],
Deflection angle θ when scanning time t = 0 = 0.45 [rad]
If the deflection current required for this is Im(o) = 1.5 [A], and the voltage drop due to various transistors and diodes is 1 [V], then the deflection angle θ = 0.45
The deflection current required for [rad] is Im(o) = 1.5 [A]
Therefore, from θ=α·Im(o), α=θ/Im(o)=0.45/1.5=0.3 [rad/A]. Also, Im(o)=1/α・tan ^-1 (α・
I ₀ ), I ₀ = 1/αtanα・Im(o) = 1/0.3tan (0.3×0.15)≒1.61 [A], which means that the time t before linearity correction is
Corresponds to the current at zero. Therefore, the deflection current
Im(t), Im(t)=1/0.3tan ^-1 [-0.3×1.61/400・(t-
400)], the electromotive force E ₄ of the power supply 14 is E ₄ > Ej (o) + 2 = -1.61/1 + (0.3 x 1.61) ² + (1 + 0.6) / 0.3・tan ^-1 ( 0.3×1.61)+2≒3 [V], and the electromotive force _E2 of the power supply 15 is _E2 <Ej( _t2 )−1 =−1.61/1+(0.3×1.61) ²⁺ (1+0.6) /0.3
- Select tan ^-1 (0.3×1.61)-1≒-5.7 [V] and select a resistance constant that can drive a deflection current of -1.5 [A].

Now, if the electromotive force E ₄ of the power supply 14 is used as the voltage supply source during the retrace period l, and if E ₄ is 5 [V] (5 [V] > 3 [V]), (if E ₄ is increased, the transistor 12 power consumption increases), retrace period l is: l=L/R+r・log [1/1−Im(o)・(R+r)
_{/E4〕=400/1+0.6}・log(1/1-1.5×1.6/5)
≒71 [μs], and the time equivalent to about 1/10 of effective scanning is wasted time. If E ₃ =50 [V] is supplied only during this period, the retrace period l≈5.3 [μs], and the horizontal scanning period (period a in Fig. 10a) is shortened to reduce wasted time. This allows the number of horizontal scans to be increased, and by increasing the dot density, it is possible to output smooth Chinese characters. Moreover, the effective scanning period can be reduced from 800 [μs].
By increasing the length to 860 [μs], the amount of light per unit area on the fluorescent surface ₆₂ of the OFT 6 can be increased.

By the way, when the scanning ends when t= _t2 , the period _l0 until the deflection current Im( _t2 ) becomes 0 [mA] is the inverting input terminal (-) of the operational amplifier 11.
Transistors 93, 8 based on the potential difference generated between
Since the voltage E 3 from the power supply 82 applied to the connection point j by turning on the terminals 0 and 12 and the back electromotive force generated when the deflection current is briefly cut off have the same polarity, the voltage E ₃ from the retrace period l will also be shorter. However, during this period l ₀ , almost no collector current flows through the transistor 80, so the cut-off of the transistor 80 is delayed due to the charge accumulated in the base, and the deflection current becomes 0 [A], corresponding to the input voltage. Even if the transistor 93 is cut off, a small amount of current I ₁ flows through the deflection yoke 6 ₁ . Then, the voltage generated across the resistor 17 becomes higher than the input deflection voltage Vx and acts in the opposite direction to the retrace line, causing the output of the operational amplifier 11 to have a value close to the negative operating power supply voltage. When cut off, the transistor 39 turns on, and the deflection current flows through the deflection yoke ₆₁ .
A current flows in the opposite direction to I ₁ , reducing the deflection current I ₁ to 0
It works as [A]. Therefore, it is necessary to draw out the charge accumulated in the base of the transistor 80 to quickly turn off the transistor 80. Therefore, the transistors 85 and 8
A circuit consisting of transistors 80 and 80 is provided.
When transistor 93 is turned on and transistor 93 is cut off, transistors 85 and 88 are turned on to extract the charge stored on the base of transistor 80.

Therefore, a newly installed power supply with a large capacity is turned on during the retrace period during OFT scanning, so the retrace period can be shortened without increasing power loss compared to the case of a single power supply.
This makes it possible to increase the number of horizontal scans,
By increasing the dot density of characters, smooth characters can be printed. Moreover, since the effective scanning period can be lengthened by shortening the retrace period, it is possible to increase the amount of light per unit area, and it is possible to maintain sufficient print density even with a small cathode current. In other words, the life of the cathode can be extended.

() On the other hand, if the transistor 27 is destroyed and becomes an open state, or if the transistor 27 continues to be cut off, the output of the operational amplifier 21 becomes a voltage close to the positive operating power supply voltage, and the electromagnetic deflection amplifier circuit 5 is input with a higher than normal voltage and a correspondingly large deflection current
Since I ₁ flows, the power consumption of the transistor 12 increases, resulting in a problem that the transistor 12 may be destroyed.

Therefore, when the output voltage of the operational amplifier 21 exceeds the voltage corresponding to effective horizontal scanning (the peak value Vz of the signal in FIG. 10b), the Zener diode 64 is made conductive, thereby causing the transistor 5
Turn on 7, 61, and 67. Then, the connection point t
The voltage V ₃ is suppressed to V ₃ ≈(+V)·r ₂ /r ₁ +r ₂ as in the case where the scanning is made to wait at the center position of the fluorescent surface 6 ₂ of the OFT 6 as described above. In this case, r ₁ and r ₂ are resistors 41,
It is assumed that the resistance value is 42, which is sufficiently smaller than the resistance value r/2. Also, unlike when the horizontal synchronizing signal is in period b, the voltage at connection point q continues until the integral waveform reaches the positive operating power supply voltage of the operational amplifier 21, and is then held at the positive operating power supply voltage, so that the horizontal The deflection current increases slightly compared to when the synchronization signal is in period b, or it is a value that can be ignored compared to the current before suppression. Even if the transistor 27 continues to be in the cut-off state, almost no deflection current is allowed to flow, thereby suppressing an increase in power consumption and also preventing damage to various circuit elements.

() Furthermore, the static characteristics of OFT6 are shown in FIG. That is, when the accelerating grid voltage, that is, the second grid voltage Ec ₂ is 250 [V], if the cathode voltage (video signal voltage) becomes 0 [V],
The beam current Ib starts to flow when the first grid voltage Ec ₁ is about -70 [V];
This increases as the grid voltage _Ec1 increases, meaning that the brightness of the fluorescent surface ₆₂ increases. In reality, however, the range of brightness variation is limited in consideration of the lifespan of the cathode. In other words, in this case, the brightness variable range of OFT6 is −V _A of the first grid voltage Ec ₁
It corresponds to [V] to -V _B [V]. When the video signal supplied to the cathode of the OFT 6 is 0 [V], an electron beam is emitted from the electron gun of the OFT 6 to the fluorescent surface 6 ₂ so that a predetermined spot on the fluorescent surface 6 ₂ emits light. It's summery.

Therefore, here, when the horizontal scanning of the OFT 6 is stopped, the second grid voltage Ec ₂ is shifted from the predetermined luminance variable range. In other words, when the horizontal scanning of OFT6 stops, the second grid voltage Ec ₂ is changed from 250 [V] to
I am trying to switch it to 100 [V]. 7 and 8, the base-emitter voltage of the transistor 102 is V _be , the amplification factor is h _fe , the electromotive force of the power supply 103 is V _b , the resistors 112, 111,
The resistance values of 110 and 109 are r ₁ , r ₂ , r ₃ ,
r ₄ , the second grid voltage Ec ₂ is Ec ₂ = [300/r ₁ +V _be /r ₃・(h _fe +1) + V _be −V _b /r
₄・h _fe ]/1/r ₁ +1/r ₃・(h _fe +1). Thus, the second grid voltage
Various elements are selected so that Ec ₂ is 250 [V].

Now, when the horizontal scanning of the OFT 6 is stopped because the horizontal synchronizing signal input to the input terminal s is for period b (zero potential), the transistor 52 is turned on by turning off the transistor 32, and as a result, the transistor 101 is turned on. Turn off. Then,
The transistor 102 turns on, and the second grid voltage Ec ₂ becomes Ec ₂ ≒300·r ₂ r ₃ /r ₁ +r ₂ r ₃ , and the second grid voltage Ec ₂ becomes 100 [V].
become. In this case, the base-emitter voltage and collector-emitter voltage of transistor 102 are sufficiently small and are therefore ignored.

By the way, if the transistor 27 of the sawtooth wave generation circuit 2 is destroyed for some reason and becomes an open state, or if a low potential signal is always input to the transistor 27 and the transistor 27 continues to be in the cut-off state, the above-mentioned situation will occur. As shown above, period a (high potential) of the horizontal synchronizing signal
Horizontal scanning of OFT6 is stopped regardless of the
At this time, the transistor 67 is turned on based on the conduction of the Zener diode 64, which turns off the transistor 101, and the second grid voltage _Ec2 becomes 100 [V] as described above.

Therefore, the accelerating grid voltage, that is, the second
By switching the grid voltage from 250 [V] to 100 [V], the output stage buffer of the video amplifier circuit is destroyed and its output (video signal) becomes 0.
[V], the second grid voltage Ec ₂
OFT6 is out of the brightness variable range.
The electron beam is cut off, and the fluorescent surface ₆₂ does not emit light. In other words, it is possible to prevent the fluorescent surface 6 ₂ of the OFT 6 from being burned out.

Furthermore, the cut-off voltage at the second grid voltage Ec ₂ =250 [V] of the static characteristics shown in FIG.
Ec ₀ is -75 [V], but the cut-off voltage Ec ₀ varies depending on the type of OFT, and there are some that vary by about 50 [V].
Depending on the type of OFT, the static characteristics shown in FIG. 11 must be shifted depending on the cut-off voltage Ec ₀ . Now, when the first grid voltage Ec ₁ is varied from -V _A to -V _B , -V A and -V _B are changed without changing "V _B - V _A " (luminance variable range).
V _B must be shifted respectively. In other words, if the first grid voltage Ec ₁ is fixed,
Even if the second grid voltage Ec ₂ is 250 [V], the brightness differs depending on each OFT, and even if the second grid voltage Ec ₂ is set to 100 [V], the electron beam cannot be cut off. . Therefore, in FIG. 9, the Zener diode 12
2 to generate "V _B -V _A ", and further vary -V _B by varying the variable resistor 124, the first
It is possible to shift the grid voltage Ec ₁ by “-V _B −V _A ”.

In the above embodiment, the deflection current is varied by turning on and off the DC power source 82. For example, if the DC power source 14 is selected in advance to have a large capacity, then the DC power source 14 is
A similar effect can be obtained even if the deflection current is varied by controlling the output of 4 with a thyristor or the like. In addition, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

As described above, according to the present invention, the above-described configuration detects whether or not a potential difference has occurred between the deflection voltage and the feedback voltage, and changes the deflection current to the deflection coil according to the detection result. Since it is made variable, it is possible to provide an extremely practical electromagnetic deflection amplification circuit for a cathode ray tube that can shorten the retrace period in deflection scanning of an electron beam of a cathode ray tube without increasing power loss.

[Brief explanation of the drawing]

Fig. 1 is a diagram schematically showing the general configuration of a drive circuit and video amplification circuit for an optical fiber recording tube, Fig. 2 is a signal waveform diagram of each part of Fig. 1, and Fig. 3 is a conventional electromagnetic deflection amplification circuit. The configuration diagram of the circuit, Figure 4 is a signal waveform diagram of each part of Figure 3, Figure 5 is a diagram of the configuration of a conventional sawtooth wave generation circuit, Figure 6 is a signal waveform diagram of each part of Figure 5, and Figure 7. 11 to 11 are for explaining one embodiment of the present invention, FIG. 7 is an overall configuration diagram of a drive circuit including an electromagnetic deflection amplifier circuit of the present invention, and FIGS. 8 and 9 are grid diagrams. FIG. 10 is a diagram of the configuration of the voltage control circuit, FIG. 10 is a signal waveform diagram of each part of FIG. 7, and FIG. 11 is a diagram of static characteristics of the optical fiber recording tube. 2... Sawtooth wave generation circuit, 3... Horizontal position adjustment circuit, 4... Linearity corrector, 5... Electromagnetic deflection amplifier circuit, 6... Cathode ray tube (optical fiber recording tube),
6 ₁ ... Deflection yoke, 6 ₂ ... Fluorescent surface.

Claims (1)

[Claims] 1 A deflection current is supplied to the deflection coil of the cathode ray tube based on the deflection voltage input in response to the deflection synchronization signal, and a voltage corresponding to the deflection current is fed back to the input side, thereby deflecting the electron beam of the cathode ray tube. The electromagnetic deflection amplification circuit of the cathode ray tube to be scanned includes a detection means for detecting whether or not a potential difference has occurred between the deflection voltage and the feedback voltage, and a first detection means for deflecting and scanning the electron beam of the cathode ray tube. A power supply, a second power supply whose absolute value is higher in potential than the first power supply, and a switch circuit that controls switching between the first power supply and the second power supply according to the detection result of the detection means. An electromagnetic deflection amplification circuit for a cathode ray tube.