JPS63160404A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

Info

Publication number
JPS63160404A
JPS63160404A JP30641286A JP30641286A JPS63160404A JP S63160404 A JPS63160404 A JP S63160404A JP 30641286 A JP30641286 A JP 30641286A JP 30641286 A JP30641286 A JP 30641286A JP S63160404 A JPS63160404 A JP S63160404A
Authority
JP
Japan
Prior art keywords
control circuit
offset
circuit
signal
gain control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30641286A
Other languages
Japanese (ja)
Inventor
Kohei Ishizuka
石塚 幸平
Taku Harada
卓 原田
Katsuyuki Nagano
長野 克之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP30641286A priority Critical patent/JPS63160404A/en
Publication of JPS63160404A publication Critical patent/JPS63160404A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent malfunction of a gain control circuit in response to an offset control circuit by adding a band limit circuit to the gain control circuit. CONSTITUTION:An input signal is inputted to a variable gain amplifier 1 and outputted from an output signal terminal 8. The variable gain amplifier 1 is added with the offset control circuit 2 to compensate the deviation of the operating point due to the input offset fluctuation and the DC fluctuation caused equivalently at the output signal terminal 8 is fed back to the input side to apply offset control. A clamp circuit 3 clamps high or low level of the output signal and since the offset fluctuation by the operation of the offset control circuit 2 is added to the signal, then the fluctuation component is eliminated by a band limit circuit 4. Then the signal peak value by a peak value detection circuit 5 is detected, it is compared with a reference signal amplitude by the gain control circuit 6, the difference signal is amplified and integrated and inputted to the variable gain amplifier 1 as the gain control signal. Thus, the gain control circuit does not receive the effect due to offset fluctuation and no malfunction takes place.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電気信号の出力振幅を一定に制御する自動利
得側#に関するものであり、4!に入力信号マーク率の
変動に対して好適な特性を有する自動利得制御回路に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an automatic gain side # that controls the output amplitude of an electrical signal to be constant. The present invention relates to an automatic gain control circuit having characteristics suitable for variations in input signal mark rate.

〔従来の技術〕[Conventional technology]

本発明は自動利得制御回路に用いる可変利得増幅器にオ
フセット制御機能を有している場合の利47!llJ#
回路の構成に関するものである。従来の利得制御回路と
して特開昭57−138208号公報が挙げられる。こ
の従来技術の場合には、受信電力を求めて利得制御を行
なりているが、制御信号を優る場合に、信号の帯域につ
いて利得制御回路では配慮されていなかった。
The present invention provides a gain of 47! when a variable gain amplifier used in an automatic gain control circuit has an offset control function. llJ#
This relates to the configuration of the circuit. A conventional gain control circuit is disclosed in Japanese Patent Laid-Open No. 138208/1983. In the case of this prior art, gain control is performed by determining the received power, but the gain control circuit does not take into account the band of the signal when it is superior to the control signal.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

利得制御回路は、本来入力信号の大小によらず信号出力
を一定値に制御しようとするものであるが、この制御信
号を優る場合に%可変利得増幅器にオフセット制御回路
が付加されている場合にはこの応答について配慮する必
要があり、入力信号のマーク率(’o1.J#よりなる
信号列について全体く対する′1′の比率を示す)が変
動した場合。
A gain control circuit originally attempts to control the signal output to a constant value regardless of the magnitude of the input signal, but if this control signal is superior to the % variable gain amplifier and an offset control circuit is added. It is necessary to consider this response when the mark rate of the input signal (indicates the ratio of '1' to the whole for a signal string consisting of 'o1.J#) changes.

オフセット制御回路の応答により利得制御回路がd14
MIJ作してしまう問題があった。
The gain control circuit changes to d14 due to the response of the offset control circuit.
There was a problem with MIJ production.

本発明の目的はオフセット制御回路の動作に対して安定
な自動利得制御回路を提供することにある。
An object of the present invention is to provide an automatic gain control circuit that is stable in the operation of an offset control circuit.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は・、利得制御回路に帯域制限回路を付加する
ことKより、入力信号のマーク率変動に起因するオフセ
ット制御回路の動作による可変利得増幅器のオフセット
変動に対して、利得制御回路が応答しないようにすると
とKより達成される。
The above purpose is to add a band-limiting circuit to the gain control circuit, so that the gain control circuit does not respond to offset fluctuations of the variable gain amplifier due to the operation of the offset control circuit caused by fluctuations in the mark rate of the input signal. If you do this, K will be more achieved.

〔作用〕[Effect]

本発明による自動利得制御回路は次のように動作する。 The automatic gain control circuit according to the invention operates as follows.

入力信号は可変利得増副器に入力される。The input signal is input to a variable gain enhancer.

可変利得増幅器は、増幅度の大きい場合に入力オフセッ
ト変動による動作点のずれを補償するため。
Variable gain amplifiers are used to compensate for operating point shifts due to input offset fluctuations when the amplification degree is large.

オフセット制御回路が付加されている。このオフセット
制御回路は可変利得増幅器の差動出力信号により制御を
行なう。すなわち可変利得増幅器の差動出力の両方の平
均値を基準値とし、可変利得増幅器の一方の平均値との
差をとり誤差信号とする。この誤差信号を増幅し積分を
したのち、入力信号端子に帰還をかけ、誤差信号が零に
なるように1rlJ御を行なっている。この形式の場合
のオフセット制御回路は入力信号のマーク率によりて、
最適動作点は変動することになる。このオフセット変動
周波数は誤差信号の積分時定数によって決定される。オ
フセット変動の制御方法はここに述べたもの以外にも各
檀構成が考えられるが、いずれもオフセット変動の制御
が基本的には直流を含む低域の領域であれば、他の構成
でも本発明を適用することができる。
An offset control circuit is added. This offset control circuit performs control using differential output signals of the variable gain amplifier. That is, the average value of both of the differential outputs of the variable gain amplifier is used as a reference value, and the difference from the average value of one of the variable gain amplifiers is taken as an error signal. After amplifying and integrating this error signal, feedback is applied to the input signal terminal, and 1rlJ control is performed so that the error signal becomes zero. The offset control circuit in this format depends on the mark rate of the input signal.
The optimal operating point will vary. This offset fluctuation frequency is determined by the integration time constant of the error signal. Various configurations other than those described here are conceivable for controlling offset fluctuations, but the present invention can be applied to other configurations as long as the offset fluctuations are basically controlled in the low frequency range including direct current. can be applied.

可変利得増幅器出力の一部は出力振幅を一定値にするた
めクランプ回路によりハイレベルまたはローレベルをク
ランプする。このとき可変利得増幅器のオフセット変動
に追随しないように帯域制限をはとこす。オフセット制
御は基本的には直流制御であるが、帯域制限回路におい
ては直流しゃ断だけでなくオフセット制御回路積分時定
数に相当する帯域まで低域をしゃ断する形式とする。入
力信号成分にはオフセット制#による変動周波数成分が
ないことを利用したものであり言い換えれば完全に周波
数分離できることが本発明の特徴でありまた条件である
A part of the variable gain amplifier output is clamped at high level or low level by a clamp circuit in order to maintain the output amplitude at a constant value. At this time, band limitation is applied so as not to follow offset fluctuations of the variable gain amplifier. Offset control is basically DC control, but the band limiting circuit not only cuts off DC but also cuts off low frequencies up to a band corresponding to the integral time constant of the offset control circuit. This method takes advantage of the fact that the input signal component has no variable frequency component due to the offset system.In other words, it is a feature and condition of the present invention that frequency can be completely separated.

この信号をピーク値検出し、基準信号振幅と比較し、差
信号を増幅、S分をしたのち利得制御信号として、可変
利得増幅器の利得制御端子に入力する。
The peak value of this signal is detected, compared with the reference signal amplitude, and the difference signal is amplified and divided by S, and then input as a gain control signal to the gain control terminal of the variable gain amplifier.

この回路構成により本回路は自動利得制御回路として動
作する。り2ンプ回路において、帯域制限をすることK
より、利得制御回路ではオフセット変動による影響を受
けることがなく、誤動作することはない。
With this circuit configuration, this circuit operates as an automatic gain control circuit. In the 2-amp circuit, it is important to limit the bandwidth.
Therefore, the gain control circuit is not affected by offset fluctuations and does not malfunction.

〔実施例〕〔Example〕

以下、本発明の一実施例を′m1図により説明する。入
力信号は入力信号端子7より利得な可変できる可変利得
増幅器1に入力され、出力信号端子8より出力される。
Hereinafter, one embodiment of the present invention will be explained with reference to Figure 'm1. An input signal is inputted to a variable gain amplifier 1 whose gain can be varied through an input signal terminal 7 and outputted from an output signal terminal 8.

oT変利得増幅器1は入力オフセット変動による動作点
のずれを補償するため。
The oT variable gain amplifier 1 is used to compensate for shifts in the operating point due to input offset fluctuations.

オフセラ)?ff1j#回路2が付加されており、等測
的に出力1B号端子8に生じた直流変動分を入力1gI
JK帰還してオフセット制御を行なう。
offsera)? ff1j# circuit 2 is added, and the DC fluctuation generated isometrically at the output 1B terminal 8 is input to the input 1gI.
Returns to JK and performs offset control.

り2ンプ回路3.螢域制限回路4・ピーク値検出回路5
.利得?ffIIa1回路6は出力信号端子8の信号m
l@を一定値に制御する動作を行なうものである。クラ
ンプ回路3は、出力信号のハイレベルまたはローレベル
をクランプする。この信号には、オフセット制御回路2
の動作によるオフセット変動分も加わっているため、こ
の変動分を帯域制限回路4により除去する。さらKこの
利得制御系では、信号成分のみが必要であるので、不要
な高域の帯域外の雑音等の信号を除去することも、安定
な利得制御を行なうために必要な場合もある。このり2
ンプ回路3と帯域制限回路4は信号処理が逆になっても
問題はない。
2 amplifier circuit 3. Firefly area limiting circuit 4/peak value detection circuit 5
.. gain? The ffIIa1 circuit 6 receives the signal m at the output signal terminal 8.
It performs an operation to control l@ to a constant value. The clamp circuit 3 clamps the high level or low level of the output signal. This signal includes an offset control circuit 2
Since the offset fluctuation due to the operation is also added, this fluctuation is removed by the band limiting circuit 4. Furthermore, since this gain control system only requires signal components, it may be necessary to remove signals such as unnecessary high frequency out-of-band noise in order to perform stable gain control. Konori 2
There is no problem even if the signal processing of the amplifier circuit 3 and the band limiting circuit 4 is reversed.

フラング回路5.帯域制限回路4を通った信号はピーク
値検出回路5により、信号のピーク値が検出され、利得
制御回路6で、基準信号振幅と比較し、その差信号を増
幅、積分し、利得制御信号として可変利得増幅器1の利
得制御端子に入力させることKより自動利得制御のルー
ズが形成される。
Flang circuit 5. A peak value detection circuit 5 detects the peak value of the signal that has passed through the band limit circuit 4, and a gain control circuit 6 compares it with the reference signal amplitude, amplifies and integrates the difference signal, and outputs it as a gain control signal. The automatic gain control loop is formed by inputting K to the gain control terminal of the variable gain amplifier 1.

り2ング回路3、ピーク値検出回路5は信号振幅を求め
るための回路であり、信号振幅を平均値で求める場合に
は平均値検出回路を用いればよい。
The averaging circuit 3 and the peak value detection circuit 5 are circuits for determining the signal amplitude, and when determining the signal amplitude as an average value, an average value detection circuit may be used.

この場合にも平均値検出を行なう前に帯域制限回路4を
挿入すれば1本発明と同様の効果がある。
In this case as well, if the band limiting circuit 4 is inserted before detecting the average value, the same effect as that of the present invention can be obtained.

〔@明の効果〕[@Ming effect]

以上に述べたごとく1本発明によれば、帯域制限回路4
においてa7変利得増幅器1のオフセット変動に追随し
ないようにオフセット制御回路積分時定数に相当する帯
域まで低域をしJPt!frすることにより、オフセッ
ト変動に対して利得側#回路は誤動作することがないの
で安定な自動詞41tlll@J回路を実現できる。
As described above, according to the present invention, the band limiting circuit 4
In order not to follow the offset fluctuation of the a7 variable gain amplifier 1, the low frequency band is adjusted to a band corresponding to the integral time constant of the offset control circuit.JPt! By using fr, the gain-side # circuit does not malfunction due to offset fluctuations, so a stable intransitive 41tllll@J circuit can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本光明の一実施例の自動利優制御回路を示す図
である。
FIG. 1 is a diagram showing an automatic profit control circuit according to an embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] オフセット制御回路を有する可変利得増幅器と、この出
力信号の振幅を一定値に制御する利得制御回路からなる
自動利得制御回路において、上記利得制御回路に帯域制
限回路を付加し、上記オフセット制御回路の応答に上記
利得制御回路の応答が追随しないように構成したことを
特徴とする自動利得制御回路。
In an automatic gain control circuit consisting of a variable gain amplifier having an offset control circuit and a gain control circuit that controls the amplitude of the output signal to a constant value, a band limiting circuit is added to the gain control circuit to control the response of the offset control circuit. An automatic gain control circuit characterized in that the automatic gain control circuit is configured such that the response of the gain control circuit does not follow the response of the gain control circuit.
JP30641286A 1986-12-24 1986-12-24 Automatic gain control circuit Pending JPS63160404A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30641286A JPS63160404A (en) 1986-12-24 1986-12-24 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30641286A JPS63160404A (en) 1986-12-24 1986-12-24 Automatic gain control circuit

Publications (1)

Publication Number Publication Date
JPS63160404A true JPS63160404A (en) 1988-07-04

Family

ID=17956706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30641286A Pending JPS63160404A (en) 1986-12-24 1986-12-24 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPS63160404A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292004A (en) * 1988-09-29 1990-03-30 Omron Tateisi Electron Co Adjusting device for electronic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0292004A (en) * 1988-09-29 1990-03-30 Omron Tateisi Electron Co Adjusting device for electronic circuit

Similar Documents

Publication Publication Date Title
KR970007983B1 (en) Receiver automatic gain control
JPS6215909A (en) Optical reception circuit
JPS63160404A (en) Automatic gain control circuit
EP1547241B1 (en) Dc-compensation loop for variable gain amplifier
JPH02246604A (en) Offset adjustment circuit for multi-stage differential amplifier
KR920005466A (en) Servo circuit
JP2001036351A (en) Power amplifier
KR0151414B1 (en) Automatic gain control circuit of image processing system
JPS5892149A (en) Detecting circuit for input electric field
JPH0265305A (en) Automatic gain control amplifier
JPS62140507A (en) Automatic gain control amplifier for offset compensation
JPH06244645A (en) Amplifier circuit
JPH0832384A (en) Apc circuit correspondent to burst wave
JPH0254629A (en) Transistor power amplifier
KR100193860B1 (en) Automatic gain control device with stable signal characteristics
JPH0638514Y2 (en) Optical receiver
JPH0421385B2 (en)
JP3012850B2 (en) Automatic gain control circuit
JPH03187599A (en) Sound output circuit
JPS5815347A (en) Automatic gain control system for optical reception circuit
JPH0258409A (en) Electric power control circuit for electric power amplifier
JPH047917A (en) Transmission power control circuit
JPH1197960A (en) Automatic gain control circuit
JPH04200006A (en) Gain control amplifier
JPH05121967A (en) Fet low noise amplifier