JPS63160363A - Semiconductor device with multilayer interconnection structure - Google Patents
Semiconductor device with multilayer interconnection structureInfo
- Publication number
- JPS63160363A JPS63160363A JP30982586A JP30982586A JPS63160363A JP S63160363 A JPS63160363 A JP S63160363A JP 30982586 A JP30982586 A JP 30982586A JP 30982586 A JP30982586 A JP 30982586A JP S63160363 A JPS63160363 A JP S63160363A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- wiring layer
- layer
- metal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 86
- 239000002184 metal Substances 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 238000001771 vacuum deposition Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 206010004950 Birth mark Diseases 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、半導体基板の上に絶縁膜を介して複数の金
属配線層が積層された多層配線構造を有する半導体装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device having a multilayer wiring structure in which a plurality of metal wiring layers are stacked on a semiconductor substrate with an insulating film interposed therebetween.
［従来の技術］
多層配線構造を有する半導体装置はコンピュータの部品
等によく用いられている。[Prior Art] Semiconductor devices having a multilayer wiring structure are often used in computer components and the like.
第２図は従来の技術によって形成された多層配線構造を
有する半導体装置の断面形状を示した図である。FIG. 2 is a diagram showing a cross-sectional shape of a semiconductor device having a multilayer wiring structure formed by a conventional technique.
シリコン基板の上に第１の絶縁膜層１が形成されている
。絶縁膜はシリコン窒化膜あるいはシリコン酸化膜で形
成される。第１の絶縁膜層１の上に第１の配線層２が形
成されている。第１の配線層２には金属２ａ２ａが並ん
でいる。金属２＄！２ａはアルミニウム配線である。第
１の配線ｍ２の上には第２の絶縁膜層３が形成されてい
る。第２の絶縁膜層３の上には第２の配線層４が形成さ
れている。第２の配ね層４には金属配線４ａ、４ｂが並
んでいる。第２図は金属配置１ｉｒ４ａおよび４ｂが金
属配線２ａと直交している部分の断面図である。最上層
である第２の配線層４は、パッジベージｉンＦ３５によ
り外界から保護すれている。A first insulating film layer 1 is formed on a silicon substrate. The insulating film is formed of a silicon nitride film or a silicon oxide film. A first wiring layer 2 is formed on the first insulating film layer 1 . In the first wiring layer 2, metals 2a2a are lined up. Metal 2$! 2a is an aluminum wiring. A second insulating film layer 3 is formed on the first wiring m2. A second wiring layer 4 is formed on the second insulating film layer 3 . Metal wirings 4a and 4b are lined up in the second arrangement layer 4. FIG. 2 is a cross-sectional view of a portion where the metal arrangements 1ir4a and 4b are orthogonal to the metal wiring 2a. The second wiring layer 4, which is the uppermost layer, is protected from the outside world by a padding board F35.
ところで、多層配線構造を有する半導体装置では、各金
属配線２ａ、４ａ、４ｂに電流が流れると、絶縁膜３が
誘電体となり、各金属配線が電極となって、コンデンサ
が形成される。By the way, in a semiconductor device having a multilayer wiring structure, when a current flows through each metal wiring 2a, 4a, 4b, the insulating film 3 becomes a dielectric, each metal wiring becomes an electrode, and a capacitor is formed.
このコンデンサの容量が大きくなると、配線の時定数（
容量×抵抗）が大きくなり、結果として信号伝達速度が
遅くなる。信号伝達速度の遅い半導体装置を、たとえば
、コンピュータの部品として使うと、コンピュータの８
１Ｉ算速度は遅くなる。As the capacitance of this capacitor increases, the wiring time constant (
(capacitance×resistance) becomes large, resulting in a slow signal transmission speed. For example, if a semiconductor device with a slow signal transmission speed is used as a computer component, the computer's 8
1I calculation speed becomes slower.
それゆえ、コンピュータの高性能化を図るためには金属
配置間に生じるコンデンサの容量を少なくしてやる必要
がある。Therefore, in order to improve the performance of computers, it is necessary to reduce the capacitance of capacitors that occur between metal locations.
第２図に示す半導体装置の場ｈ、金属２８！４ａあるい
は４ｂの持つ単位長さあたりの？７ｆｆｉは次式％式％
上式において、ε。：真空中のｔＲ電率ε′ ：第２層
絶縁ｌ１ｌＩ３の誘電率ε“：パッシベーション！１１
５の
誘電率
込 ：金属配線の幅
立′ 二金属配線間のスペース
ｔｌ ；第２層絶縁膜３の厚さ
く２ ：金属配線の厚さ
である。In the case of the semiconductor device shown in FIG. 2, what is the per unit length of the metal 28!4a or 4b? 7ffi is the following formula % Formula % In the above formula, ε. : tR electric constant ε' in vacuum : Permittivity ε of second layer insulation l1lI3 : Passivation!11
Including dielectric constant of 5: Width of metal wiring 'Space tl between two metal wirings: Thickness of second layer insulating film 3 2: Thickness of metal wiring.
金属配線の容量を低減する方法としては、下記の４項目
が考えられる。The following four methods can be considered as methods for reducing the capacitance of metal wiring.
（１） 絶縁膜３の１１１Ｉ厚く【、）を厚くする。(1) Increase the thickness of 111I of the insulating film 3 [,).
（２〉 誘電率（ε′、ε“）の低い絶縁膜を選ぶ。(2> Select an insulating film with a low dielectric constant (ε', ε'').
（３） 金属配線間の間隔（見′）を大きくする。(3) Increase the spacing (apparent distance) between metal wires.
（４） 金属配線間の膜厚（ｔ２）を薄くする。(4) Reduce the film thickness (t2) between metal interconnects.
［発明が解決しようとする問題点］
前記（１）の第２の絶縁１１！＠３の絶縁膜３の膜厚（
ｔ、）を厚くする方法を採用した場合、第２層配線層４
内にある金属配置！４ａ 、４ｂとシリコン基板を、お
よび第２層配線層４内にある金属配線４ａ、４ｂと第１
層配線層２内にある金属配線２ａを、接続するために形
成されるコンタクト孔の深さが非常に深くなり、微細コ
ンタクトの形成が困難となる。[Problems to be solved by the invention] The second insulation 11 of (1) above! Film thickness of insulating film 3 of @3 (
t,), the second wiring layer 4
Metal arrangement inside! 4a, 4b and the silicon substrate, and the metal wirings 4a, 4b in the second wiring layer 4 and the first
The depth of the contact hole formed to connect the metal wiring 2a in the wiring layer 2 becomes very deep, making it difficult to form fine contacts.
前記（２）の低Ｍ電率の絶縁膜を選ぶ方法では。In the method (2) of selecting an insulating film with a low M electric constant.
現在半導体装置で使用されかつ信頼性ある絶縁膜として
知られるシリコン窒化膜およびシリコン酸化膜以外の絶
縁膜を用いな（ブればならない。しかし、これら以外に
優れたものがないのが現状である。It is necessary to use insulating films other than silicon nitride and silicon oxide, which are currently used in semiconductor devices and are known to be reliable insulating films. .
前記〈３）の金属配線容量の間隔（ｆＬ’ ）を大きく
する手段には、金属配線４ａ 、４ｂの線幅〈庭）を細
くするか、あるいは線幅（庭）はそのままにしておいて
金属配線Ｆ５隔（見′）を大きくするか、の２通りが考
えられる。しかし、前者の方法では金属配線の断面積（
ｔ２Ｘｆｌ）が小さくなる結果、抵抗が大きくなったり
、Ｉｇｉ線等の問題が生じる。Means for increasing the spacing (fL') between the metal wiring capacitances in <3) above include reducing the line width (field) of the metal wirings 4a and 4b, or leaving the line width (field) as it is and increasing the metal wiring capacitance (fL'). There are two possible ways to do this: increase the distance between the wiring F5 (see); However, in the former method, the cross-sectional area of the metal wiring (
t2Xfl) becomes smaller, resulting in increased resistance and problems such as Igi lines.
また、後者の方法は半導体装置の高ａｈａ化に反する方
向である。Moreover, the latter method is against the trend of increasing the AHA of semiconductor devices.
前記（４）の金属配線の１１１１ｆ（１２）を薄くする
手段も、前記（３）で述べた線幅〈庭）を細くする場合
と同様に、金属配線の抵抗増加・断線等の問題を招来す
る。The method of thinning the metal wiring 1111f (12) in (4) above also brings about problems such as increased resistance and disconnection of the metal wiring, similar to the case of thinning the line width described in (3) above. do.
以上のように従来の半導体装置では、金属配線の持つ容
量を低減するための良い方法がなかった。As described above, in conventional semiconductor devices, there has been no good method for reducing the capacitance of metal wiring.
この発明は上記のような問題点を解決するためになされ
たもので、高集積度を保ちかつ金属配線の抵抗増大・断
線等の問題を発生させずに金属配線容量を減少すること
ができる、多層配線構造を有する半導体装置を提供する
ことを目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to maintain a high degree of integration and reduce metal wiring capacitance without causing problems such as increased resistance or disconnection of metal wiring. An object of the present invention is to provide a semiconductor device having a multilayer wiring structure.
［問題点を解決するための手段］
この発明は、半導体基板の上に絶縁膜を介して槽数の金
属配線層が４ａ層された、多層配線構造を有する半導体
装置に係るものである。[Means for Solving the Problems] The present invention relates to a semiconductor device having a multilayer wiring structure in which 4a metal wiring layers are formed on a semiconductor substrate via an insulating film.
そして前記問題点を解決するために、該絶縁膜を介して
配置された第１の金属配線層と第２の金属配線層のうち
の、該第２の金属配線層内にある合成！ｉ’ｉ！線の断
面形状を、該第１の金属配線層に向き合う辺がそれに対
向する辺よりも矧くなった、台形形状にしている。In order to solve the above-mentioned problem, a combination of the first metal wiring layer and the second metal wiring layer arranged in the second metal wiring layer with the insulating film interposed! i'i! The line has a trapezoidal cross-sectional shape in which the side facing the first metal wiring layer is more slender than the side facing the first metal wiring layer.
［作用］
絶縁膜を介して配置された第１の金腐配ｍ層と第２の金
属配線層のうちの、該第２の金属配線層内にある金属配
線の断面形状は、該第１の金属配線層に向き合う辺がそ
れに対向する辺よりも短くなった台形形状であるので、
高集積度は保たれ、金属配線の抵抗増大・断線等の問題
を発生させずに、金属の配線の容量を減少させることが
できる。[Function] The cross-sectional shape of the metal wiring in the second metal wiring layer of the first metal wiring layer and the second metal wiring layer arranged through an insulating film is the same as that of the first metal wiring layer. Since it has a trapezoidal shape with the side facing the metal wiring layer shorter than the side opposite it,
A high degree of integration is maintained, and the capacitance of the metal wiring can be reduced without causing problems such as increased resistance or disconnection of the metal wiring.
［実施例］
以下、図面に示した実施例に基づいて本発明の詳細な説
明する。[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings.
第１図はこの発明に係る多層配線構造を有する半導体装
置の断面図である。このような断面を有する多層配線構
造を有する半導体装置を作る方法を説明する。FIG. 1 is a sectional view of a semiconductor device having a multilayer wiring structure according to the present invention. A method for manufacturing a semiconductor device having a multilayer wiring structure having such a cross section will be described.
まず、シリコン基板の上に第１の絶縁層１、第１の金属
配線層２、および第２の絶縁膜層３を順次形成する。First, a first insulating layer 1, a first metal wiring layer 2, and a second insulating film layer 3 are sequentially formed on a silicon substrate.
引き続いて、第２の金属配線層４の材料であるアルミニ
ウムを表面全体に真空蒸着等により被覆する。Subsequently, the entire surface is coated with aluminum, which is the material of the second metal wiring layer 4, by vacuum deposition or the like.
次いで、感光性レジストを用いて、写真製版技術により
、該アルミニウム膜の上に所望のレジストパターンを形
成する。Next, a desired resist pattern is formed on the aluminum film by photolithography using a photosensitive resist.
そして、このレジストパターンをマスクとして、アルミ
ニウムの反応性イオンエツチングを行なう。Then, using this resist pattern as a mask, reactive ion etching of aluminum is performed.
このエツチングの際、真空度、ガス流量比、反応性イオ
ン種等のエツチング条件を時間とともに徐々に変更する
ことにより１等方的なエツチング゛を行なうと、最終的
には第１図に示すように、第２の金属配線層２内にある
金属配線４ａ 、４ｂの断面形、状は、第１の金属配線
層２に向き合う辺がそれに対向する辺よりも短くなった
、台形形状となる。During this etching, if one isotropic etching is performed by gradually changing the etching conditions such as the degree of vacuum, gas flow rate ratio, and reactive ion species over time, the final result will be as shown in Figure 1. In addition, the cross-sectional shape of the metal wirings 4a and 4b in the second metal wiring layer 2 is trapezoidal, with the side facing the first metal wiring layer 2 being shorter than the side facing it.
その後、パッシベーションｌｌｌ５を形成し、表面を保
護する。After that, passivation lll5 is formed to protect the surface.
このようにして得られた第２の金属配線層４にある金属
配線４ａ、４ｂの持つ単億長ざあたりの容ｆｆ１ｃ （
ＮＥＷ）は次式で表わされる。Capacity ff1c (
NEW) is expressed by the following equation.
ε、ｔ’ ・Ｌ＋ ε。ε”ｔｚ
Ｃ（Ｎ Ｅ Ｗ ） ｍ−−−１−、己ゴーここで立−
痣、−Δ痣とすると、
上式は
となる。ε, t' ・L+ ε. ε”tz C(NEW) m---1-, I'm standing here-
Assuming birthmark and -Δ birthmark, the above equation becomes.
従来の半導体装置の金属配線の容量Ｃ（ＣＯＮＶ）と本
発明に係る半導体装置の金属配線の容量Ｃ（ＮＥＷ）
を［２すると、Ｃ（ＣＯＮＶ＞＞Ｃ（Ｎ Ｅ Ｗ ）と
なる。Capacitance C (CONV) of metal wiring of a conventional semiconductor device and capacitance C (NEW) of metal wiring of a semiconductor device according to the present invention
[2, then C(CONV>>C(NEW)).
すなわち、従来の装置に比べて、本発明に係る半導体装
置の金属配線の容量は低減する。That is, the capacitance of the metal wiring of the semiconductor device according to the present invention is reduced compared to the conventional device.
−力木発明によると５ｉ１！１Ｆｊｌの断面積に若干の
減少が見られが、この程度の減少なら半導体装置上の大
きな問題とはならない。すなわち、この程度の断面積の
減少ならば、金属配線の抵抗増大およＶ断線等の問題を
発ｔさぜない。- According to Riki's invention, there is a slight decrease in the cross-sectional area of 5i1!1Fjl, but this level of decrease does not pose a major problem for the semiconductor device. That is, if the cross-sectional area is reduced to this extent, problems such as increased resistance of metal wiring and disconnection of V wires will not occur.
なお上記実施例では第２の金属配線層４内にある金属配
線４ａ 、４ｂの形状が、その下辺が上辺よりも短い、
逆台形形状である場合を示したが、本発明はこれに限ら
れない、、すなわち、第１の金属配線層２内にある金属
配線２ａの形状が、その下辺が上辺よりも畏い、正台形
の形状であっても、実施例と同様の効果が実現する。In the above embodiment, the shape of the metal wirings 4a and 4b in the second metal wiring layer 4 is such that the lower side thereof is shorter than the upper side.
Although the case is shown in which the shape is an inverted trapezoid, the present invention is not limited to this. That is, the shape of the metal wiring 2a in the first metal wiring layer 2 is such that the lower side thereof is larger than the upper side and the shape is correct. Even with a trapezoidal shape, the same effect as in the embodiment is achieved.
また、上記実施例では金属配線層が第１の金属配線層２
と第２の金属配線層４の２層からなる半導体装置を例に
挙げて説明したが、本発明はこれに限られず、ざらに多
くの金属配線層からなる半導体装置に応用しても、実施
例と同様の効果を実現する。Further, in the above embodiment, the metal wiring layer is the first metal wiring layer 2.
Although the present invention has been described using an example of a semiconductor device consisting of two layers, ie, the second metal wiring layer 4, the present invention is not limited to this, and can be applied to a semiconductor device consisting of a large number of metal wiring layers. Achieve the same effect as the example.
さらに、上記実流例では、半導体基板にシリコン基板を
用いた場合を示したが、本発明はこれに限られず池の材
料からなる半導体基板を用いても実施例と同様の効果を
実現し得る。Furthermore, although the above actual flow example shows a case where a silicon substrate is used as the semiconductor substrate, the present invention is not limited to this, and the same effects as in the embodiment can be achieved even when a semiconductor substrate made of a silicon material is used. .
［発明の効果］
以上のようにこの発明に係る多層配線構造を有する半導
体装置によれば、絶縁膜を介して配置された第１の金属
配線層内
の、該第２の金属配線層内にある金属配線の断面形状は
、該第１の金属配線層に向き合う辺がそれに対向する辺
よりも短くなった台形形状となっている。したがって、
半導体装置の高集積度を保ち、金属配線の抵抗増大・断
線等の半導体装置上の問題を発生させずに、金属配線の
容量を減少させることができる。[Effects of the Invention] As described above, according to the semiconductor device having the multilayer wiring structure according to the present invention, in the second metal wiring layer in the first metal wiring layer arranged through the insulating film, The cross-sectional shape of a certain metal wiring is a trapezoid in which the side facing the first metal wiring layer is shorter than the side facing the first metal wiring layer. therefore,
It is possible to maintain a high degree of integration of the semiconductor device and reduce the capacitance of the metal wiring without causing problems with the semiconductor device such as increased resistance or disconnection of the metal wiring.
第１因はこの発明の一実施例の部分断面図、第２図は従
来の多層配線構造を有する半導体装置の部分断面図であ
る。
図において、１は第１の絶縁膜層、２は第１の金属配線
層、２ａ、４ａ、４ｂは金属配線、３は第２の絶縁膜層
、４は第２の金属配Ｉａ層である。
なお、各図中同一符号は同一または相当部分を示す。The first factor is a partial sectional view of an embodiment of the present invention, and FIG. 2 is a partial sectional view of a semiconductor device having a conventional multilayer wiring structure. In the figure, 1 is a first insulating film layer, 2 is a first metal wiring layer, 2a, 4a, 4b are metal wirings, 3 is a second insulating film layer, and 4 is a second metal wiring layer. . Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
積層された多層配線構造を有する半導体装置において、 前記絶縁膜を介して配置された第１の金属配線層と第２
の金属配線層のうちの、該第２の金属配線層内にある金
属配線の断面形状は、該第１の金属配線層に向き合う辺
がそれに対向する辺よりも短くなった台形形状であるこ
とを特徴とする多層配線構造を有する半導体装置。[Scope of Claims] A semiconductor device having a multilayer wiring structure in which a plurality of metal wiring layers are stacked on a semiconductor substrate with an insulating film interposed therebetween, comprising: a first metal wiring layer disposed with the insulating film interposed therebetween; Second
Of the metal wiring layers, the metal wiring in the second metal wiring layer has a trapezoidal cross-sectional shape in which the side facing the first metal wiring layer is shorter than the side facing the first metal wiring layer. A semiconductor device having a multilayer wiring structure characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30982586A JPS63160363A (en) | 1986-12-24 | 1986-12-24 | Semiconductor device with multilayer interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30982586A JPS63160363A (en) | 1986-12-24 | 1986-12-24 | Semiconductor device with multilayer interconnection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63160363A true JPS63160363A (en) | 1988-07-04 |
Family
ID=17997714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30982586A Pending JPS63160363A (en) | 1986-12-24 | 1986-12-24 | Semiconductor device with multilayer interconnection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63160363A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7450397B2 (en) | 2005-03-24 | 2008-11-11 | Sanyo Electric Co., Ltd. | Wiring board and circuit apparatus |
| JP2010221307A (en) * | 2009-03-19 | 2010-10-07 | Toyota Central R&D Labs Inc | Electric device |
-
1986
- 1986-12-24 JP JP30982586A patent/JPS63160363A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7450397B2 (en) | 2005-03-24 | 2008-11-11 | Sanyo Electric Co., Ltd. | Wiring board and circuit apparatus |
| JP2010221307A (en) * | 2009-03-19 | 2010-10-07 | Toyota Central R&D Labs Inc | Electric device |
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