JPS63157525A - Dissipated position polynominal expression generating circuit - Google Patents

Abstract

PURPOSE:To increase a processing capacity by connecting plural arithmetic circuits consisting of a multiplier having an output selected from a multi-input and a multi-output, in its one input, and a register for storing an output added with the result of its multiplication, and the output of a selecting circuit. CONSTITUTION:A processing unit PE is provided with a selector 1 for inputting the polynominal expressions A, B and C by selecting signals S1, S2, and outputting X and Y. The outputs X, Y of the selector 1 are inputted to multipliers 2, 3 formed by a ROM or a gate circuit on a Galois body, and its outputs are added by an adder 4 formed by an EXOR circuit on the Galois body. Registers 5, 7 latch the outputs X, Y selected by a clock CK, and a register 6 latches the result of the adder 4. By connecting plural pieces of such processing units PE in the same form, various arithmetic operations on the Galois body are executed. In such a way, the high reliability, the high speed property, the large integration, and the regularity of an internal structure can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the field of error correction, and also relates to a technique for performing parallel processing in signal processing that is symmetrical about communication channels. ' The present invention relates to a technique for performing erasure error correction in encoding and decoding BCH codes.

[Prior art and its problems]

In recent years, the application of error detection and error correction codes (hereinafter simply referred to as error correction codes) has become widespread as a measure to improve the reliability of various digital systems including memory systems.

There are various types of error correction codes that are used in the target system, but the most typical one is a class of linear codes called cyclic codes.

This includes BCH code suitable for random error correction, fire code suitable for burst error correction, and R e e d which is a type of BCH code and suitable for byte error correction.
-Solomon code (hereinafter referred to as R3 code) and the like are included. Among these, the RS code is a code that is extremely important in practical use because it has the lowest redundancy among linear codes with the same code length and correction ability. It is widely used for discs (hereinafter referred to as CDs).

There are various decoding methods for this RS code.
It is relatively easy to implement a decoder for a small degree of correction capability. However, in order to obtain high confidence, it is necessary to increase the correction ability. In that case, problems arise in that the scale and control of the device becomes extremely complex, and the calculation time required for decoding processing also increases. For this reason, CDs currently use a type of double encoding called CIRC.
This poses a problem in systems that require higher reliability or higher speed. In addition, in order to obtain high reliability, magneto-optical disks etc. use Long Distance C0de (
A multiple error correction code called I, DC) has been proposed, but the problem is how to achieve high speed. Satellite communications require two things: high reliability and high speed, but when considering the development of equipment, it has been extremely difficult to satisfy the above two conditions.

However, with recent advances in semiconductor technology, VLS
I am now able to think about becoming an I. At that time VL
It is important to consider a decoding method that takes advantage of the characteristics of the SI architecture. A feature of the VLSI architecture is that it achieves large scale integration by regularly configuring the internal structure.

Further, the decoding procedure of the R3 code is divided into the following four steps.

Step 1) Syndrome generation step 2) Generation of error position polynomial and error value polynomial Step 3) Generation of error position and error value Step 4) Execution of error correction Step 2 is the most complicated step in decoding the R3 code. Well-known algorithms for this purpose include Peterson's method, Berlecumbe-Matsusay's method, and Euclid's algorithm. The derivation of the error locator polynomial and the error value polynomial based on Euclid's algorithm can be reduced to an extended GCD (greatest common denominator) problem of polynomials. The extended GCD problem of polynomials can be solved by the systolic algorithm. The systolic algorithm is a VLSI-oriented algorithm proposed by K. It is composed of a network of

(Technical) Calculations are performed while data travels through a network of identical processors.

■) A network between processors is constructed by connecting adjacent processors according to certain rules.

(2) There is a small (one unit) time delay in passing data from one node (processor) to another in the network.

This architecture is one of the Vibrine methods,
Perform parallel processing by regularly circulating data. Furthermore, by increasing the number of PHs that operate in parallel, processing capacity can be increased.

[Means and works for solving the problems] In view of the above points, the present invention applies the idea of the systolic algorithm and develops a specific algorithm for actually applying it to an erasure error corrector for I3 CH codes. In particular, the vanishing position polynomial generation circuit is constructed using the same processing element (
The aim is to achieve this through PE (hereinafter referred to as PE).

Further, a configuration is shown in which the configuration of the same PE is changed to realize a trade-off between hardware amount and high speed.

[Example] Before entering into a detailed explanation of the present invention, the principle of error correction will be explained.

1ULiΔPlate First, the principle of the R3 code will be described. The R8 code is a code of great practical importance, having the characteristic of having the lowest redundancy among linear codes having the same code length and correction ability.

The R3 code is a non-dual BCH code (Bose-Chavd
huri-1-1ocquenghen code)
This is a special case of finite field, hereinafter abbreviated as GF. )
It is composed of elements of GF (q). Here, q is GF
It is the original number of (q).

Using this q, various parameters characterizing the RS code are defined as follows.

・Code length: n (-number of symbols in the code) n≦q
-1 (2-1) - Number of information symbols: k (-number of information symbols in code)
・Number of check symbols: n-k (-number of check symbols in the code) n- = dmin-1 (2-2) ・Correction ability: t (-number of symbols that can be corrected in the code)
([X] Gauss symbol 0.The largest integer not exceeding X) Here, dmin is what is called the minimum distance (Hamming distance).

conquest - uization First, polynomial expressions such as code words will be explained here.

For example, if you want to encode as many information symbols as 1"('
an i,, ++, Ik-1)
(210), this is expressed as a polynomial as follows.

1(x)=io+i, x+i, x”+・=+i, −, x
'-'+i,-,x'-' (2-11) Similarly added (n-k) check symbols C= (c.+
C+ +..., Cm-*-+)
(212) is C(x)=Co+C+ x+c=x”+ ++ CM
- to -1"X"-to' (2-13) Furthermore, a code word FF" that summarizes these
(2-14)=c,...self"'Cn-
-1・to・L + 1! +...tm-+)
(215) is F(x) = fo+f, x−H,x”+ −・−
'f,-,x'-'+f,-,x'-' (2-16
) is expressed as a polynomial.

Next, as mentioned at the beginning, the R8 code is a type of cyclic code, and what characterizes the cyclic code is the generator polynomial G (x) used during encoding/decoding. This generating polynomial must have a degree equal to the number of check symbols (n-k) of the code and must be able to divide (x'-'), but in the RS code, the following equation is used.

G(x)=(x-a)(x-a2)-(x-an-'
) (2-17)(G(x)=(x-IXx-a)
-(x-a”-to can be used) (2-18) Here, α
is the primitive light of the finite field CF (q) whose sign is defined.

Using this (n-k) order generator polynomial, (n, k)R
To obtain the S code, follow the steps below.

i) Multiply the information symbol polynomial I (x) (formula (2-11)) by xnl.

1i) Let R(x) be the remainder polynomial obtained by dividing I(x)·Xn-k by the generator polynomial G(x).

1ii) Replace this R(x) with a check symbol polynomial C(x), and add it to I(x)·xn-k to obtain a codeword polynomial F(x).

F(x)=I(x)-xn-'-C(x)=Q(x)・
G(x) (220) As can be seen from equation (2-20), the codeword polynomial F (x) can be divided by the generator polynomial 〇(x) that generated it. However, (2-
The generating polynomial of equation 17) is α, α2. ...Since it has a root α1, when this root is substituted into the code word polynomial F (x), the following equation is established.

F(a')=O(i=1.2..., n-k)
(2-21) Expression (2-21) is expressed as a matrix as follows (FT is the transposed matrix of F).

Here, the matrix H on the left side is called a parity check matrix and has an important meaning in decoding.

De-JL method As already mentioned, since the Its code is a type of BCH code, it can be decoded using the general OrCl-1 code decoding algorithm. However, in that case, the handling of symbols such as addition 9 multiplication in the decoding process will depend on the R
It must be performed on a finite field CF (q) in which three codes are defined.

Considering an R3 code with code length n = 2''-1 defined on GF(2'') (m: positive integer), the symbol is represented by an m-bit binary number, and the operation is GF(2'
''). Also, the generator polynomial is the equation (2-17), and the minimum distance between the codes is dmin=2t+1 for simplicity.
To put it (make it a thing)

g(x)=, (x-a Xx-a...(x-a"-
”> (2-17) However, α is a finite field GF (2″
Now, the decoding procedure for such an RS code is as follows:
As with the general CH code, it is divided into the following four steps.

Step 1) Syndrome calculation.

Step 2) Calculate error locator polynomial and error evaluation polynomial.

Step 3) Estimation of error location and error value.

Step 4) Execute error correction.

Step 1 Syndrome ■U First, the transmitted codeword is F: F=(fo, I+, −-
−fn−+) occurred error as E: E=(co,
el, "'en-1) R the received word: R=
(ro, rl, "rn-1) = F+E = (f+)+eo, f++e+, -= fn-
I+en-1), then the polynomial representation R(x) of the received word
becomes as follows.

R(x) =F(x)+E(x)=(fo+
eo) + (f++e+) x+ =+ (
fn-+ +en-+ ) x″-’ (223
) However, the generator polynomial G (
x) (Equation (2-17)) root a' (i=1....
, n-k), (F(α') = O) holds, so similarly a i (i=
1. ..., n-k), R (α') = F (α') + E (α') = O + E (α')
=E(αI), a value determined only by the error E is found.

This is called a syndrome, and once again S= (so, s+, =, -1 for Sn-)
(2-25) siR(α”')=E(α1F')
(i = 0, 1, -, n-1) (2-2
6). This syndrome contains all the information about the error (location and size of the error).

(Since the syndrome is 0 if there is no error, the presence or absence of an error can be detected.) Syndrome ((2-25).

Expression (2-26) is expressed as a matrix as follows.

5=HR” (R”: R’s permuted matrix), (2-
28) Suits 2 Wrong 1″IYIIf Wang゛ Wrong
, - In Step 2 of Tae, an error locator polynomial and an error evaluation polynomial are calculated using the syndrome of the calculation result of Step 1. First, here the error E=(e, ,
Let the number of non-zero elements of e, . . . en-+), that is, the number of errors, be 1 (1≦t). Also, the position where the error occurs is ju (u=1゜2-1ri (ju=o, 1-n-
1), and the error at position ju is 01. shall be. Furthermore, convert formulas (2-2) and (2-3) to n-=dmin-]=2
t, (2-30) and (.Then,
The syndrome and syndrome polynomial of equation (2-26) are expressed as follows.

The following equation is obtained.

S (x) = [S-(x) mad x”
(2-35) Now, here the error locator polynomial σ
(x) is defined as follows. This polynomial is expressed as the error position ju(u” L2+”””+ ') (J
GF (2
It is a polynomial whose root is "element α month of )".

ty (x) = (1-(Z”X) (1-a”x) ・
(1-a"x) = n (1-(!" Define.

Then, from equations (2-34), (2-35), and (2-37), the following equation holds true.

σ (x) − 8(x) = [ω (x) co mo
dx2I (2-38
) Therefore, using an appropriate polynomial A (x), σ(x),
The relationship between S (x) and ω(x) is expressed as follows.

A (x)-x”+ a (x)・S (x) = (I
J (x) (2-39) By the way, the number of errors l is CI! ≦t), so ω(x) and σ(
x) is deg ω(x) < deg a (x)≦t(2-
40) is satisfied. Furthermore, since ω(x) and σ(x) are relatively prime (the greatest common difference (GCD) polynomial is a constant), (2−
39), ω(x) and σ(x) that satisfy equation (2-40) are uniquely determined except for the difference in constant coefficients. From the above, ω, (
x) and a (x) are the greatest commons of x 21 and S (x) (
GCD) can be obtained through the process of Euclid's algorithm for finding polynomials. Here, a method for calculating the greatest common difference (GCD) polynomial using Euclid's algorithm will be briefly described. First, GC the greatest common polynomial of the two polynomials A and B.
Let it be expressed as D [A, B]. Also, for these A and B, the following polynomial is written: If n 1dcgΔ≧degn, then N=Δ−[A−13′]−
13(2-41)+1=I) (2-
42) If dcg8≧cgl] then λ=A
(2-43) L1=n-[1-A']-A
(2-44) ([x-y-']: quotient of polynomial X divided by polynomial Y) Determine a t, GCD [A, Il
l GcD [A, 11 satisfies the following formula.

GCD [A, B] = GCD [AJ] (2
-45) Therefore, let the above-mentioned λ and n be A and B again, and according to the magnitude relationship of the respective orders degA and degB (2-41).

(2-42) or (2-43), (2-44
), and when either A or B becomes a zero polynomial, the other non-zero polynomial is obtained as the greatest common polynomial of A and B. In addition,
Finding the greatest common polynomial of polynomials A and B is no different from finding polynomials C and D as shown below. Note that deg refers to the order.

GCD [A, 113] = C-A0D-IJ
(2-46) Then, in the process of executing the above repeating steps to obtain the greatest common polynomial of B to a polynomial whose degree is expressed as B to i=deg8≧de, polynomials C, , W can be found.

The problem of finding such a polynomial is called an extended GCD problem.

Therefore, the error locator polynomial σ(x) and the error evaluation polynomial ω(
x) is, in equation (2-47), the polynomial A is
It can be found by solving the extended GCD problem when polynomial 2〇 is set as S (x).

- Algorithm First, as mentioned above, the dedicated algorithm for σ(x) and ω(x) can be reduced to an extended GCD problem. That is, x2
′ as polynomial AO, syndrome polynomial S (x) ((2
-32) equation) as a polynomial Bo (degAo=2
t.

degBo=2t-1), the polynomial that satisfies GCD [Ao, Bo] is calculated as follows: If W is found, then D is the error locator polynomial σ(x), and W is the error evaluation polynomial ω(x). each represents. It is known that such σ(x) and ω(x) are uniquely determined except for the difference in constant coefficients.

Therefore, for Ao and Bo, the following polynomial A,
Define B, U, V, L, M and set their initial values as U=M=l;, L=V=O; (A=Ao, B=B
o), repeat the steps in Figure 15, and when degA (degB) < t, A (B
) is found as ω(x), and L (M) is found as σ(x), respectively.

In addition, in the method shown in Fig. 15, the division on GF in the iterative step is omitted by multiplying A and H by the highest degree coefficient α of polynomial B and the highest degree coefficient β of polynomial A, respectively. . ((2-41).

(See equation (2-43)) Even if we do this, σ(x) and ω
There is no essential problem with the value of (x).

FIG. 15 will be explained. First, in step l, U=M=1. Set initial values by setting L=V=O, A=Ao, l3=I3°. In step 2 dc
It is determined that gA≧degl'l, and in step 3, the highest degree coefficients β and α of the polynomials A and I3 are expressed as A and I, respectively.
3 is multiplied by each other, formula (2-41), (2-
The division on GF in the repetition step of 43) is omitted.

If degA and degB become smaller than the predetermined order in step 4, proceed to steps 5 and 6, and ω(x)
=A, σ(x) =L, ω(x) =B, σ(x) =
Calculate M.

Note that in order to execute the iterative steps shown in FIG. 15, three execution modes are required depending on the orders of A and B, and these will be referred to hereinafter as follows.

i) degA, degB≧t and degA≧de
gB-'reduceA"ii) degA, degB≧
t and degA≧degB−・・“reduceB”1
ii) degA < t or degB < t
-""nop" Step 31r 1♂ SoP's ~ In step 3, the error location and error value are estimated from the error location polynomial σ(x) and error evaluation polynomial ω(x) obtained in step 2. I do. First, the received word R= (r
o, x, ---, rn=') symbol position ff1
t=o.

The element α-1 of GF(2") corresponding to l...n-1 is successively substituted into the error locator polynomial σ(x). At this time, (2-
From formula 36), if σ(a '' ) = O holds true, it can be seen that α-1 = α-1u holds true for i at the error position ju. (j u = 0, 1 -n
-1, u = 1, 2-1, 1≦t) Also, the error evaluation polynomial ω(x) for such α1 = α-)
The value of is as follows.

Furthermore, if σ'(x) is the differential of σ(x), then the following holds true. Therefore, from equations (2-48) and (2-49), the error value C1 at the error position ju can be obtained from the following equation.

As mentioned above, in step 3) of decoding, step 2
CF(2”) whose RS code is defined by three polynomials: the error locator polynomial σ(x) obtained from ), the error evaluation polynomial ω(x), and the differential σ′(x) of σ(x) It is necessary to calculate the value by successively substituting the element α-' (j = n-1, ・2, 1.0). (Here, the received symbol is input from the higher-order term of the received word polynomial.) In other words, assume that rj is input in the order of j=n-1,..., 2, 1.0.Therefore, in the explanation of step 3), a= (j=n-1, . -・, 2, 1.0) must be noted that the order of substitution is reversed.) Here, the concrete calculation required is simply to substitute the variable to the polynomial and find its value. Since there is
The calculation of x) is developed as follows.

f (x) = ftx'+ft-1x'-'
+...10r, x-)-f.
(5-11) = I-...[(ftx+f
t-1) x-Ht-2) x+...+f+l x+
fo (5-12) However, in the syndrome calculation, each cell has X to be substituted in advance, and a coefficient is given to each cell to calculate suit 4 W's! -'- From equation (2-9), the received symbol r at the position ju where the error occurs. is expressed as follows from the symbol f2 of the original code word and the error magnitude e2.

rJu= rlu −el,, (251) Therefore, in step 4, the execution result of step 3 a (α−′) =O
At the position i (i=0.1.-n 1) where is established, subtract the received symbol r1 < (on GF(2")) f, = r+ -
el (2-53) performs error correction at position i.

Next, the configuration and operation of the embodiment of the present invention will be described, taking into consideration the principle of error correction described above.

Here, the processing element (PE) that is the basis of the systolic architecture is defined as shown in FIG.

In Figure 1, l represents the inputs of A, n, and C as Sl,
It is a selector that outputs to X and Y as shown in Table 1 according to the selection signal of S2, and O shown in 2 and 3 are multipliers on a Galois field, which can be realized by a ROM, but can also be realized by a gate circuit. 4 is an adder on a Galois field and can be realized by an EXOR circuit. Registers 5 to 7 are latched by the clock CK.

Selector by gate circuit on GF (2'), multiplier, adder (primitive polynomial p (x) =x'+x'+
x"+x"+x+1), it can be realized as shown in Figures 2, 3, and 4, and the circuit scale and processing speed required for IPH are approximately 800 gates and 1 gate, respectively. 10-20 when delay is 5-10ns
Mhz=80-1610-2O (because processing is performed in units of 1 symbol (8 bits)). (The delay in the l gate is set to TTL level, but since the selector, multiplier, and adder, which are the processing parts in the PH, are consolidated in one place, this part will be optimized and speeded up when converting to vLSI. (By doing so, the processing speed can be further increased.) Furthermore, by expanding the configuration of the IPE as shown in FIG. 5, connections with fewer interface sections can be achieved. In FIG. 5, the selector 1 is a five-man power, four-output selector, and the combination of outputs is the selection signal S1. .

4 as shown in Table 2), the number of registers is increased to five. The circuit scale required for this PE is approximately 100
0 gate, but the processing speed remains the same.

By using this PE, all PEs are operated with the same clock, and the entire system is controlled by each PE's selection signal S1. ．． It is possible to have only 4.

(Syndrome generation unit) In step l, the received sequence R(rn-II rn-2”・
+rl+r□) to the syndrome polynomial % expression % required in step 2. To calculate the specific coefficients of the syndrome polynomial, the received symbols rn-I, rn-2"', rl,
Since ro is sent serially, it is expressed by an iterative algorithm as shown below.

s,,+ =(・((r,,,*α'+rn,z)*α
'+rn, )*α'+・+r, )*α1+r6 Therefore, the above equation can be decomposed as follows.

Z0=O Z+ =21-+ *(2' + rn-+
(!” 1....-, n) Sb, + = Zll The PE shown in Fig. 1 is used as shown in Fig. 6, and the signal is sent as shown in Fig. 8.

Initially (i=1), rn-1 is input to selector B. The Y output of the selector selects the B input and outputs rn-1. At this time, in order to calculate Zl=Zo*α' + r n-1, the X output of the selector selects C so that Zo=O, and outputs O (Sl, 2=1.O).

The X and Y outputs are respectively multiplied by αI and 1, and by adding the outputs together, a Zl''rn-1 output is generated, which is input into the register 6 at the next clock.

Furthermore, the Y output r1-1 is input to the register 7 at the same clock. Next, (i=2...+n), by setting the X output of the selector so that the A input is selected, the previous output Zi-1 is output from X, so (SL, 2=
0゜0), Zi=Zi-1*tl'+rn-i is calculated, and when i=n, one coefficient 5 of the syndrome polynomial
i-1 is generated. During this time, rl is sequentially output from the register 7.

By connecting these PEs as shown in FIG. 7 and assigning the value of α1, each coefficient of the syndrome polynomial is sequentially generated (the timing is shown in FIG. 8).

Furthermore, in order to simultaneously generate each coefficient of the syndrome polynomial, PEs are connected to each other as shown in FIG. In this case, it must be noted that the communication distance of the received symbol r1 differs depending on each PE (timing is shown in FIG. 11).

Furthermore, by using the PEs shown in FIG. 5 as shown in FIG. 12 and connecting them as shown in FIG. 13, each coefficient of the syndrome polynomial can be output continuously from the last PE. A signal is input to the circuit shown in FIG. 13 as shown in FIG. 14.

In the first I'E, the selector output W normally selects the D input, but when the syndrome 521-1 is generated, the selection signals S1, . 4 = 1010, W 1. : Output the A input, input syndrome 521-1 to register 8, and output from 5(x). When syndrome S 21-2 is generated in the next PE
Since the output 52L-1 of the previous PE is input from the input, the input is output to Z to shift S2L-2 by one clock (Sl,,4=1110), and the syndrome S21-2 is input to register 9. Incorporate. By outputting that output to W at the next clock (Sl,,4=OOIO
) S2 and 2 are input to register 8, and S (x) to 5
S21-2 can be output next to 2L-1.

For subsequent PEs, the timing for outputting to S (x) after the syndrome S i-+ is generated is further shifted by one clock (therefore, the timing for setting Sl,,4=OO10 is shifted by one clock). As a result, the coefficients 521-1, . . . , So of the syndrome polynomial can be continuously output from S(x) of the last PE.

In Figures 7, 10, and 13, the number of PEs required is 2.
, and the processing speed is 10-210-2O (word
/sec).

(GCD generation unit (error locator polynomial and error numeric polynomial generation)) The algorithm for deriving the error locator polynomial σ(x) and the error numeric polynomial ω(x) in step 2 can be reduced to an extended GCD problem. That is, when x 2 + is set as polynomial A0 and syndrome polynomial S (x) is set as polynomial B0 (
d e g A .

=2t, degBo=2t-1), GCD [A,
. (x)). It is known that such σ(x) and ω(x) are uniquely determined except for the difference in constant coefficients. Therefore, Δ. and Bo
For the following polynomials A, n, U, V
, L, and M, and Δ=U*Ao×L*I3゜=V*A0+M*[lI+its initial value as U=M=1. I,=V=O,(A=A,, l3
= B, ), and execute the repeated steps in Fig. 15, and when dcgA (degI3) < t, A
(n) is found as ω(x), and L (M) is found as σ(x).

In the method shown in FIG. 15, the division on GF in the repetition step is omitted by multiplying A and B alternately by the highest degree coefficient α of polynomial B and the highest degree coefficient β to the polynomial. Even if we do this, σ(x) and ω(
There is no essential problem with the value of x).

However, the problem here is that the length of the polynomial changes during the process. For example, when focusing on one process, the degree of the generated polynomial of A or B, that is, the length of the polynomial, changes depending on the magnitude of the difference between degA and degB. In order to make the functions of the PEs correspond to such changes in the length of the input polynomial, each PE is required to have very complex functions. Moreover, in that case, the amount of calculation for each PE becomes uneven, resulting in poor efficiency. to solve this problem,
In the systolic algorithm for solving the extended G CD IL'l i of K. Only the coefficient data of the polynomial is input to the controller, and the order difference is generated in the following three modes by a separate circuit and used as a PE selector selection signal.

1) reduceA; = degA, deg
B≧t or degA≧degB2) reduceB
; = degA, degB≧t and degA≧de
gB3) nop; = degA<t or degB<t Furthermore, in order to equalize the amount of calculation for each PH, the change in the order of A or B in one process is limited to at most the first order. In this way, d of A and B
egA.

degB The next term is not necessarily non-zero, but A (B)
degA (degB) If the next term is zero, then A (
There is no problem if you simply shift B) to a higher position.

Therefore, the algorithm shown in FIG. 15 can be changed to the one shown in FIG. In Figure 15, A (B) or L
The algorithm for calculating (M) is the same except for the order processing, so in Fig. 16, P r o c e s s
The parts are shown using common expressions. In the actual circuit, A (B
) and when calculating L (M).
It is necessary to have two independent ss sections or use one section twice. Below, we will evaluate one Process process, but if one Process part is used twice, the processing speed should be halved, and if two Process parts are used independently, the number of required PHs should be doubled. good.

The main specific calculation for GCD generation is Pr in Figure 16.
Since this is the part expressed as ocess, consider implementing this with PE. However, since the order processing represented by Set and the part for setting 5tate are irregular processing, they are realized by an external circuit. As shown in FIG. 31, this circuit is a circuit 6 (ROM etc.) and order subtractors 7, 8 (configured by adders)
It can be realized with a very small circuit scale.

Process processing is input→selection→product-sum processing, so it corresponds to the operation of IPE. The state of 5tate corresponds to the selection signals St and S2 of the selector as shown in Table 3. When one process is assigned to IPH, the connection is as shown in FIG. 18. 18th
The top row in the figure is a row for setting α and β, and α determined by each PE.

β (output from G, H) is common to all columns below it. Furthermore, the state of 5tate is also common to each column.

In this case, the number of required PHs is 2t* (2t+2), and the processing speed is 10-1 because it is processed in units of one code word.
210-2O(length/5ec) =n* (1
0-20) Mwps (word/5ec) =n*
(80-160) Mbps (bit/se
c) (n is the code length).

Further, when Process processing 2 is performed twice, that is, processing for each l polynomial is assigned to lPE, the connections are made as shown in FIG. 22. In FIG. 22, a register is inserted after register 5.7 to realize bIl. This allows coefficient data input to the next PE to A, I3.
Regarding the polynomial of C, terms corresponding to the degree of each polynomial are aligned with each other and inputted sequentially from the higher degree. Further, in order to set α and β, it is necessary to externally add registers controlled by CK2 and CL. Input polynomial A, I3. x, y output with C selected by 5tate.

The coefficients of the highest degree of the power polynomial are each alternately β.

α is output from H and G, latched by CK 2, and the value is stored in a register for each PE. However, A,
α during the highest degree input of polynomials in B and C.

Since β is not determined, CL outputs 0 (because it is determined that the processing result of the highest order is 0).

In this case, the number of required PHs is 2t*2, and the processing speed is (10-20)/2tM1 ps because Process 2 is allocated to IPR.

Here, for the example shown in FIG. 25, the signal flows when finding A (B) using the connections shown in FIGS. 18 and 22 are shown in FIGS. 19 and 23, respectively, and when finding L (M), The signal flows are shown in FIGS. 20 and 24. (α.

It is assumed that the value of β is determined during the processing of A (B) and is saved until the processing of L (M)).Also, using the PE shown in FIG. By connecting as shown in the figure, the connection in Figure 22 can be made between neighbors or itself, which is the condition of the communication path originally determined, and the error locator polynomial can be directly received from the syndrome output S (x) in Figure 13. , and the error numerical polynomial can be output. (The timing is the same as in Figures 23 and 24. However, #0 PE is S only at the beginning of A (B) processing.
l,, 4=OOOO1 onwards S1. .

4=0100, and only the beginning of the processing of L (M) is Sl,
, 4=1100, hereafter S1. ．． By setting 4=0100, the inputs shown in FIGS. 23 and 24 are realized. ) Also, if the processing for each # of Process processing is assigned to IPH, the PE in Fig. 5 is used as shown in Fig. 28, and the second
9. Connect as shown in Figure 9. In this case, the number of PEs required is 2, and the processing speed is (10-20)/(2t+
2) Mlps (timing is shown in Figures 19 and 20)
(same as figure).

(Error position and error value generation unit) In step 3, the error position polynomial σ(x), error value polynomial ω(x), and σ(x) obtained in step 2 are
Element α-' (i=n-1
, . . . , 1.0) must be sequentially substituted to find the value. The specific calculation required here is simply substituting a variable into a polynomial and finding its value, so an iterative algorithm similar to the syndrome calculation can be used. For example, the calculation of the t-1 flame term "(x) is expanded as follows.

f(x) = f, -, * 'x'-' + f, -, * x
'-''...+f, *x+f.

”(((L-+ *x+f, ω*+f, -3)*X+・
...10fυ*x1fo) Therefore, it is decomposed as the following equation, which is similar to the syndrome calculation.

Z0=O Z(= Zl-+ * X + L-+ (
j = 1 +..., 1) f(x) = Z.

However, in the syndrome calculation, each I'E has X to be substituted in advance, and a coefficient is substituted for each r'E.
Here, the coefficient f, -+ 0 = 1, . . . , 1) is known in advance, and X is substituted into each PE.

Therefore, using the PE in FIG. 1 as shown in FIG. 32,
Connect as shown in the figure and send signals as shown in Figure 34. FIG. 33 shows that f(α -1) are output sequentially. One I'E
Z+-1 (previous PE's e output) and α-1 (previous PE's α-
” output) are input at the same time, and from that I'E Z+ =
The configuration is such that Zl-+ *α-' + f, -, and α-1 are output.

f (x) is calculated by assigning this process to each PE from i=1 to t.

Further, the PE having the configuration shown in FIG. 5 is used as shown in FIG. 35, connected as shown in FIG. 36, and signals are sent as shown in FIG. 37. First, the coefficient f is set by applying fl-+(j=1.・
. . , 1) are input sequentially, and each PE is set to Ll.
When the value of S1. is input, the selection signal S1. ．． 4=OOIO
shall be. As a result, fl-1 is output from the W and Z outputs, and "1." is input to register 8. After that, Sl
,.

By setting 4=0000, fl-1 is stored in register 8.
is stored. Then, when processing the next received series, if Sl, , 4=0110, Ll stored in register 8 is output from the Y output and input to register 7. Hereinafter, if the selection signal St, , 4=OOOO, then Y
The output always outputs "11", and each PE receives f +-1
is now set. Meanwhile, the X output selects the input to, and α-' (i=n-1,..., 0) continues to be output, and the α-1 output is sent to the next PE from register 5 with a one-clock delay. Sent sequentially. By performing this for each received sequence, f(α-1) in FIG. 34 is calculated. By connecting this to the circuits shown in FIGS. 13 and 27, steps 1-3 can be realized without an interface circuit.

The circuits in FIGS. 34 and 36 have ω(x) and σ(x).

Three sets are required for the calculation of σ'(x). Since 1 set requires t PEs, the number of PEs required is 3t, and the processing speed is 1
Since each word is processed sequentially, 10-210-
It is 2O.

Here, consider the coefficients of the differential equation σ'(x) of σ(x).

f(x)=f,,*x"+f+-2*xl-"+-+f
, *x+f.

Then, the differential expression f'(x) of f('x) is f' (
x)=(t1)*L-1*x'-"+(t2)
*fl:4*X'-"+-+fl.When the value of (t-i) is an even number, (t-i)=O due to the properties of the Galois field, so the coefficient of f'(x) has a value of 0 intermittently.When the coefficient of 1.1σ'(x) is set as an O coefficient, the selection signal S1.

If 4=OO01 is set instead of 4=0010, O of the C input is output from the W output and set in the register 8.

(Erasure position polynomial generation unit) S erasure errors are at positions jl, j2 . ...+JS, and errors other than one erasure occur at positions kl, k2 .・・・
・, consider the case where this occurs in kr. However, it is assumed that 2r+s+1≦d (d: minimum distance) holds true. Here, Yi=a1' (i==t, 2.-, s), and the vanishing position polynomial λ(x) is λ(x)=(1-Y+*x)*(I Y=*x)-・
・(l Yi*x) and (5(x)*λ(x) (7(x) = ω(x) mod
It can be derived that ``x'' holds. However, σ(x) is an error locator polynomial, and ω(x) is a polynomial of degree r+s-1 or less. However, E.

is the error value of position ji, and Lk is αk l (i
=1. ....

r), and el is the error value of position ki.

At this time, in order to find σ(x) and ω(x) using Euclid's mutual division method, the syndrome polynomial S (x) must be changed to 5(x
)*λ(x), degA<t (degB<
In 1), degA< should be replaced with 10s (degB<t+s).

Therefore, to perform erasure error correction, S (x) *λ(x
) can be generated using PE (degA (B)<
(Replacement with t+S is done in the control section).

To calculate λ(x), the equation for λ(x) is decomposed as shown below.

Z0=1 ZH=(I Y+ * x ) * Zl−+”
Yl * Zll * X + Zl-+ (j= 1
+...,s)λ(x) = Z.

Therefore, the specific calculation of λ(x) is Zl =: Yl *
All you have to do is Zl-+ *X12+-+. Since the order only indicates the order of the signals, it is sufficient to first multiply the input of Zl-1 by Yl and add it to Zl-1 delayed by l clock. Therefore, to generate λ(x), the 42nd
It is sufficient to use the PE as shown in the figure and connect as shown in FIG. 43 (the timing is shown in FIG. 44).

First, regarding the PH of Sl (i=1), the selection signal of the selector is set to Sl,2=01, and the six inputs Z,=1 are set to XL.

Output C input 0 to Y. YI which is the calculation result
*Z6=Yl is input to register 6, and X output z0 is delayed by one clock by register 5 and input to B.

After that, by setting Sl,2=lO, C input O is applied to X, and Z is delayed by one clock to Y.

is output, and the calculation result Z is output at the next clock. =1 is input to the register 6, and 21=(Y1*X+1) are sequentially output from Q. Next, regarding PEs after #2 (i
=2. ..., s), first select the selection signal Sl,
2=01, the highest order coefficient of the Z l-1 output from Q is outputted to X as six inputs, and the C input O is outputted to Y.

Thereby, the highest order term of Y+*Z+-+ is calculated and input into the register 6. l from register 5
The clock delayed Zl-1 is output and fed back to the B input. When Z,-1 is fed back to the B input, by setting Sl,2=OO, Yl
The operation results of *z, -, *X+Zl-1 are sequentially output from the register 6 and input to the next PH. Therefore, the result of λ(x) is output from the PE of #S as a higher-order term.

Since S≦2t, the number of PHs required here is 2t, and if you assign ○ to Y of PEs of S or more, the result of λ(x) from PE of #2t will be output from the higher-order term. .

Further, to generate λ(x) *S (x), PE is used as shown in FIG. 45 and connected as shown in FIG. 46 (timing is shown in FIG. 47). The configuration of FIG. 46 is exactly the same as the polynomial multiplication circuit shown in FIG. 48. The selector selection signal may be fixed to Sl,2=OO. The operation of the multiplier circuit is well known and will therefore be omitted here.

However, in the multiplication circuit shown in Fig. 46, the input of λ(x) is input to all PEs, and the communication distance is different, so the PE shown in Fig. 5 is used as shown in Fig. 52, and the connection is made as shown in Fig. 53. By doing so, the communication distance can be made the same (the timing is shown in FIG. 54). Here the multiplication C(x) = A(x)
* The calculation of B(x) is decomposed as follows.

A (x) = a,, -+*x"-'+ all, *
x″−”+・+ a, *X+a.

Then C(x) = affi-, *B(x)*x"-' +a
, -z*B(x)*x-"10-・--+ a +*B(
x) *x + a0*B(x), so 2, =0 Z (=Z +-+ * x + B (x) *
a +w-1(1=1+...+rl'l)C
(x)=Z,.

Therefore, here, the allocation of Sl to each PE is reversed, and #1
Assign S to -1 to I'E (the assignment power of S, , -1 will be described later). First, in r'E of #l, let i o ” O, and 2. = 2゜ + n(x) * a, , , 1 (
a,, + = 821 +, r3(x) = λ(x
)), and the next I'E is 13 (x), which is delayed by one clock with respect to the output, as r3 (x ) * a
By adding as m −i , 21=Z+−
The calculation 1*X+B (x) *am1 is performed. C(x) is calculated by doing this m=2 times, that is, by allocating 2 to E'E.

In addition, the connection in FIG. 53 directly receives the output S (x) from the syndrome generator in FIG. 13 and generates S (x) *λ(
x). In the circuit of FIG. 53, 3. should be set for each PE. (j=2t i.

..., 0) is sent S 1, . 4 = 0
101, 81 is input to register 9, and thereafter S 1, . By setting 4=0100, the output of register 9 is fed back to the C input, so 81 is stored in register 9, and SI is selected for that PE. The above-mentioned multiplication is performed by setting the selector selection signal of each PE to S1, 4="0100, inputting 2+-+ to the 6 inputs and inputting λ(x) to the C input.

However, in order to input λ(x) with a delay of one clock from the input of Z, λ(x) from register 7 is input in the previous PE.
) The output is fed back to the D input and output from the register 8 through the W output.

Moreover, the circuit of FIG. 50 has Y+ (i = 1, . . .
s) is continuously input.

In this case, too, the input of Y(x) is set to each PE by using I'E in FIG. 5 as shown in FIG. 49 and sending a signal as shown in FIG. 51. Usually, the selector selection signal is Sl.

. 4=0000 (#1 PE only Sl, 4=lO00
), and when Yl to be set is input from the D input, S
l,,4=OO01(PE(7) of #1 1..4=1
101), the D input is selected as the Z output and Yi is input to the register 9. Thereafter, by returning the selector selection signal setting, the output of the register 9 is fed back to the register 9 through the C input and the Z output. The value of Yi is stored in register 9, and Y is input as input to multiplier 2.
This means that the value of i has been set. (2) The operation of generating λ(x) after setting is the same as that shown in FIG.

(Encoder) The encoder is usually constructed from a polynomial division circuit. The division circuit has the configuration shown in FIG.

By using PEs as shown in FIG. 56 and connecting them as shown in FIG. 57, it is possible to obtain exactly the same configuration as shown in FIG. 55. #2t+1 I'E connection! ffa is irregular because information + (x) = (Ll, To-2
,...

■. ) and parity P (x) ” (P2+, P2
1-+, . . . , Pl) to be used as a code word. Therefore, initially #l
The selection signal of r'E from #2t to St, 2=10.
Let the selection signal of I'E of #2t+1 be st, 2=01, and the first word I k-1 of information 1 (x) is #2t+1.
When input from the C input of PE, the selection signal of I'E from #l to #2t is input to Sl.

2=00. During that time, information I (x) is output from the G of the #2t+1 PE through the C input from the Y output.

The final word of information r (x) is input to C. When the input is completed, select signals of PEs from #l to #2t are set to SL.

2=O1, and the I'E selection signal of #2t is Sl, 2
=OO. As a result, parity is output from PE G of 12t+1 following information 1 (x) (timing is shown in FIG. 58). In the circuit shown in FIG. 57, the communication path differs depending on each PE.

(Error Correction Execution Unit and System) The error correction execution unit in step 4 is also configured by the PH shown in FIG. 1, as shown in FIG. However, the 0 detection circuit (O
R) and a reciprocal generator circuit on a Galois field (
ROM, etc.) must be added externally. In the GCD generation section, the processing of A (13) and L (M) is combined into one P
When the rocess section is used twice, the coefficient of ω(x) is sent first, so the value of ω(α″) is also calculated first and sent to this circuit. −1), σ
It is necessary to insert a buffer to match the output timing of ω(α-1) and delay the output of ω(α-1). There is no need to insert a buffer when processing L (M)).

When ω(α and σ′(α−1) are input at the same time, ω(α−′) is input to B, and σ′(α−′
) is converted into a reciprocal and input to the multiplier 3.・σ(α−′) is input to the 0 detection circuit, and when σ(α1)−〇, σ(α−′) is 0, σ(α
1) When ≠0, it is input as l to the selector selection signal S2. When the error position is σ(α″′)20, Sl, 2=00
Therefore, T output is ω(α″) and σ′-1(α
The error value ω(α゛/σ′
(α-1) is output from the multiplier 3. When it is not an error position, σ(σ')≠0, so Sl,2=01 and the Y output outputs O of the C input, so the output of the multiplier 3 becomes 0. The X output always outputs the received word sequence r,' (i=n-1, . . . , O) delayed by the buffer, and the multiplier 2 outputs each received word sequence r.

Therefore, error correction is performed by EXORing the outputs from the multipliers.

In addition, in the previous three sections, in order to find the value of [(α−′), α
-' (i=n-1, ..., 0) is required to be input, but as a generator (i=n-1, -, O), see Figure 1.
PE can be used as shown in FIG. 39th
In the figure, α′=α−0, α8=α, αn−
It is sufficient to set the selector selection signal Sl,2=10 at the clock immediately before generating 1, and thereafter set the selector selection signal Sl,2=OO. The situation is shown in FIG.

As mentioned above, based on Euclid's mutual division method (
Each step of the RS code decoder was configured with the same PH. As an example, by combining each step as follows, the selection signal S1 . .

The entire system can be operated with only 4 controls.

The entire system is shown in FIG.

Step 1) SYNDROME: Fig. 13 Step 2) GCD: Fig. 27 Step 3
) EVALUATE: Figure 36 Step 4) COR
RECT: Figure 38 This allows the entire system to be
The number of PEs required for TeR is as follows.

S G EC [(2t) + (2t+2) + (3t) +11
-” (7t+3) * 1000100O and each P
E selection signal S1. ．． 4 in Figure 14, Figure 23, Figure 24
The entire system is constructed by adding a control circuit as shown in Fig. 37 (the control circuit is realized on a very small circuit scale using ROM, etc.).Also, α-1 is shown in Fig. 39. In this case, the number of ICEs required is 7t+5).

The processing speed of this system is 1 Pr in the GCD generator.
If the ocess section is used twice, it will take more than 4t clocks, so if the code length n is > 4t, it will take 10-20 M
This can be realized with w p s (the processing time when using two Process units is 2t, so there is no problem).

When considering the encoding/decoder as a system, the decoder for erasure error correction can also be used as an encoder, so the decoder for erasure error correction in Fig. 59 is an example of the following combination. It can be realized as an encoder/decoder by

1) SYNDROME: Fig. 13 2) GCD: Fig. 27 3) E
VALUE: Figure 36 4) COR
RECT: Fig. 38 5) ERASURE I: Fig. 50 6) ERASU
REII: Fig. 53 This is the decoder of Fig. 41 plus ERASURE I and ERASURE Tl -, but the processing speed remains the same, and the number of PHs required for the entire system is as follows.

+(2t) + (2t+1) + (4t) + 1
+ (2t) + (2t)1= (12t+3)*
1000 gates If erasure correction is not performed, it is necessary to add the encoder shown in FIG. 57 to the decoder shown in FIG. 41. At this time, the number of PEs required for the entire system is the number of PEs required for the decoder in Fig. 41 (7t + 3) plus (2t +
1) plus (9t+4) (If encoding and decoding are not performed at the same time, the circuit scale in Figure 41 can be reduced by making PE connection and PE control variable between encoding and decoding. without changing (code/decoder can be realized)
.

As described above, by using the PE shown in FIG. 1 or 5, an R3 encoding decoder having a processing speed of 10-20 M w ps can be realized with the following circuit scale.

R8 encoding decoder: 7t-t-3 (9t+, 4) Erasure error correction encoding decoder: 12t+3 For example, t=2
If we consider an R3 encoding decoder with t=8, then 1 at t=2
7,000 gates, and 59,000 gates at t=8, which is within the range that is fully achievable in VLSI even if a control circuit is included. In addition, by optimizing the regularity of the internal structure and communication distance, it is easy to convert to VLSI (by increasing the number of PEs, the processing capacity can be increased linearly. In this case, since the calculation unit consisting of the selector, multiplier, and adder is consolidated in one place, the configuration is such that a processing speed of 10-210-2O or more can be obtained by optimization.

In addition, this PE is used to generate the error locator polynomial and error value polynomial in step 2, which is the center of the decoding process.
By connecting as shown in the figure, high-speed processing of 10-210-2O can be realized. The processing in step 1.3 can also be sped up by special processing (parallelization for each code word, etc.), or by connecting these PEs as shown in Fig. 60, high-speed processing of 10-20 M l ps can be achieved. can be realized.

However, the circuit scale becomes very large.

Further, using this PE, the X1 generation circuit and the divider can be constructed as shown in FIGS. 61 and 62 (timings are shown in FIGS. 61 and 62).

As described above, various operations on the Galois field are possible using this PE, and an R8 code encoding/decoding device can be efficiently configured.

〔Effect of the invention〕

The present invention utilizes the features of the VLSI architecture to achieve the following.

■) High reliability (large capacity) 2) High speed 3) Regularity of internal structure 4) Large integration
We have shown that it is possible to realize an erasure error corrector with a processing speed higher than ). Furthermore, by increasing the number of PEs with the same configuration linearly with respect to the correction capability, the configuration is such that arbitrary high reliability can be obtained. Further, by controlling each PE only by controlling the selector selection signal, all PEs can be operated with the same clock. This is a very effective method for systems that require high speed and high reliability.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of a processing element (PE) according to an embodiment of the present invention. Figure 2 is a diagram showing the configuration of a selector in 1) 1.
) Figure 4 shows the specific configuration of the multiplier on the Galois field of E. Figure 4 shows the specific configuration of the adder on the Galois field of PE. Figure 5 shows the expanded configuration of I'E according to the present invention. Figure 6 shows a PE for syndrome generation using Figure 1 according to the present invention.
FIG. 7 is a connection diagram of PE for syndrome generation using FIG. 1 according to the present invention. FIG. 8 is a timing diagram of 1'E for syndrome generation using FIG. 1 according to the present invention. FIG. 10 is a connection diagram showing another configuration of the syndrome generation PE using FIG. 1 according to the present invention. FIG. 11 is a connection diagram showing another configuration of the syndrome generation PE using FIG. 1 according to the present invention. FIG. 12 is a timing diagram showing another configuration of the I'E for syndrome generation using FIG. 1 according to the present invention. FIG. A connection diagram of a PH for syndrome generation using a diagram. FIG. 14 is a timing diagram of a PE for syndrome generation using the present invention. FIG. 15 is a diagram showing an algorithm for determining GCD. FIG. 17 is a diagram showing an algorithm for GCD generation using PE according to the present invention.
FIG. 18 is a block diagram of H for generating GCD using FIG. 1 according to the present invention.
The connection diagram of E in FIG. 19 is the connection diagram of P for GCD generation using FIG. 1 according to the present invention.
FIG. 20 is a timing diagram of E for generating a GCD using FIG. 1 according to the present invention.
FIG. 21 is a timing diagram of E for generating a GCD using FIG. 1 according to the present invention.
FIG. 22 is a diagram showing another configuration of P for generating GCD using FIG. 1 according to the present invention.
FIG. 23 shows another configuration of P for GCD generation using FIG. 1 according to the present invention.
FIG. 24 is a timing diagram showing another configuration of PE for GCD generation using FIG. 1 according to the present invention. FIG. 25 is a timing diagram showing an example of GCD generation. For GCD generation using FIG. 5 according to the invention [
The configuration diagram of 'E in Figure 27 is for GCD generation using Figure 5 according to the present invention!
'E connection diagram Figure 28 is a P for GCD generation using Figure 5 according to the present invention.
Figures 29 and 30 showing other configurations of H are GCs using the configuration shown in Figure 5 according to the present invention.
Connection diagram 31 showing another configuration of D generation PH is 5ta
FIG. 32 is a block diagram of a te generation circuit. FIG. 32 is a block diagram of an error evaluation PH using FIG. 1 according to the present invention. FIG. 33 is a block diagram of an error evaluation PE using FIG. 1 according to the present invention.
The connection diagram in Fig. 34 is a PH for error evaluation using Fig. 1 according to the present invention.
The timing diagram of Fig. 35 is for error evaluation using Fig. 5 according to the present invention 1)
The configuration diagram of E, Fig. 36 is for error evaluation using Fig. 5 according to the present invention 1)
The connection diagram of E in Fig. 37 is a PE for error evaluation using Fig. 5 according to the present invention.
FIG. 38 is a diagram showing the configuration of r'E for error correction using the method shown in FIG. 1 according to the present invention. FIG.
Fig. 40 is a block diagram of PE for generating 1. α'-(α') using Fig. 1 according to the present invention.
FIG. 41 is a system configuration diagram of an error correction decoder according to the present invention. FIG. 42 is a configuration diagram of an erasure position polynomial generation PE using FIG. 1 according to the present invention. FIG. FIG. 44 is a connection diagram of the PH for generating an vanishing position polynomial using FIG. 1 according to the present invention. FIG. 44 is a timing diagram of the PH for generating an vanishing position polynomial using FIG. FIG. 46 is a connection diagram of a multiplication PE according to the present invention. FIG. 47 is a timing diagram of a multiplication PE using FIG. 1 according to the present invention. FIG. 48 is a diagram showing the configuration of a conventional multiplication circuit. 50 is a configuration diagram of a PE for generating an vanishing position polynomial using FIG. 5 according to the present invention. FIG. 51 is a connection diagram of a PH for generating an vanishing position polynomial using FIG. 5 according to the present invention. Fig. 52 is a diagram of the timing diagram of the PE for generating an vanishing position polynomial using the diagram. Fig. 52 is a configuration diagram of the multiplication PE using Fig. 5 according to the present invention. Fig. 53 is the connection of the multiplication PE using Fig. 5 according to the present invention. FIG. 54 is a timing diagram of a multiplication PE using FIG. 5 according to the present invention. FIG. 55 is a conventional encoding circuit. FIG. 56 is a configuration diagram of an encoding PE using FIG. 1 according to the present invention. FIG. 57 is a connection diagram of a PE for processing using the method shown in FIG. 1 according to the present invention. FIG. 58 is a timing diagram of a PE for encoding using the method shown in FIG. 1 according to the present invention. FIG. 59 is an erasure error correction code according to the present invention. Fig. 60 is a diagram showing a high-speed multiply-accumulator using the system shown in Fig. 1 according to the present invention. Fig. 61 is a diagram showing an X2'' generator using Fig. 1 according to the present invention. Fig. 62 is a diagram showing a divider using Fig. 1 according to the present invention.
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・Multiplier, ■ ・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
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Minoru 27th prisoner cKt in Figure 40 Figure 41 C ↑ ↑ Q Yaezo T = mouth = = = = Bez (χ・z−
1o) 51.2 2 0
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x? ２逼χY＋”Y−1′＝＝＝＝２
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Claims (1)

[Claims] (1) A multi-input multi-output or multi-input-output selector circuit, a multiplier on a Galois field that has the output of the selector circuit as at least one input, and an addition on a Galois field that adds the outputs of the multiplier. The processing capacity is increased by connecting multiple arithmetic circuits consisting of a register and a register that stores the output of the adder and the output of the selector circuit in the same manner, and the value of Y_i (i = 1, ..., s) can be increased. Enter the polynomial λ(x)λ(x)=(1-Y_1・x)・(1-Y_
2.x)...(1-Y_s.x).