JPS6315618B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a data processing device equipped with an audio output function for generating audio in an electronic device equipped with at least a display section or a printing section.

[Prior Art] Conventionally, as shown in Japanese Unexamined Patent Publication No. 53-73051, when a key operation is performed in a small data processing device such as an ECR (electronic cash register), the content of this operation is displayed or printed. At the same time, a recording mechanism is operated by the audio output data corresponding to the key operation, and a sound generating device is connected to announce the registered contents corresponding to the key operation contents from a speaker, and the registered processing contents are outputted by voice. be.

[Problems to be Solved by the Invention] In this type of ECR, it is necessary to incorporate in advance into the program what kind of data is to be output in what processing process. In addition, display data, print data, and audio output data must be created by a data processing device in response to key operations, which makes the program complicated and time-consuming, and also increases ECR processing time. It has the disadvantage that it takes a long time. Furthermore, there is no built-in program for the audio output.
It was impossible to add audio functionality to ECR.

An object of this invention is to connect the same data to a transfer means and a display section or a printing section when a series of data consisting of numerical data and guidance data indicating the type of this numerical data is displayed or printed out. The data is written in a voice generating means detachably connected to a connection line, and the voice generating means converts the written data into voice according to the guidance data and outputs the voice.

[Means for solving problems] The means of this invention are as follows.

A storage means for storing a series of data consisting of numerical data such as monetary data and guidance data indicating the type of this numerical data (subtotal, total, change, etc.), and a storage means for storing the data stored in this storage means.
A transfer means that transfers data to a display section using an LCD, LED, etc. or a printing section of a printer device, etc., and a connection line that connects this transfer means and the display section or printing section. an audio data storage means in which the same data as the data is written as audio output data when the data is transferred; The apparatus is equipped with a sound generating means including a speaker, etc., which converts the sound into a sound and outputs the sound.

[Effect] The operation of the means of this invention is as follows.

When a series of data consisting of numerical data such as monetary data stored in the storage means and guidance data indicating the type of this numerical data is transferred to the display section or the printing section by the transfer means, the transfer means and the display The same data as the above-mentioned data is written as audio output data in an audio data storage means detachably connected to the connection line connecting the section or the printing section, and the guidance data of the written audio output data is followed. Then, the numerical data is converted into sound by the sound generation means and output. Therefore, since the display data or print data is directly used for voice generation, even a data processing device such as an ECR that does not have a voice output function can be easily provided with a voice generation function.

[Example] (1) Configuration An example will be described below with reference to FIGS. 1 to 8. FIG. 1 shows a schematic system configuration diagram of an electronic register, in which 1 is an input section;
This input section 1 is equipped with an amount key, departmental key, subtotal key, etc., as well as "registration (REG)",
"Return (REF)", "Setting (SET)", "Inspection (X)",
A mode switch is provided to set each mode of "Payment (Z)". This input section 1 is given a sampling timing signal KP from an input control section 2, and when a key operation is performed on the input section 1, the timing signal KP is selected according to the operation key, and the key input signal is The signal is input as KI to the input buffer IB provided in the input control section 2.

Further, the printing section 3 sends a printing position signal TP of a printing drum (not shown) provided therein to the printing control section 4, and the printing control section 4 internally sends the data in the printing buffer PB. A print drive signal MD generated by the coincidence is sent to the printing unit 3, and amount data and the like are printed on journal paper and receipt paper. Further, the print control section 4 outputs a printing in progress signal from the time the print data is given to the print buffer PB until the printing of this print data is completed. Further, the display section 5 is given the digit signal DG from the display control section 6, and is also given a segment signal SG obtained by decoding the data in the display buffer HB provided therein, and displays amount data, etc. in accordance with both signals. .

Each of the control units 2, 4, and 6 is connected to the CPU via an address bus line AB and a data bus line DB.
7 and RAM (random access memory) 8 are connected. The RAM 8 stores input sales data classified by department, transaction, etc. In addition, the CPU 7 outputs chip designation signals CS ₁ , CS ₂ , CS ₃ and CS ₄ to each of the control units 2, 4, 6 and RAM 8, respectively, and also outputs an R/W signal in common. is,
Data is exchanged between the CPU 7 and each control section 2, 4, 6 and RAM 8.

A sound generation circuit G is detachably connected to the address bus line AB, data bus line DB, R/W signal and chip designation signal _CS3 . This sound generation circuit G includes a sound control section 9 and a sound conversion circuit 1.
0 and a speaker 11, and data is written to the audio buffer BB provided in the audio control section 9. Then, the audio buffer BB outputs a sound generation signal from the time the data is given until the output of the sound corresponding to this data is completed. This sound generation signal and the printing signal are transmitted as a busy signal via a line m connected by a wired OR.
Given to CPU7 as PY. Furthermore, the audio control section 9 and the audio conversion circuit 10 are connected to the bus lines B ₁ , B ₂ ,
Data is exchanged via _B3 . and,
The audio conversion circuit 10 converts the given data into audio data and outputs it to the speaker 11.

FIG. 2 is a circuit configuration diagram showing the CPU 7 in detail, and reference numeral 12 in the figure is a program storage section consisting of a ROM (read only memory), in which various microinstructions are stored. This program storage section 12 provides an address signal to the address control section 13 via line _l1 , and also sends an operation code and a next address signal specifying the next address of the program storage section 12 to the control section via line _l2 . Give to 14. Then, the control section 1
A next address signal is applied from 4 to the program storage section 12 via line _l3 , and microinstructions are sequentially output.

The control unit 14 decodes the applied operation code and outputs a designation signal for designating addition or subtraction to the calculation unit 15 via line _l4 . The control unit 14 also controls the R/W signal,
In addition to outputting chip designation signals CS ₁ to ₄ , line l ₅
The R/W signal is outputted to the storage unit 16 via. Further, the control unit 14 changes the next address according to the data provided via line _l6 and the presence or absence of a carry. In addition, the control unit 14 is connected to the line _l7.
A signal designating count-up or count-down is output to the address counter in the address control section 13 via the address control section 13. Furthermore, the control section 14 provides a control signal to the gate of the three-state buffer 17. The busy signal PY is input to this three-state buffer 17, and when the control signal is applied, the busy signal PY is inputted through the line _l8 .
PY is output, but line _l8 is kept at high impedance when the control signal is not applied.

FIG. 3 is a circuit configuration diagram showing the audio control section 9 in detail. The chip designation signal _CS3 is applied to the S side input terminals of the flip-flops 18 and 19, and the set output of the flip-flop 18 is a writing signal BY.
The set output of the flip-flop 19 is output as the input signal IN to the audio conversion circuit 10 via the bus line _B3 , and the set output of the flip-flop 19 is also output as the audio generation signal. In addition, the voice buffer BB has a storage capacity of 12 digits each with 4 bits.
The address bus line AB, multiplexer 2
Address data given via 0 and R/
According to the W signal, data applied via the data bus line DB is written. The address data is also given to the address decoder 21, and when the address data indicating the 12th digit is detected, a reset signal is output to the R-side input terminal of the flip-flop 18, and the output of the writing signal BY is stopped. do. Further, the multiplexer 20 is supplied with the chip designation signal CS' via the bus line _B2 , and after its input state is switched, the chip designation signal CS' is applied to the multiplexer 20 via the bus line _B2 .
The data in the audio buffer BB is read out via the bus line _B1 in accordance with the R/W' signal provided via the address bus line AB' and the address data (provided via the address bus line AB'). Further, an end signal EN is applied to the R side input terminal of the flip-flop 19 via the bus line _B3 , and the input signal
Output of IN and audio generation signals stops.

FIG. 4 is a schematic circuit diagram of the voice conversion circuit 10, in which the CPU 22, the synthesizer 23 and the ROM 24
It consists of The CPU 22 exchanges data with the audio control unit 9 via bus lines B ₁ , B ₂ , and B ₃ and also exchanges data with the synthesizer 23 . Also, CPU
22 is provided with an M register having a storage capacity of 12 digits of 4 bits each, and data read from the audio buffer BB is written into this M register. Further, the ROM 24 stores analyzed data of the audio to be output. Further, the synthesizer 23 includes a CPU 22 and a ROM 24.
and the interface section provided between the
After reading data from the ROM 24 and performing calculations according to the read data, this audio data is converted into an analog quantity by a D/A converter and output to the speaker 11. be done.

(2) Operation Next, the operation of this invention will be explained. It is now assumed that the audio generating circuit G is connected to the electronic register. Then, A of the storage unit 16
In the register, as shown in Figure 5A, mode data indicating the setting mode status of the mode switch is placed in digit _A0 , and input amount data is placed in digits _A1 to _A8 .
A ₉ contains guidance data indicating the type of amount data stored (subtotal, total, change, etc.).
It is assumed that the input department data is stored in A ₁₀ and A ₁₁ , respectively. At this time, display/print operations are executed in the CPU 7 of the electronic register according to the flow shown in FIG. That is, in executing step _S1 , a control signal is output from the control section 14 to the three-state buffer 17, and it is determined whether or not there is a busy signal PY. A determination is made as to whether or not a voice generation signal is being outputted, and if it is determined that a voice generation signal is being output, the process waits until both the printing and voice generation operations are completed and the busy signal PY disappears, and then the process moves to step _S2 . In executing step _S2 , the chip designation signal is sent from the control unit 14.
_CS3 is output and the data stored in the A register is transferred to the display buffer HB. Similarly, the data stored in the A register is also written to the audio buffer BB. Then, as shown in FIG. 5B, the display controller 6 decodes the data, and the amount data is displayed on the amount display section 5a of the display section 5, the department data is displayed on the department display section 5b, and the mode display section 5c displays the amount data. indicates the setting mode, and the type of amount data is displayed on the guidance display section 5d.
Each light is displayed using an LED (light emitting diode). Next, the process moves to step _S3 , where the chip designation signal _CS2 is output from the control section 14, and the data in the A register is transferred to the print buffer PB.
Similarly, the printing control unit 4 outputs a printing signal, and the data is decoded and printed on recording paper in the printing unit 3.

On the other hand, the flow according to FIG. 7 is also executed in the CPU 22 of the voice conversion circuit 10. That is, in executing step _S11 , whether or not the input signal IN (sound generation signal) is provided from the audio control section 9, in other words, the chip designation signal _CS3 is output from the control section 14 and the flip-flop 19
A determination is made as to whether or not the output is set, and if it is determined that there is no output, the system waits until there is an output.
If it is determined that there is an output, then the process moves to step _S12 , where it is determined whether the writing signal BY is being given or not, in other words, whether the flip-flop 18 has been set and data is currently being written to the audio buffer BB. If it is determined that there is a write signal BY, the CPU 22 waits until the write operation is completed, and if it is determined that there is no BY signal, the CPU ₂₂ Chip designation signal CS' is output and multiplexer 2
After the input state of 0 is switched, the data stored in the audio buffer BB is written to the M register of the CPU 22. Next, the process moves to step _S14 , where the CPU 22 reads the digit _M0 of the M register.
The setting mode state is determined from the mode data stored in the . Next, proceed to step _S15 ,
The type of amount data stored in digits _M1 to _M8 is determined from the guidance data stored in digit _M9 of the M register. Next, proceed to step _S16 ,
Audio data is created in the synthesizer 24 based on the determined mode and guidance, and is sent to the speaker 11 to output audio. Next, the process moves to step _S17 , and when the voice generation is finished, the CPU 22 outputs an end signal EN to the voice control section 9, and the flip-flop 19 is reset. As a result, the input signal IN and the voice generation signal are output. stops, and after this the step
Return to _S11 .

In this way, from the A register to the display buffer HB
When the data is transferred to the audio buffer BB, the data is also written to the audio buffer BB and displayed on the display section 5, and the audio corresponding to the data is generated. At the same time, the data is printed in the printing unit 3, and during this printing period and during the sound generation, a busy signal PY is applied, and the output of the next data is awaited.

In the above embodiment, when the data in the A register is transferred to the display buffer HB in step _S2 , the audio control unit 9 is also specified by the chip designation signal _CS3 , and the data is also transferred to the audio buffer BB. However, as shown in FIG. 8, when transferring the data in the A register to the print buffer PB, the audio control unit 9 may also be configured to simultaneously designate a chip and write the data.

Further, in the embodiments described above, the present invention is applied to an electronic register, but the present invention is not limited thereto, and can be applied to an electronic device having at least a display section or a printing section.

Further, in the above embodiment, the sound generation circuit G is connected to the electronic register in a detachable manner, but the sound generation circuit G may be connected in a fixed manner. It is not limited to the examples.

[Effects of the Invention] According to the present invention, the data displayed or printed by the data processing device can be directly used for voice generation, which is advantageous when adding a voice output device as an option, and furthermore, the voice generation function is Even when a voice generation function is added to a data processing device that does not have a voice generation function, it is possible to eliminate the burden of changing stored programs.

[Brief explanation of the drawing]

Fig. 1 is a schematic system configuration diagram showing an embodiment in which the present invention is applied to an electronic register, Fig. 2 is a detailed circuit diagram of the CPU of the embodiment, and Fig. 3 is a detailed diagram of the voice control section of the embodiment. FIG. 4 is a schematic circuit diagram of the voice conversion circuit of the same embodiment, and FIG. 5 shows a route through which data stored in the storage section of the electronic register of the same embodiment is displayed and sound is generated. A schematic explanatory diagram, FIG. 6 is a flowchart executed at the time of display/printing in the CPU equipped in the electronic register of the same embodiment, and FIG. 7 is a flow chart executed in the CPU equipped in the voice conversion circuit of the same embodiment. The flowchart shown in FIG. 8 is a schematic explanatory diagram showing the route by which data stored in the storage section of the electronic register of the same embodiment is printed and audio is generated. 3...Printing unit, 4...Printing control unit, 5...Display unit, 6...Display control unit, 7...CPU, 9...Audio control unit, 10...Audio conversion circuit, 11...Speaker, 22...CPU, 23...Synthesizer, 24...
...ROM, G...Sound generation circuit.

Claims (1)

[Claims] 1. A storage means for storing a series of data consisting of numerical data and guidance data indicating the type of this numerical data, a transfer means for transmitting the data stored in this storage means to a display section or a printing section, and this transfer means is detachably connected to a connection line connecting the display section or the printing section,
audio data storage means in which data identical to the data is written as audio output data when the data is transferred by the transfer means; A data processing device equipped with a voice output function, comprising a voice generating means that converts numerical data into voice and outputs the voice.