JPS63156120U - - Google Patents

Info

Publication number
JPS63156120U
JPS63156120U JP4773087U JP4773087U JPS63156120U JP S63156120 U JPS63156120 U JP S63156120U JP 4773087 U JP4773087 U JP 4773087U JP 4773087 U JP4773087 U JP 4773087U JP S63156120 U JPS63156120 U JP S63156120U
Authority
JP
Japan
Prior art keywords
varying
control circuit
clock control
filter
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4773087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4773087U priority Critical patent/JPS63156120U/ja
Publication of JPS63156120U publication Critical patent/JPS63156120U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Filters That Use Time-Delay Elements (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案による多重化フイルタの一実施
例を示すブロツク図、第2図は第1図における多
重化フイルタの構成例を示す回路図、第3図は第
2図における各アナログスイツチを駆動する可変
サンプリングクロツクのタイムチヤート、第4図
は従来の多重化フイルタの一例を示すブロツク図
、第5図は第4図における多重化フイルタの構成
例を示す回路図である。 1……スイツチトキヤパシタフイルタ、2……
スイツチトレジスタ回路、3……クロツク制御回
路。
FIG. 1 is a block diagram showing an embodiment of the multiplexing filter according to the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the multiplexing filter in FIG. 1, and FIG. 3 shows each analog switch in FIG. FIG. 4 is a block diagram showing an example of a conventional multiplexing filter, and FIG. 5 is a circuit diagram showing an example of the configuration of the multiplexing filter in FIG. 4. 1... Switch capacity filter, 2...
Switch register circuit, 3...clock control circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] サンプリング周波数を可変させるクロツク制御
回路と、このクロツク制御回路によりカツトオフ
周波数を可変としたスイツチトキヤパシタフイル
タおよびスイツチトレジスタ回路を設け、モノリ
シツクIC化されたことを特徴とする多重化フイ
ルタ。
1. A multiplexed filter comprising a clock control circuit for varying a sampling frequency, a switch capacitor filter and a switch register circuit for varying a cutoff frequency by the clock control circuit, and formed into a monolithic IC.
JP4773087U 1987-04-01 1987-04-01 Pending JPS63156120U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4773087U JPS63156120U (en) 1987-04-01 1987-04-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4773087U JPS63156120U (en) 1987-04-01 1987-04-01

Publications (1)

Publication Number Publication Date
JPS63156120U true JPS63156120U (en) 1988-10-13

Family

ID=30868611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4773087U Pending JPS63156120U (en) 1987-04-01 1987-04-01

Country Status (1)

Country Link
JP (1) JPS63156120U (en)

Similar Documents

Publication Publication Date Title
JPS63156120U (en)
JPS63156119U (en)
JPH02133018U (en)
JPS62181038U (en)
JPS6454416U (en)
JPS6190324U (en)
JPS61116437U (en)
JPH0167822U (en)
JPS625722U (en)
JPS6380602U (en)
JPS63136410U (en)
JPS61103969U (en)
JPS62154634U (en)
JPS5927632U (en) A/D converter
JPS6361808U (en)
JPH01179275U (en)
JPH02115224U (en)
JPS6387816U (en)
JPS63200902U (en)
JPS6114526U (en) RC filter for power supply
JPH0160526U (en)
JPS6170417U (en)
JPS6367874U (en)
JPS63153995U (en)
JPS6344434U (en)