JPS63155970A - Vertical resolution correcting circuit - Google Patents

Abstract

PURPOSE:To attain vertical resolution correction in double speed conversion without narrowing the band of a luminance signal by using a band limit circuit so as to limit the band of one of two luminance signals having different bands so as to add both the signals. CONSTITUTION:A double speed luminance signal Y5 given to a transistor (TR) 18 is subject to band limit up to the same band of a double speed luminance signal, inverse of Y6 inputted to a TR 19 by a band limit circuit 31 (filter) comprising resistors 32, 33 and a capacitor 34. Then the signal is added to the signal, inverse of Y6, and only the rewriten signal of double speed is extracted by a blanking circuit 16 and the result goes to a correction signal D2. Since no high frequency is supplied to the correction signal D2 generated in such a way, even when a difference is operated between the double speed luminance signal Y5 and the correction signal D2 by using a differential amplifier comprising TRs 20, 21, a resistor 28 and a constant current source 30, the luminance signal is corrected without decreasing the characteristic of high frequencies.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical resolution correction circuit in double speed conversion.

2. Description of the Related Art In recent years, as digital signal processing of television signals has progressed, circuits for improving image quality have been widely introduced.

One such method is double-speed conversion, but simple double-speed conversion using a line memory has the problem of lowering vertical resolution. In order to solve this problem, a vertical resolution correction circuit has been devised.

A conventional vertical resolution correction circuit will be described below with reference to the drawings. FIG. 3 is an overall configuration diagram of a conventional vertical resolution correction circuit, and FIG. 4 is a specific circuit diagram of an analog circuit that is the central part thereof. In Figure 3, 1 and 9 are A/D
Converter, 2 is a digital signal demodulation circuit with a 1-line delay circuit, 3 is a double speed conversion circuit, 4 to e and 13 are D/A converters, 7 is an RGB conversion circuit, 8 is a CRT display device, 1o is a video signal 11 is an inverter circuit, 12 is a double speed conversion circuit, 14 is an analog addition circuit that adds two brightness signals Y5 and -Y6, and 16.16 is a double speed signal writing circuit. A blanking pulse generation circuit and a blanking circuit are used to extract signals, and 17 is an analog subtraction circuit that takes the difference between the original signal Y6 and the correction signal D2. Further, in FIG. 4, 18 to 22 are transistors, 23 to 28 are resistors, 29 is an electrolytic capacitor, and 3o is a constant current source.

Video signal A is digitized by A/D converter 1,
The digital signal demodulation circuit 2 uses a comb filter to generate a luminance signal Y1 and a color difference signal U1. ■Separated into 1. At this time, the luminance signal Y1 is delayed by one line. Signal Y1. U1. V1 are converted into double speed signals Y3. U3.
V3, and further converted into analog signals Ys, U5, and V5 by D/A converters 4-6. On the other hand, a signal digitized using another A/D converter 9 is passed through a color signal trap 1o and an inverter 11 to obtain a luminance signal -Y2. Since Yl and -Y2 are delayed by one line in the digital signal demodulation circuit 2, -Y2 is 1H ahead in phase. Also, the polarity should be reversed. -Y2 is also Y
Similarly to 1, double speed conversion circuit 12. It passes through the D/A converter 13 and is converted into a double-speed analog luminance signal -Y6. If the video signal A is as shown in Figure 5 a and b, Y5 and -
Y6 is as shown in c and d of the figure, respectively. Further, the blanking pulse generating circuit 15 generates a blanking pulse B (FIG. 6e) that is high for half of the 1H period and low for half of the 1H period.

FIG. 4 shows a specific example of an analog circuit that receives the above three signals Ys, -Ys, and B as inputs. Y5 and -Y6 are respectively input to the paces of transistors 18 and 19, and their emitter outputs are summed together through resistors 26.26 to obtain the sum signal D1 (FIG. 5f), but the blanking pulse B The transistor 22, which performs a switching operation, extracts only the second write signal at double speed.

Moreover, the level can be adjusted by dividing the resistors 25, 26, and 27. In this way, the correction signal D as shown in FIG.
2 is obtained, transistor 20.21 and resistor 28. D2 is connected to one side of a differential amplifier composed of a constant current source 3o and a constant current source 3o.
By inputting the Y5 signal to the other side and taking the difference, a signal in which the Y5 luminance signal has a transient luminance change suppressed as shown in the fifth diagram can be obtained. Similarly, for field 2, the signal shown in Figure 1 is obtained, and when it is subjected to the eye integration effect on the CRT display device 8, it appears as shown in Figure 5, and when compared with the signal k in the same figure when no correction is made. The level of the signal in the portion indicated by the arrow in the figure is closer to that of the interlaced signal (a, l in the figure).

Problems to be Solved by the Invention However, in the above configuration, two luminance signals Y
5 and -Y6 have different signal processing methods; Y5 is a broadband signal that is separated from the color signal by a comb filter, whereas -YeO only traps the color signal in a single call. The video frequency band is just under 3MHz. Therefore, when the two are added, the high frequency components of the signal are extracted and added to the correction signal, resulting in the original signal Y5
The problem was that when the difference was taken, the high range of the Y6 was lost.

In view of the above problems, the present invention provides a vertical resolution correction circuit that prevents a decrease in vertical resolution without narrowing the band of a luminance signal.

Means for Solving the Problems In order to solve the above-mentioned problems, the vertical resolution correction circuit of the present invention includes a band limiting circuit which receives the 10th speed luminance signal as input, and a band limiting circuit that receives the 10th speed luminance signal as input, and the output thereof and the 20th speed brightness signal into two circuits. An analog addition circuit as an input, a blanking circuit for obtaining a blanking signal during the second horizontal scanning period among the double speed signals of the output thereof, and the output of this blanking circuit and the first double speed luminance signal. It is equipped with an analog subtraction circuit that takes two inputs.

Effect The present invention has the above-described configuration, and the two analog adder circuits are
By making the bands of the two double-speed luminance signal inputs the same, it is possible to prevent high-frequency components from appearing in the correction signal and to guarantee the luminance signal band to the high-frequency range.

Embodiment Below, regarding a vertical resolution correction circuit according to an embodiment of the present invention,
This will be explained with reference to the drawings.

FIG. 1 is a block diagram of a vertical resolution correction circuit according to an embodiment of the present invention, and FIG. 2 is a specific example of the circuit.

In FIG. 1, 31 is a band-limiting circuit which inputs the double-speed luminance signal Y6; 14 is an analog addition circuit that adds the output of this band-limiting circuit 31 and another double-speed luminance signal -Ye;
Reference numeral 17 denotes a blanking circuit that extracts only the double-speed double writing using the output of the analog adder circuit 14, and 17 a subtraction circuit that performs subtraction processing between the double-speed luminance signal Y5 and the output of the blanking circuit 16. It is.

In addition, in FIG. 2, 18 to 22 are transistors, and 23 to 22 are transistors.
28 and 32.33 are resistors, 29 is an electrolytic capacitor, 3
o is a constant current source, and 34 is a capacitor.

The Y5 double-speed luminance signal input to the transistor 18 in FIG. Bandwidth is limited. Then, it is added to -Ye, and the blanking circuit 16 extracts only the double-speed write twice, resulting in the correction signal D2. Since the correction signal D2 created in this way does not contain high-frequency components, the transistor 2
0.21 and resistance 28. Even if the difference between the double-speed luminance signal Y6 and the correction signal D2 is taken by the differential amplifier constituted by the constant current source 30, it is possible to correct the difference without reducing the high frequency range of the luminance signal.

As described above, according to this embodiment, by providing the luminance signal band limiting circuit 31, the vertical resolution can be corrected without narrowing the luminance signal band.

Effects of the Invention As described above, the present invention limits the band of one of two luminance signals with different bands using a band limiting circuit and then adds the two, thereby achieving vertical conversion in double speed conversion without narrowing the band of the luminance signal Resolution correction can be performed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the main parts of a vertical resolution correction circuit according to an embodiment of the present invention, Fig. 2 is a specific circuit diagram realizing the same circuit, and Fig. 3 is an overall block diagram of a conventional vertical resolution correction circuit. 4 is a specific circuit diagram of the analog circuit portion in FIG. 3, and FIG. 5 is an operational waveform diagram thereof. 14... Analog addition circuit, 16...
Blanking circuit, 17...analog subtraction circuit, 31...bandwidth limiting circuit. Name of agent: Patent attorney Satoshi Nakao and one other person I4-
Like analog! Circuit 17- Analog adder circuit Figure 1 C reference l8~? 2- Transistor 23~? 8.3233-Resistance 29- Electrolytic contact length %-Core length +V Figure 4

Claims (1)

[Claims] A band limiting circuit that receives a first double-speed luminance signal as an input and limits its band; an analog addition circuit that receives the output of the band-limiting circuit and a second double-speed luminance signal as two inputs; and an output of the analog addition circuit. a blanking circuit that obtains a blanking signal during the second horizontal scanning period among the double-speed signals; and an analog subtraction circuit that receives the output of this blanking circuit and the first double-speed luminance signal as two inputs. A vertical resolution correction circuit characterized by comprising: