JPS63155500A - Readout device for ram building-in lsi - Google Patents

Abstract

PURPOSE:To easily know information of a built-in RAM, and to easily execute its test by providing a means for supplying a testing address to the built-in RAM, and a means for outputting readout data of that time to the outside of an LSI. CONSTITUTION:In case of executing a test of the built-in RAM 9, a test mode is designated by a mode switching signal 15, and also, a readout clock 13 is inputted from a terminal 14, by which a testing readout address 12 generated by an address generating means 7 is selected in an address selecting means 8, and supplied to the built-in RAM 9. Readout data 17 from the built-in RAM 9 is selected for every 1 bit in a readout bit selecting means 11, and outputted as 1-bit data 18 to the outside of an LSI 6 from a readout data output terminal 19. By said operation, direct access from the outside of the built-in RAM 9 can be executed, and its test can be executed easily.

Description

[Detailed Description of the Invention] Summary] The present invention provides an R
During an AM test, the LSI has a means for supplying a read address for testing to the built-in RAM by mode switching from outside the LSI in order to read the contents, and furthermore, the data read from the built-in RAM at that time is sent to the outside of the LSI. This is an LSI built-in RAM reading device that can easily know built-in RAM information by having an output terminal.

[Industrial application field]

The present invention relates to a content reading device for testing a RAM built into an LSI.

[Traditional techniques]

LSIs are usually constructed from complex combinational circuits, and in this case, many include built-in RAM in order to realize more complex and programmable control operations.

FIG. 3 shows its general configuration, which includes a combinational circuit 1 to which an input/output pin 5 is connected, and a built-in RAM 2 that operates according to a specified address 3 from the combinational circuit 1. Data 4 is fed to the combinational circuit 1. In addition, from the combinational circuit 1 to the built-in RAM
In the case of writing to 2, although not shown, it can be considered in the same way, only that the input/output direction of the data is reversed.

When testing an LSI with the above configuration, when it is desired to read the information in the built-in RAM 2, conventionally, by inputting a test signal with various conditions set from the input/output pin 5,
By controlling the specified address 3 to set the address of the built-in RAM 2, and outputting the read data 4 from the built-in RAM 2 to either of the input/output pins 5 via the combinational circuit 1, the data from the built-in RAM 2 is set. He was showing off his emotions.

[Problem that the invention seeks to solve]

However, in the case of the above conventional example, the built-in RAM 2 plays a larger role as a control means for the combinational circuit 1 than as a data buffer between the LSI and the outside, and the address of the built-in RAM 2 is directly accessed from outside the LSI. It is difficult to read the data from the LSI
It is also difficult to take it out. Therefore, in order to perform the above operation via the combinational circuit 1, the condition setting of the test signal input from the input/output pin 5 becomes extremely complicated, which may be impossible especially in LSIs that perform complex functions. However, there was a problem in that the test could not be carried out easily.

In order to solve the above problems, the present invention provides a circuit that generates a read address for testing inside the LSI, supplies the address to the built-in RAM by external mode switching, and further transfers the read data in that case to the LSI. It is an object of the present invention to provide an LSI built-in RAM readout device that enables easy testing of internal gcRAM by having a terminal for outputting to the outside.

[Means for solving problems]

In order to solve the above problems, the present invention has a basic configuration shown in FIG. 1. That is, a combinational circuit 10 having input/output pins 21 and a built-in RAM (random access memory).
9, an address generating means 7 for generating a read address 12;
Select either the read address 12 or the specified address 20 from the combinational circuit 10, and read the address from the built-in RAM.
9, a read clock input terminal 14 for supplying a read clock 13 from outside the LSI 6 to the address generating means 7, and a mode switching signal input for supplying a mode switching signal 15 to the address selecting means 8. It has a terminal 16 and also has a built-in RA.
It has a read data output terminal 19 that outputs read data 17 from M9 to the outside of LSI 6.

In this case, more specifically, it has a read bit selection means 11 that sequentially selects the read data 17 bit by bit and outputs it as 1-bit data 18.

[For production]

In each of the above means, when the LSI 6 is operated normally, the mode switching signal 15 specifies the normal mode. As a result, the address selection means 8 selects the combinational circuit 1.
A designated address 20 from 0 is selected and supplied to the built-in RAM 9 to perform normal operation.

On the other hand, when testing the built-in RAM 9, the test mode is designated by the mode switching signal 15, and the read clock 13 is input from the terminal 14. As a result, the test read address 12 generated by the address generation means 7 is selected by the address selection means 8 and supplied to the built-in RAM 9. At this time, the read clock 13 supplied to the address generating means 7 is normally
It is input from the read clock input terminal 14, but the LS
The internal clock of I6 may also be used. As a result, the read data 17 from the built-in R8M9 is selected bit by bit in the read bit selection means 11, and is output from the read data output terminal 19 as 1 bit data 18 to the LS.
Output to the outside of I6.

The above operation enables direct access to the built-in RAM 9 from the outside, making it easy to test it.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail.

(Circuit configuration of an embodiment of the present invention (FIG. 2)) FIG. 2 shows an embodiment in which FIG. 1 is specifically implemented. In FIG. 2, the first input terminals of AND circuits 26-0 to 26-n are supplied with designated addresses Bo, B+, . . . , B, from the combinational circuit 24 (corresponding to 10 in FIG. 1). (corresponding to 20 in Figure 1) is input, and the mode switching signal RM (corresponding to 15 in Figure 1) from input terminal 30 (corresponding to 16 in Figure 1) is input to each second input terminal. input. On the other hand, each of the first input terminals of the AND circuits 27-O to 27-n receives a read address Ao, which is determined by the lower bit output Eo=En of the counter 22 (corresponding to 7 in FIG. 1).
A+, ..., An (corresponding to 12 in Fig. 1) are input, and the same (mode switching signal RM
A signal inverted by impark 29 is input. and,
Each output of the AND circuits 26-0 to 26-n is connected to the OR circuit 2.
The outputs of the AND circuits 27-0 to 27-n are input to the respective second input terminals of the AND circuits 27-0 to 28-n, and the outputs of the AND circuits 27-0 to 27-n are input to the second input terminals of the OR circuits 28-0 to 28-n. -n outputs are input to each address input terminal C01C1, . . . , Cn of the built-in RAM 23 (corresponding to 9 in FIG. 1). Here, AND circuits 26-O to 26-n, 27-0 to 27-
n, OR circuits 2B-0 to 28-n, and inverter 29
corresponds to 8 in FIG. Next, each read data output dosd, +, ..., dK (first
17 in the figure) is input to the combinational circuit 24 and also to the multiplexer 25 (corresponding to 11 in FIG. 1). The 1-bit data Do (corresponding to 18 in FIG. 1) from the multiplexer 25 is output from the output terminal 33 to the outside of the LSI. Also, multiplexer 2
5, the upper bit outputs of the counter 22 E~, ~f3.
Select signals So, S+, ..., S, determined by Cow-+1
, l are input to the counter 22, and the input terminal 31 is input to the counter 22.
A read clock CLK and a reset signal R3T are input from 32 and 32, respectively.

(Operation of the embodiment of the present invention (FIG. 2)) Next, the operation of the above embodiment will be explained. First, when the LSI shown in FIG. 2 is to be operated normally, a high level signal indicating normal operation is inputted from the input terminal 30 as the mode switching signal RM. As a result, the AND circuit 26-0
26-n operates, and the AND circuits 27-0 to 27-n are turned off by the impedance controller 29, and the designated address Bθ, B l % from the combinational circuit 11PF24 is turned off.
..., Bn is connected to the address input terminal C'0%CI% of the built-in RAM 23 via the OR circuits 28-0 to 2B-n.
..., c.

Enter. That is, the built-in RAM 23 is connected to the combinational circuit 24.
The read data output d O%
d+, . . . , dK are fed back to the combinational circuit 24. At this time, since the counter 22 is not operating, the multiplexer 25 is also not operating, and no data appears at the output terminal 33.

Next, when testing the built-in RAM 23, a low level signal representing a test mode is inputted from the input terminal 30 as a mode switching signal RM.

As a result, the inverter 29 causes the AND circuit 27-
0 to 27-n are turned on, and the AND circuits 26-0 to 26
-n is turned off, allowing the read addresses Ao, A+, . . . , An from the counter 22 to be input. Subsequently, the counter 22 is reset to the reset signal input from the input terminal 32.
After the readout clock CLK is input from the input terminal 31, the readout clock CLK is sequentially inputted from the input terminal 31. This results in
The counter 22 starts counting and its lower bit output E
O%E1, ..., read address Ao by En,
AI, . . . , An are sequentially specified and supplied to address input terminals Co, C+, . . . , C1 of the built-in RAM 23. At this time, the upper bit output of the counter 22 E%95
, E, L(-□,..., Eyachi1 are all "0" until the lower bit outputs Eo, E+,...En all become "1". In other words, the outputs to the multiplexer 25 Select signals So, S+, . . . , S l.

Initially, the read address A is O%Δ1, . . .Δ.

All values are 0'' until all are specified.

As a result, in the multiplexer 25, the built-in R
AM23 read data output do, d+, ..., d
Of K, only one bit of dO is selected and read data do corresponding to each address designation is sequentially outputted from the output terminal 33 as one-bit data Do. Next, when all read addresses Ao, 81, ..., An are specified by the counter 22, the upper bit output EfL
The value of ++ becomes 1'', and the select signal So becomes 1''.

Then, the read address Ao,,A+,...,Ar
l starts counting from O again. As a result, read data d1 of the built-in RAM is selected in the multiplexer 25, and read data d1 for all addresses of the built-in RAM 23 are sequentially outputted from the output terminal 33.

In this way, the upper bit output Ran~E of the counter 22
Built-in RA at multiplexer 25 by %+3*l
Each read data dO to dK of M23 is sequentially selected,
Every time the above read data is selected by the lower bit output E Osy Eo of the counter 22, all of the read addresses AO to Ao are specified.

The above operation makes it possible to sequentially read the contents of each bit of all addresses in the built-in RAM 23 from the output terminal 33. At this time, in this embodiment, the multiplexer 25 converts the read data do, d11, . It is possible to design the LSI without changing the size of the LSI.If there is enough room for the LSI size,
The multiplexer 25 may be configured to output all the read data dO-dK.

Further, the read clock CLK may be shared with the clock of the LSI main body, and in that case, the input terminal 31 is not required.

〔Effect of the invention〕

According to the present invention, by having the means for supplying a test address to the built-in RAM and the means for outputting the read data at that time to the outside of the LSI, it is possible to easily know the built-in RAM information, and the test It becomes possible to do this easily.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 3 is a configuration diagram of a conventional example. 6...LSI. 7...Address generation means, 8...Address selection means, 9...Built-in RAM. DESCRIPTION OF SYMBOLS 10... Combinational circuit, 11... Read bit selection means, 12... Read address, 13... Read clock, 15... Mode switching signal, 16... Mode switching signal input terminal, 17... ...Read data, 18...1 bit data, 19...Read data output terminal, 20...Specified address.

Claims (1)

[Claims] 1) A large-scale integrated circuit (6) consisting of a combinational circuit (10)
) built-in random access memory (9
), a predetermined read clock (13) is used when reading the data.
address generating means (7) for supplying a read address (12) to the built-in random access memory (9) according to the
) and the specified address (20) from the combinational circuit (10).
or address selection means (12) that selects one of the read addresses (12) from the address generation means (7) and supplies it to the built-in random access memory (9);
8), and a mode switching signal (15) for causing the address selection means (8) to select an address, to the large-scale integrated circuit (6).
a mode switching signal input terminal (16) for supplying from the outside of the built-in random access memory (9); and a read data output terminal (16) for outputting read data from the built-in random access memory (9) to the outside of the large-scale integrated circuit (6). 19) An LSI built-in RAM reading device comprising: 2) The read data output terminal (19) is a 1-bit output, and each bit of the read data (17) from the built-in random access memory (9) is sequentially selected and output as 1 bit.
2. The LSI built-in RAM reading device according to claim 1, further comprising read bit selection means (11) for outputting bit data (18) to said read data output terminal (19) in units of bits. 3) The address generating means (7) includes one counter (22) that operates according to the read clock (13).
The predetermined lower bits (E_0 to E_n) of the counter (22) are set to the read address (12).
), and the read bit selection means (11)
is the lower bit (E_0~E_0~) of the counter (22).
Predetermined upper bits (E_n_+_1 to E_n) other than E_n)
_n_+_n_+_1), the read data (1
7) sequentially select each bit of 1-bit data (18)
3. The LSI built-in RAM reading device according to claim 1, characterized in that it is constituted by a multiplexer (25) that outputs the read data to the read data output terminal (19) in units of 1 bit.