JPS63153970A - Photoelectric converter - Google Patents

Abstract

PURPOSE:To suppress the signal of a photoelectric converting picture element from being lowered due to capacitance division, by providing plural capacitance means which hold the signal of each picture element transiently, and plural amplifiers less than the capacitance means which amplify in order the signal held by the capacitance means. CONSTITUTION:Plural capacitors CTn (n is integer) which hold the signal of each picture element transiently are provided for each signal line VSL. Also, plural buffer amplifiers S-Trm (m is integer) which amplify the signals held by the capacitors CTn in order are provided. The number of the buffer amplifiers are set less than that of the capacitors. And the outputs of the buffer amplifiers S-Trm are supplied to a common amplifier 4. In such way, it is possible to suppress the lowering of the output due to the capacitance division. Also, since it is not required to provide the buffer amplifier for every capacitor, the constitution of a circuit can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a photoelectric conversion device, and particularly to a photoelectric conversion device formed on a semiconductor substrate.

<Prior Art> Some conventional photoelectric conversion devices transfer signals generated and accumulated in a photoelectric conversion region to a first capacitive region provided separately from the photoelectric conversion region, and then This device transferred signals accumulated in a capacitive area to a second capacitive area, and outputted the signals accumulated in the second capacitive area to the outside. An example of such a conventional photoelectric conversion device will be explained using FIG. 5.

FIG. 5 is a circuit diagram of a photoelectric conversion device in which basic optical sensor cells 30 are two-dimensionally arranged in a 3×3 arrangement.

In FIG. 5, 30 is a basic photosensor cell, which accumulates carriers generated by photoexcitation in the PN junction of a bipolar transistor in its base region, sets the output line connected to the emitter region in a floating state, and connects the capacitor connected to the base. The carriers accumulated in the base region are non-destructively read out by applying a positive pulse to the base through the emitter region, and the output line connected to the emitter region is grounded, for example, and a positive pulse is applied to the base through the yapacitor. By doing so, carriers accumulated in the base region are erased. This will be explained below with reference to the drawings. The conventional photoelectric conversion device shown in FIG. 5 includes horizontal lines 31, 31', 31' for applying read pulses and refresh pulses, a vertical shift register 32 for generating read pulses and refresh pulses, and a vertical shift register. Buffer M between 32 and horizontal line 31° 31', 31'
O5) Terminal 34 for applying gate pulses of transistors 33° 33', 33', and basic optical sensor cell 3
Vertical line 38.38 for reading the stored voltage from o
', 38', horizontal shift register 39 that generates pulses for selecting each vertical line, gate MOS transistor 40.4 for opening and closing each vertical line.
0'.

40', an output line 41 for reading out the accumulated voltage to the amplifier section; A MOS transistor 42 for refreshing the retained charge accumulated in the column 41 after reading, a terminal 43 for applying a helicopter shock pulse to the MOS transistor 42, a bipolar transistor, MOS, and FET for amplifying the output signal. , a transistor 44 such as a J-FET, a load resistor 45, a terminal 46 for connecting the transistor and a power supply, an output terminal 47 of the transistor,
In the read operation the vertical lines 40, 40',
MOS) transistor 48.48' for refreshing the charge stored in 40'.

48', and MOS) transistor 48. 48'
.

A terminal 49 is provided for applying a pulse to the gate of 48'. In such a photoelectric conversion device, first, the terminal 4
9, MOS transistors 48, 48'
, turn on 48' and set the vertical line 38°38 in advance.
', 38' are grounded and cleared, and then the MOS transistors 48. 48' and 48' are turned on and the horizontal line 31 selected by the vertical shift register 32
, 31', 31' are MOS transistors 33.3
3'.

The vertical lines 38, 38' and 38' are pulsed through 33' and are in a floating state.
The sensor cell 30 is configured to read out signals from the sensor cell 30 at the same time.

Here, the vertical lines 38, 38', 3g' have their own capacitance components, and by this read operation, a signal corresponding to the signal of the sensor cell is held in the vertical line capacitance. Next, the horizontal shift register 39 sequentially selects the MOS transistors 40, 40', 40', and transfers the signals held in the characteristic capacitances of the vertical lines 38, 38', 38' to the control electrode of the transistor 44 via the horizontal line 41. and sequentially output signals corresponding to the output of the sensor cell 30 from the terminal 47.

Also, while applying a pulse through a capacitor connected to the base of the sensor cell, a pulse is applied to the terminal 49 and the vertical line 38.38'.

By grounding 38', carriers accumulated in the base region can be erased.

<Problems to be Solved by the Invention> By the way, in the above-mentioned conventional photoelectric conversion device, the signals held in the specific capacitances of the vertical lines 38, 38' and 38' are sequentially transferred to the control electrode of the transistor 44 via the horizontal line 41. , the level of the signal applied to transistor 44 is determined by the characteristic capacitance of horizontal line 41 and the vertical line 38 . which horizontal register 39 is accessing. 38
Since it is determined by the ratio to the specific capacitance of ' and 38', the level decreases in accordance with the capacity division ratio.

Such a reduction in signal level becomes more noticeable as the number of horizontal pixels increases. This is because the capacity of the horizontal line 41 is approximately that of the gate MO3) transistor 40°40', 40
This is because it increases in proportion to the number of '...'.

Therefore, in order to avoid a drop in signal level, it is necessary to either make the vertical line capacitance thicker, or to use a multi-output line system in which the horizontal line is divided to read out the signal.

However, the former has the disadvantage of increasing the chip area, and the latter has the drawback of increasing the number of output terminals, that is, the number of bins.

Another method is to prevent the signal level from decreasing by inserting an amplifier between the vertical line and the horizontal line. However, this method has disadvantages in that the structure of the amplifier section is complicated, which increases the chip area and further complicates the horizontal shift register section.

The present invention aims to solve the above-mentioned problems.

Means for Solving Problems> The present invention provides a plurality of photoelectric conversion pixels, a plurality of capacitance means for temporarily holding the signal of each pixel, and a plurality of capacitance means for temporarily holding the signal of each pixel. It has a plurality of first amplifiers whose number is smaller than the capacitive means for sequentially amplifying signals, and a common second amplifier for commonly amplifying the outputs of the plurality of amplifiers.

<Function> Signals formed by a plurality of photoelectric conversion pixels are temporarily accumulated by a plurality of capacitive means, and when sequentially reading out the accumulated signals, the signals formed by a plurality of photoelectric conversion pixels are read out sequentially through the first amplifier, which is smaller in number than the capacitive means. Since the output is increased and then read out and guided to a common second amplifier, there is no output drop due to capacitance division, and the configuration is simple because there is no need to provide a first amplifier for all capacitance means. Become.

<Example> The present invention will be described in detail below using the drawings.

FIG. 1 is a diagram showing the configuration of a photoelectric conversion device according to a first embodiment of the present invention, and FIG. 2 is a drive timing chart thereof.

In the figure, 1 is a horizontal shift register which starts with a pulse φH5 and sequentially sets one of its output lines to a high level with pulses φH1 and φH3 having opposite phases.

Note that one of the output lines of the shift register 1 is configured to be at a high level while φH1 is at a high level.

A bipolar transistor 2 has a base connected to a capacitor constituting one pixel, its emitter is connected to the vertical signal line VSL, and its collector is connected to a constant voltage source.

Reference numeral 3 designates a transistor for clearing the residual signal on the vertical signal line VSL while φVC is at the NO1 level.

In addition, T-Tr is a signal line Vst, and a capacitor CTn (n
is an integer).

R-Trn is a transistor for sequentially guiding the signals accumulated in each capacitor CTn to the signal line SL by the scanning output of the shift register.

C-Tr is a transistor for clearing residual charges on the signal line SL.

STrm (m is an integer) is a buffer amplifier, SW −
T r m is a transistor for selectively connecting the power supply VDD to each transistor S-Trm, and a pulse φV
ON while m is at high level. 4 is output amplifier, CPC
is a clamp circuit that clamps to the clamp voltage Vcp at the timing of the pulse φcp.

The feature of this embodiment is that the capacitor CTn is connected to each signal line VSL.
In addition, by providing a buffer amplifier S-Trm to read the signal of this capacitor CTn, the output drop due to capacitance division is suppressed, and the power consumption of this buffer amplifier and the heat generated by it are minimized. It is turned on by φV in order to keep it to a minimum.

In addition, one buffer amplifier is provided for each vertical signal line in order to prevent the chip area from increasing due to the transistors SW-Trm and S-Trm. be.

Next, the operation of this embodiment will be explained based on FIG.

First, unnecessary charges on the vertical signal line VSt and the temporary storage capacitor are 1. will be removed during the period.

Next, during the period t2, the signal of each pixel is CT by φD and φT.
transferred to n. The signal charges accumulated in the CT are read out to the output amplifier 4 via the buffer amplifier STrm by sequentially opening and closing the read transfer transistor R-Tr in synchronization with φH1.

At this time, power is supplied to only the read signal buffer amplifiers S-Trm corresponding to reading.

That is, during the period t3 during which S W −T r l is controlled to be conductive by φV1, the temporary storage capacitance c”r 1 +
This is only the period during which the cT 2 tCT3 signals are read.

The common signal line SL is held at a certain reference potential by a pulse φHC every time one bit is transferred.

This is to remove residual charges and further correct the variation ΔVT in the threshold level of the buffer amplifier 5-Tr. That is, by clamping the portion of the output signal 5out corresponding to the reference voltage with the pulse φcp for each bit, the variation ΔvT can be removed.

Incidentally, the buffer amplifier S-Trm in the embodiment of FIG.
S transistor, but this can be replaced by the second transistor shown in Figure 3.
As in the embodiment (it is possible to replace it with a bipolar transistor. If the buffer amplifier is configured with bipolar transistors, S W -T r m becomes unnecessary. This means that the bias component of the signal on Crn during reading is This is because the bipolar transistor is biased in the forward direction.

Next, FIG. 4 is a diagram showing a third embodiment. In FIG. 4, the power supply transistor S W -T r m is controlled by the output pulses φH1 and φHC of the shift register.

That is, in FIG. 4, the same reference numerals in FIGS. 1 to 3 indicate the same elements and have the same configuration.

In this embodiment, a plurality of transistors D-Trn are provided for the gate of transistor SW-Trm. Furthermore, each 'transistor D-Trn receives the scanning output φ of the shift register 5.
The difference from the configuration shown in the first diagram is that H1 and φHC are sequentially turned on.

The operation will be explained below.

For pulses φHC, φH1, φcp, etc., the second
Drive at exactly the same timing as shown in the diagram. However, φV.

φV,...φvm does not exist.

Assume that a signal is currently stored in the capacitor CTn.

First, D Tr 1 and RTr H are turned on by φI+-1. As a result, SW Tr-1 becomes ONL, CT
, is amplified to STr+ and output to the output line LS.

Next, when φ)(I-1 becomes low level and φ)IC-1 becomes high level, D-Tr 2 and CTr are turned on. As a result, the reference O level is input to the base of the buffer transistor 5Trl, and sw-'rr is also turned on, so that this signal is output to the output line LS.

This signal is φ
) It is clamped with a clamp pulse φcp having the same timing as the IC.

Similarly, φH2. φHC-2 outputs the signal of CT2 and the reference 0 level signal in a dot-sequential manner, and thereafter such operations are sequentially performed.

According to this embodiment, compared to the first embodiment, φV I + φ
V2. . . . Since φVm is no longer necessary, the number of pulse input terminals is reduced and the wiring area can be reduced.

Effects> According to the present invention, it is possible to suppress the reduction in the signal of the photoelectric conversion pixel due to capacitance division without increasing the capacitance means, and furthermore, it is possible to reduce the heat generation by the first amplifier, and it is possible to The configuration can be simplified.

[Brief explanation of the drawing]

Fig. 1 is a diagram of a first embodiment of a photoelectric conversion device of the present invention, Fig. 2 is a timing chart of the first embodiment, Fig. 3 is a main part configuration diagram of a second embodiment, and Fig. 4 is a diagram of a third embodiment. FIG. 5 is a block diagram of a conventional example.

Claims (1)

[Claims] A plurality of photoelectric conversion pixels, a plurality of capacitor means for temporarily holding the signal of each pixel, and a plurality of capacitors whose number is smaller than the number of capacitor means that sequentially amplifies the signal held in each capacitor means. A photoelectric conversion device comprising a first amplifier of the plurality of amplifiers, and a common second amplifier for commonly amplifying the outputs of the plurality of amplifiers.