JPH0817463B2 - Photoelectric conversion device - Google Patents

Description

The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device formed on a semiconductor substrate.

<Prior Art> Some conventional photoelectric conversion devices generate in a photoelectric conversion region,
The accumulated signal is transferred to a first capacitance region provided separately from the photoelectric conversion region, then the signal accumulated in the first capacitance region is transferred to a second capacitance region, and the second capacitance region is transferred to the second capacitance region. It was a device that output the signal accumulated in the capacitance area of the above to the outside. An example of such a conventional photoelectric conversion device will be described with reference to FIG.

FIG. 5 is a circuit configuration diagram of a photoelectric conversion device in which the basic photosensor cells 30 are two-dimensionally arranged in 3 × 3.

In FIG. 5, reference numeral 30 is a basic optical sensor cell, which stores a carrier generated by photoexcitation at the PN junction of a bipolar transistor in the base region, sets an output line connected to the emitter region in a floating state, and a capacitor connected to the base. The carrier accumulated in the base region is read nondestructively by applying a positive pulse to the base via, and the output line connected to the emitter region is grounded, for example, and a positive pulse is applied to the base via the yapasita. By applying the voltage, the carrier accumulated in the base region is erased. The following is a description with reference to the drawings. In the conventional photoelectric conversion device of FIG. 5, horizontal lines 31, 31 ', 31 "for applying the read pulse and the refresh pulse, a vertical shift register 32 for generating the read pulse and the refresh pulse, and a vertical line Shift register 32 and horizontal lines 31,31 ', 3
Terminal 34 for applying the gate pulse of the buffer MOS transistors 33, 33 ', 33 "between 1", and vertical lines 38, 38', for reading the accumulated voltage from the basic photosensor cell 30.
38 ″, horizontal shift register 39 for generating a pulse for selecting each vertical line, gate MOS transistors 40, 40 ′, 40 ″ for opening / closing each vertical line, output for reading the accumulated voltage to the amplifier section Line 41, MOS transistor 42 for refreshing the retained charge accumulated in the force line 41 after reading, terminal 43 for applying a refresh pulse to the MOS transistor 42, bipolar for amplifying the output signal, MOS , A transistor 44 such as FET, J-FET, a load resistor 45, a terminal 46 for connecting the transistor and the power supply, an output terminal 47 of the transistor, and a charge accumulated in the vertical lines 40, 40 ', 40 "in the read operation. MOS transistors 48,48 ', 48 "for refreshing,
And a terminal 49 for applying a pulse to the gates of the MOS transistors 48, 48 ', 48 ". In such a photoelectric conversion device, a pulse is first applied to the terminal 49, and the MOS transistors 48, 48', 48" are provided. Turn on and pre-set vertical lines 38,3
8 ', 38 "grounded to clear, then MOS transistor 4
8,48 ', 48 "is turned on and MOS transistors 33,33 are provided on the horizontal lines 31,31', 31" selected by the vertical shift register 32
Applying a pulse through 33 ', 33 ", the sensor cell 30 is applied to the floating vertical line 38,38', 38".
Is read out. Here, the vertical lines 38, 38 ', 38 "have an inherent capacitance component, and by this read operation, a signal corresponding to the signal of the sensor cell is held in the vertical line capacitance.
The MOS transistors 40, 40 ', 40 "are sequentially selected by 39, and the signal held in the intrinsic capacitance of the vertical lines 38, 38', 38" is applied to the control electrode of the transistor 44 via the horizontal line 41, A signal corresponding to the output of the sensor cell 30 is sequentially output from the terminal 47.

In addition, if a pulse is applied to the terminal 49 and the vertical lines 38, 38 ', 38 "are grounded while a pulse is applied through the capacitor connected to the base of the sensor cell, it is accumulated in the base region. You can erase the carrier.

<Problems to be Solved by the Invention> In the conventional photoelectric conversion device described above, the signals held in the inherent capacitances of the vertical lines 38, 38 ′, 38 ″ are sequentially passed through the horizontal line 41 to the control electrode of the transistor 44. Since the level of the signal applied to the transistor 44 when applied to the horizontal line is determined by the ratio of the specific capacitance of the horizontal line 41 to the specific capacitance of the vertical lines 38, 38 ', 38 "accessed by the horizontal register 39. , The level will decrease according to the capacity division ratio.

Such a decrease in signal level becomes more remarkable as the number of horizontal pixels increases. This is because the capacitance of the horizontal line 41 increases almost in proportion to the number of gate MOS transistors 40, 40 ', 40 "....

Therefore, in order to prevent the signal level from being lowered, it is necessary to further increase the vertical line capacity or to adopt a multi-output line system in which the horizontal line is divided and the signal is read.

However, the former has a problem that the chip area increases, and the latter has a problem that the number of pins is increased after the output terminal.

In addition, as another method, it is considered to prevent the signal level from decreasing by inserting an amplifier between the vertical line and the horizontal line. However, in this method, since the configuration of the amplifier section is complicated, there are drawbacks that the chip area is increased and the horizontal shift register section is further complicated.

 An object of the present invention is to solve the above problems.

<Means for Solving the Problem> The present invention has a plurality of photoelectric conversion pixels,
A plurality of capacitance means for temporarily holding the signal of each pixel, a plurality of first amplifiers smaller in number than the capacitance means for sequentially increasing the signal held in each capacitance means, and outputs of the plurality of amplifiers Has a common second amplifier for commonly amplifying.

<Operation> A signal formed by a plurality of photoelectric conversion pixels is temporarily stored by a plurality of capacitance means, and when sequentially reading out the stored signals, a first amplifier, which is smaller in number than the capacitance means, is used. Second output common after reading
Since it is led to the amplifier, there is no reduction in output due to capacitance division, and since it is not necessary to provide the first amplifier for all capacitance means, the configuration is simple.

<Examples> The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a photoelectric conversion device according to a first embodiment of the present invention, and FIG. 2 is its drive timing chart.

In the figure, 1 is started by the pulse phi _HS horizontal shift register, reverse phase pulse phi _HI each other, sequentially and one at a high level of the output line by phi _HS.

It should be noted that one of the output lines of the shift register 1 is configured to be at a high level while φ _HI is at a high level.

Reference numeral 2 is a bipolar transistor having a capacitor connected to its base, which constitutes one pixel, its emitter is connected to the vertical signal line V _SL , and its collector is connected to a constant voltage source.

Reference _numeral 3 is a transistor for clearing the residual signal on the vertical signal line V _SL while φ _VC is at a high level.

Further, T-Tr is a transistor for selectively connecting the signal line V _SL and the capacitor CTn (n is an integer).

R-Trn is a transistor for sequentially guiding the signal accumulated in each capacitor CTn to the signal line SL by the scan output of the shift register.

C-Tr is a transistor for clearing the residual charge of the signal line SL.

STrm (m is an integer) is a buffer amplifier, SW-Trm is a transistor for selectively connecting the power supply V _DD to each transistor S-TrmT, and is turned on while the pulse φ _Vm is at a high level. Reference numeral 4 is an output amplifier, and CPC is a clamp circuit for clamping the clamp voltage V _CP at the timing of the pulse φ _CP .

The feature of this embodiment is that a capacitor CTn is provided for each signal line V _{SL, and} that a buffer amplifier S-Trm for reading the signal of this capacitor CTn is provided to suppress the output reduction due to the capacitance division. To minimize the power consumption of this buffer amplifier and the heat generated due to this, φ _V1
Is provided with a transistor SW-Trm that turns on and off, and one buffer amplifier is provided for each vertical signal line to prevent an increase in the chip area due to the transistors SW-Trm and S-Trm. .

 Next, the operation of this embodiment will be described with reference to FIG.

First, the unnecessary charge on the vertical signal line V _SL and the temporary storage capacitor is t
Removed in period ₁ .

Next, during the period of t ₂ , the signal of each pixel is CTn by φ _D and φ _T.
Transferred to. The signal charge accumulated in C _T is read out to the output amplifier 4 via the buffer amplifier STrm by sequentially opening and closing the read transfer transistor R-Tr in synchronization with φ _HI .

At this time, power is supplied to only the read signal buffer amplifier S-Trm corresponding to the read.

That is, the period t during which SW-Tr1 is controlled to be conductive by φ _V1
3 is only the period during which the signals of the temporary storage capacitors CT ₁ , CT ₂ , and CT ₃ are read out.

The common signal line SL has a pulse φ _{HC for} each bit transfer,
It is held at a certain reference potential.

This is because the residual charge is removed and the variation ΔV _T of the threshold level of the buffer amplifier S-Tr is corrected. That is, the variation ΔV _T can be removed by clamping the portion of the output signal Sout corresponding to the reference voltage with the pulse φ _CP for each bit.

The buffer amplifier S-Trm in the embodiment of FIG. 1 is composed of a MOS transistor, but it can be replaced with a bipolar transistor as in the second embodiment shown in FIG. If the buffer amplifier is composed of bipolar
SW-Trm is unnecessary. This is because the bias component of the signal on C _Tn at the time of reading biases the bipolar transistor in the forward direction.

Next, FIG. 4 is a diagram showing the embodiment of FIG. In FIG. 4, the power supply transistor SW-Trm is controlled by the output pulses φ _HI and φ _HC of the shift register.

That is, in FIG. 4, the same reference numerals in FIGS. 1 to 3 indicate the same elements and have the same configuration.

In this embodiment, a plurality of transistors D-Trn are provided for the gate of the transistor SW-Trm. Further, the respective transistors D-Trn are scan outputs φ _HI and φ _{HC of the} shift register 5.
It is different from the configuration shown in FIG. 1 in that it is configured to be sequentially turned on.

 The operation will be described below.

The pulses φ _HC , φ _HI , φ _T , φ _CP, etc. are driven at exactly the same timing as in FIG. However, φ _V , φ _V , ... φ _vm does not exist.

It is assumed that the signal is currently stored in the capacitor CTn.

First, φ- _HI-1 turns on D-T _r1 and R-T _r1 . As a result, SW-T _r1 is turned on, the signal of CT ₁ is amplified to S-T _r1 and output to the output line LS.

Then phi _HI-1 is phi _HC-1 becomes the low level to the high level when the D-T _r2 and C-Tr is turned ON. As a result, the reference 0 level is input to the base of the buffer transistor S-T _r1 and SW-T _r1 is also turned on.
Output to S. This signal is a clamp pulse φ at the same timing as φ _HC by the same clamp circuit CPU as shown in the first figure.
_Clamped with _CP .

Similarly, the signals of CT ₂ and the reference 0 are obtained by φ _HI-2 and φ _HC-2.
The level signals are output in dot order, and thereafter such operations are sequentially performed.

According to the present embodiment, compared with the first embodiment, φ _V1 , φ _V2 , ...
…, Φ _Vm is not required, so the number of pulse input terminals is reduced and the wiring area can be reduced.

<Effect> According to the present invention, it is possible to suppress the deterioration of the signal of the photoelectric conversion pixel due to the capacitance division without increasing the capacitance means.
Moreover, the heat generated by the first amplifier can be reduced, and
The configuration of the first amplifier can be simplified.

[Brief description of drawings]

FIG. 1 is a first embodiment of the photoelectric conversion device of the present invention, FIG. 2 is a timing chart of the first embodiment, FIG. 3 is a configuration diagram of a main part of the second embodiment, and FIG. 4 is a third embodiment. Of the essential parts of the
The figure is a block diagram of a conventional example.

Claims (1)

[Claims] 1. A plurality of photoelectric conversion pixels, a plurality of capacitance means for temporarily holding a signal of each pixel, and a plurality of capacitance means which are smaller in number than the capacitance means for sequentially increasing the signal held in each capacitance means. A first amplifier, a common second for commonly amplifying the outputs of the plurality of amplifiers,
Photoelectric conversion device having an amplifier.