JPS63151265A - Line type tone recorder - Google Patents

Abstract

PURPOSE:To record tone at a high speed by correcting a tonal recording data to drive a heater corresponding to the hysteresis of driving. CONSTITUTION:Data D1-D3 that are outputted convertibly from memories M1-M3 are supplied to an adder ADD from which a sum data is outputted. The transmission of data is executed in synchronism with a basic address clock ADCK supplied from a timing control circuit 5 and a line synchronizing pulse LS. The output data D of the adder ADD is supplied to a subtractor SUB along with the data di of an i-th line, and a subtraction Di=di-D is executed in the subtractor SUB, and an arithmetic result Di is outputted. The data Di stored in an output line memory OB1 or OB2 in such a way as the above, comes to be such a data as processed corresponding to the past hysteresis of a j-th line in the subscanning direction (direction of paper feeding) of a picture element.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a line type gradation recording device that performs density gradation recording using a line type thermal head.
Specifically, this relates to improving recording speed.

(Prior art) Fig. 6 is a characteristic diagram showing, by linear approximation, the relationship between the coloring temperature of thermal recording paper and the pulse width of the drive signal of a thermal head with a constant signal level, and the vertical axis shows the coloring density d. , and the horizontal axis shows the pulse width t. As is clear from FIG. 3, the thermal recording paper begins to develop color when a driving signal with a pulse width to having a constant signal level is applied, and until the pulse width ts is reached, the color develops in proportion to the pulse width. lIi degree increases, and the maximum moisture degree diN- with a pulse width of 1 s
Become aX.

By the way, if the recorded Wi mark of one pixel is expressed by n bits, a recording density of 2n gradations will be obtained.

In such density gradation recording of 2n gradations, the pulse width (ts −'jo) of the thermal head used as a heating element is set to 2.
Pulse width tπ = (js-1o)/2” divided by n
It is only necessary to apply a weight to each bit and drive it with a drive signal. That is, the total pulse width t required for arbitrary ma recording is t=ao to+bo20t71
+b+ 2' i7c +-+t)TI-+ 2"-
' It can be expressed as t71. Here, bO9b1.
....

bπ-1 is binary n-bit gradation recording data per pixel, and ao is these n-bit gradation recording data b. +b++...+bn-1, and to is the pulse width necessary as an offset for preheating the thermal recording paper.

For example, the number of gradations is 8 (n-3>, tE= (isL
o)/2', the total pulse width t required for arbitrary density recording is t-ao to +botE+b, 2 jε+b241
= becomes. Here, each time slot T corresponds to each data aO+ bO+ b + and b2.

~ T3 (Pulse width weighting (P is T 3 ”
It is assumed that To>T2>TI is set.

To record one line of density gradation, four time slots To"-Ti are sequentially taken in, and a plurality of heating elements arranged in a line are weighted for each time slot bottom 0 to T3. Selective driving is performed with a predetermined pulse width.

By the way, when a thermal head is continuously driven, heat is accumulated in the head, resulting in recording with an excessive degree of color development such as tailing and collapse, and an expansion of the color development area, resulting in a difference in the recorded image compared to the original image. The high frequency characteristics will deteriorate.

Therefore, for example, one or more preliminary pulses that are turned on and off according to the past drive history are assigned to some of the drive pulses of the heating element, and these preliminary pulses are selectively turned on and off according to the drive history. By turning off the heating element, the drive pulse width of each heating element is controlled to prevent recording quality from deteriorating due to heat accumulation.

(Problem to be Solved by the Invention) However, in order to control the driving pulse width of each heating element by allocating preliminary pulses in this way, it is necessary to increase the time slots according to the preliminary pulses, and as a result, In other words, the recording speed will be reduced.

In addition, with such a concept of preliminary pulses, it is difficult to respond in detail to various combinations of histories of multiple past lines.

The present invention has been made with attention to such problems, and its purpose is to perform high-speed gradation recording by correcting gradation recording data for driving a heating element according to the driving history. The object of the present invention is to realize a line type gradation recording device as described above.

(Means for Solving the Problems) The present invention, which solves these problems, uses a line-shaped thermal head in which a plurality of m heating elements are arranged in a line, and the drive pulse width of each heating element is In a line type gradation recording device that performs density gradation recording by controlling The present invention is characterized by comprising: means for obtaining conversion data according to the history of a plurality of j lines; and means for subtracting input data and conversion data to obtain gradation recording data to be recorded next.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, and it is assumed that m-degree recording of 8 gradations is performed in 3 pixels 1 to 1 as described above.

In FIG. 1, 1 is a line-shaped thermal head in which a plurality of m heating elements are arranged in a line, 2 is thermal recording paper,
3 is a motor that transports the thermal recording paper 2 at a predetermined speed, 4 is a drive circuit for the motor, and 5 is a timing control circuit that sends predetermined control signals to each part.

IB is a line memory that stores gradation recording data of a plurality of past lines, and in this embodiment, an example is shown in which gradation recording data D of three past lines is stored in three line memories IB+ to IB3. M1 to M3 are memories, which convert and output history coefficients D1 to D3 corresponding to each line using the gradation recording outputs DL-+ to Di-3 of each heating element of each line memory IB+ to IB3 as addresses. ADD is an adder that adds history coefficient outputs D+ to D3 of these memories M+ to M3. SUB is input data d.

This is a subtracter that subtracts the output of the adder ADD and outputs data Di to be recorded next. The output of the subtracter SUB is sent to the line memory O via the demultiplexer ODM.
B1. Added to OB2 and demultiplexed
+IDM to line memories I B + to IBs. Then, line memory OB1. The data stored in OB2 is added as data (Di-1) to the thermal head 1 alternately line by line via the multiplexer MUX. It has a width of bits, and each bit has a depth corresponding to the number n of gradation bits.

FIG. 2 is a diagram showing a specific example of a drive circuit for the thermal head 1. As shown in FIG. In FIG. 2, one end of the heating elements 61-6m constituting the thermal head 1 is commonly connected to the DC power supply 7, and the other end is connected to the output terminal of the corresponding Nant gates 81-8. An enable pulse EP is commonly applied from the timing control circuit 5 to one input terminal of the Nant gates 81 to 8, and corresponding bit data of the shift register 10 is applied to the other input terminal via the latch 9. There is. The latch 9 is connected to the timing control circuit 5
The data of each bit of the shift register 10 is latched in accordance with the latch control pulse LP applied from the shift register 10. The shift register 10 has a width of m bits corresponding to the number m of heating elements 6, and stores the data sent from the multiplexer MLIX as serial data in accordance with the clock CK applied from the timing control circuit 5.

The operation of the apparatus configured as shown in FIGS. 1 and 2 will be explained.

First, data (
The procedure in which D<1)- is read out, transferred to the thermal head 1, and recorded will be explained using the timing chart of FIG.

In FIG. 3, (a) shows data (Dt-1>-) applied to the thermal head 1.

This data (DL 1)- is the clock C shown in (b).
According to the address of an address counter (not shown) operated by K, line memories OB1. From OB2: ■Logical OR of bits 0 to 2, ■Bit 0. ■Bit 1. ■Pips 1 to 2 are read out in order,
It is transferred to the shift register 10 together with the clock OK. Each time m-bit data of one line is transferred to the shift register 10, it is latched into the latch 9 by the latch pulse LP shown in (C). After the data is latched in this way, each bit data
Predetermined pulse width tO* tO~t corresponding to the weight of ~■
An enable pulse EP having a value of 2 is applied to the Nant gate 8 and recording is performed. (e) is a line synchronization pulse LS that sets the recording cycle of one line, and the paper feed motor 3 rotates by a predetermined angle in accordance with this line synchronization pulse LS. (f) is the basic address clock ADCK of data, and the detailed timing relationship will be explained with reference to timings p-1 and up in FIG. 4.

In FIG. 4, (a) is an enlarged view of the basic address clock ADCK in FIG. 3(f). At the rising edge of the basic address clock ADCK, the address counter in the timing control circuit 5 is activated and supplies address data to the line memories IB+ to rB3tJ and OB+ or OB2. The 1-level interval of this basic address clock ADCK is the line memory JB+ to I
The data in B3 is read, and during the L level period, data is written to any of the line memories IBI to IB3 and the data is written in the line memories OB1. Write data to either OB2.

First, for a certain address data Aχ shown in (b), (
As shown in C), n-bit data D, -1 to Di-3 are read from the line memories IB+ to IB3, respectively. The memories M1 to M3 store these data Di-+ to D, -
3 as the address input, each n as shown in (d)
Bit data D+ to D3 are output. Here, these data D1 to D3 are set by 1 to a predetermined history coefficient corresponding to the history of multiple past lines for data Dj-+ to DL-3.
~ is multiplied by (k≦1. + >k2 >k3), and the following relationships hold: D+ = + *Di -+ 02 = 2 *Dt -2 D3 = 3*Dt -3 do.

The data D, -D3 converted and outputted from the memories M, -M3 in this way are added to the adder ADD, and the summation data D (D- ΣDJ) is output. Data is sent from the host computer (not shown) in synchronization with the basic address clock ADCK and line synchronization pulse LS sent from the timing control circuit 5. Therefore, the i-th line data dL is input at a timing almost synchronized with D, as shown in (f).

The output data D of the adder ADD is the i-th line data d,
and is added to the subtractor S LJ B, and as shown in ()>, subtraction of Dc=diD is performed at the falling timing of the basic address clock [1 ts ADCK, and the operation result Dc is output. .

is the line memory IB+ via the demultiplexer rDM.
The oldest data among IB3 is written to the line memory (1B3 in this embodiment) at the same address Aχ at which the data is read at the 1-level timing of the basic address clock ADCK. At the same time as this writing, data II) t is transferred to the demultiplexer ODM.
The line memory OB1. The line memory in which old data is stored in OB2 (in the case of this embodiment, the line memory
B2) is also written to the same address Aχ at which the data is read at the timing of the L level of the basic address clock ΔDCK. And line memory OB+ or O
As described above, the data DL stored in B2 is sequentially transferred to the thermal head 1 at a timing different from the basic address clock ADCK although it is synchronized with the line synchronization pulse LS.

This series of processing is performed on all addresses △. ~Am-4, that is, executed for one line consisting of m dots,
Furthermore, similar processing is repeated for each line.

In this way the output line memory OB+ or OB2
The data Dt stored in is subjected to processing expressed as Dj=dj-ΣkjDt-J according to the history of the past j lines in the sub-scanning direction (paper feeding direction) of a certain pixel. Here, kj has different values depending on the values of past j lines.

In other words, j is a subscript representing the number of past lines, and the value of j should be set so that the influence of past heat generation disappears (heat accumulation disappears) in the period of recording j lines in the sub-scanning direction. good.

With this configuration, history control can be performed without increasing the number of time slots (and without reducing the recording speed) unlike in the case of using a conventional preliminary pulse.

In the above embodiment, the data stored in the line memories IB+ to IB3 are stored in the corresponding memory M1.
~Conversion output D according to history as address input horn of M3
1 to D3, and adder A converts these converted outputs DI-03 to
Although we have shown an example of calculating the sum in addition to DD, as a simplified version, as shown in FIG. The conversion output corresponding to the history may be obtained by inputting the address of the memory M. According to such a configuration, memory can be reduced.

(Effects of the Invention) As described above, according to the present invention, the linear gradation allows high-speed gradation recording by correcting the gradation recording data for driving the heating element according to the drive history. A recording device can be realized, and the practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention, FIG. 2 is a concrete example diagram of a driving circuit for a thermal head, and FIGS. 3 and 4 explain the operation of FIGS. 1 and 2. Figure 5 is a configuration explanatory diagram showing the main parts of the embodiment of the present invention, Figure 6 is a linear approximation of the relationship between the coloring temperature of the thermal recording paper and the pulse width of the drive signal of the thermal head. It has the characteristics shown in . DESCRIPTION OF SYMBOLS 1...Line type thermal head, 2...Thermal recording paper, 3...Motor, 4...Motor drive circuit, 5...
・Timing control circuit, 61~6m...heating resistor (
heating element), 7... DC power supply, 81 to 8 layers... Nantes gate, 9... Latch, 10... Shift register,
IB, 10...Line memory, M...Memory, 80D...Adder, SUB...Subtractor, ODM, IDM
...Demultiplexer, MUX...Multiplexer.

Claims (1)

[Claims] Line-type gradation recording that uses a line-shaped thermal head in which a plurality of m heating elements are arranged in a line, and performs density gradation recording by controlling the drive pulse width of each heating element. The apparatus includes: j line memories for storing gradation recording data of a plurality of past j lines; a means for obtaining conversion data according to a history of a plurality of past j lines based on the gradation recording output of each line memory; and an input. A line type gradation recording device comprising: means for subtracting data and conversion data to obtain gradation recording data to be recorded next.