JP2547939B2 - Color image processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image processing apparatus.

[0002]

2. Description of the Related Art Conventionally, for example, in a digital copying machine, data of respective colors R, G, B are read, the read image data is converted into a digital signal, and then data processing is performed, and a laser beam printer, a liquid crystal printer, an ink jet printer. And the like are used to form a color image.

Then, such data processing is performed by R, G, B
Signal or Bk generated from Y, M, C after Y, M, C
The recording signals of were processed in parallel.

Further, when this processing is simply performed with the color sequential data as it is, after the black signal is extracted by the black extraction unit, the color sequential data is converted into parallel for each color to generate again the color sequential data including the black signal. Or, the color sequential data consisting of Y, M and C and the black signal must be independently provided with a memory for time conversion to generate a color sequential signal containing the black signal,
There is a problem that the circuit scale becomes large.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned prior art, in which the color sequential image data to be input is processed by a processing system including a black extraction circuit without having a circuit for each color. An object of the present invention is to provide a color image processing device having a data structure capable of real-time processing as it is.

[0006]

In order to solve the above-mentioned problems, the present invention provides an input means for time-divisionally inputting a plurality of color component signals forming pixels, and serially outputting the plurality of color component signals for one pixel. Output means for serially outputting the plurality of color component signals for the one pixel input from the input means at a cycle obtained by adding a predetermined time to the time required for output to A black signal is extracted by using the plurality of color component signals output to, and the extracted black signal is continuously output to the serial plurality of color component signals used when the black signal is extracted. And a black signal processing means for outputting the extracted black signal during the predetermined time when no signal is output from the output means.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of color image processing of this embodiment.

In the figure, 100R, 100G, 100B
Are CCD line sensors for detecting the R, G, and B components of the original, respectively. Each color signal from the line sensor is sequentially converted into a digital value by the analog-digital converter 110.

Therefore, the A / D converter 110 has B, G, R,
Digital data is output in the order of B, G, R ....

The obtained digital data is the complementary color conversion circuit 1
At 20, it is converted into complementary color data Y, M, C, and Y, M, C,
It is output in the order of Y, M, C ....

The obtained color-sequential color image data is sent to the time axis conversion unit 200a. Since the frequency of the input image data is different from that of the subsequent image data in the time-axis conversion unit, the time-axis conversion unit 200a performs frequency conversion according to the time-axis conversion control signal sent from the control unit 200 and outputs the result. . The output image data (hereinafter, input image data) is sent to the serial / parallel conversion unit 201,
After being converted into Y (yellow), M (magenta), and C (cyan) parallel signals, the signals are sent to the masking unit 202 and the selector 203.

The masking section 202 is a circuit for correcting the turbidity of the color of the output ink, and carries out the following calculation.

[0013]

[Outside 1] Y, M, C: Input data Y ', M', C ': Output data

These nine coefficients are determined by the masking control signal from the control unit 200 and the masking unit 202.
After the ink has been corrected for turbidity with, it is input to the selector unit 203 and the UCR unit 205 as a serial signal.

The selector 203 has input image data,
Also, the image data output from the masking unit 202 is input.

In the selector 203, the normal control unit 200
The input image data is selected by the selector control signal 1 sent from the controller. When the color correction in the input system is not sufficiently performed, the masking unit 202 is controlled by the control signal 1.
Output image data is selected and output. Selector 2
The serial image data output from 03 is the black extraction unit 2
It is input to 04. Since the minimum value of Y, M, and C in one pixel is used as black data, the black extraction unit 204 detects the minimum value of Y, M, and C. The detected black data is input to the UCR unit 205.

The UCR unit 205 subtracts the black data extracted from each of the Y, M and C signals. The black data is simply multiplied by the coefficient. The black data input to the UCR unit 205 is corrected for time lag with the image data sent from the masking unit 202, and then the calculation of the following equation is performed. Y ′ = Y−a ₁ Bk M ′ = M−a ₂ Bk C ′ = C−a ₃ Bk Bk ′ = a ₄ Bk Y, M, C, Bk: extractor, input data Y ′, M ′, C ′, Bk ′: Extractor, output data Coefficients (a ₁ , a ₂ , a ₃ , a ₄ ) are determined by the UCR control signal sent from the controller 200.

The data output from the UCR unit 205 is
Next, γ is input to the offset unit 206.

The γ / offset unit 206 performs gradation correction as in the following equation. Y ′ = b ₁ (Y−C ₁ ) M ′ = b ₂ (M−C ₂ ) C ′ = b ₃ (C−C ₃ ) Bk ′ = b ₄ (Bk−C ₄ ) Y, M, C, Bk: γ, offset part input data Y ′, M ′, C ′, Bk ′: γ, offset part output data Further, the coefficients (b _{1 to} b ₄ , C _{1 to} C ₄ ) in the above equation are the control part 20.
Determined by γ and offset control signal sent from 0.

The signal whose gradation has been corrected by the γ offset unit 206 is next input to a line buffer 207 which stores image data for N lines. This line buffer 20
7, the memory control signal sent from the control unit 200 outputs the data of 5 lines necessary for the smoothing and edge enhancement unit 208 in the subsequent stage in 5 lines in parallel. The signals of the five lines are input to a spatial filter having a variable filter size by a filter control signal from the control unit 200, smoothed, and then edge enhanced. In the smoothing, the noise of the image is removed by setting the average value of the target pixel and the peripheral pixels as the density value of the target pixel. Further, as shown in FIG. 2, the difference between the pixel data of interest and the smoothed signal is used as an edge signal, and this is added to the pixel data of interest to enhance the edge. Smoothing edge enhancement unit 208
A detailed description of the above will be given later.

The image data output from the smoothing / edge enhancement unit 208 is input to the color conversion unit 209, and the control unit 2
Color conversion is performed by a color conversion control signal from 00. A digitizer device or the like inputs in advance a color to be converted, a color to be converted, and an area where the signal is effective, and the color conversion unit 209 replaces the image data based on the data. In this embodiment, detailed description of the color conversion unit 209 is omitted. The image signal output from the smoothing / edge enhancing unit 208 and the image signal after color conversion are input to the selector 210, and the image data to be output is selected by the selector control signal 2. Which image data is selected is determined by designating an effective area input from the digitizer device or the like. The image signal selected by the selector 210 has a buffer memory (not shown) and a dither processing unit 211 for binarization processing.
Is input to

Here, description of the system input to the buffer memory is omitted.

The binarization process will be described. The image data to be binarized is displayed on the dither unit 211 of FIG.
Serial 8 bits are input in the order of M, C and Bk.

The dither section 211 has a main scanning direction of 6 bits, a sub scanning direction of 6 bits, or a main scanning direction of 4 bit for each color.
It has a memory space of t and 8 bits in the sub-scanning direction, and the dither matrix size and the dither threshold in the matrix are set by the dither control signal from the control unit 200. When the dither circuit operates, the mechanical main scanning direction is CCD
The image reading section signal of one line of the line sensor, the sub-scanning direction counts the image video clock,
Reads the set dither threshold in memory space. A serial dither threshold can be obtained by serially switching this memory space to Y, M, C, Bk. Next, this threshold value is input to a comparator (not shown) and the selector 210
The size of the input image data is compared.

The output from the comparator is image data> threshold value: 1 image data ≦ threshold value: 0. This data is then output as parallel 4-bit data in the serial / parallel converter.

Next, specific circuits of each processing apparatus shown in FIG. 1 will be described in detail below.

First, the time axis converter 200a will be described.

As shown in FIG. 3- (a), the time axis conversion unit 200a includes a FiFo memory 200 '(μPD42505).
C: made by NEC). The FiFo memory 200 'has write and read counters independently incorporated therein, and has a structure in which write and read counters can be controlled independently.

As shown in FIG. 3- (b), when the reset signal invert RSTW generated at the timing before the data for one line is input and the signal WE indicating the input image signal period is enabled, the FiFO memory Writing is sequentially performed from the address 0 during the enable.
Similarly, in the reading, the reset signal invert RST generated at the timing before the data for one line is output.
When R is input and the read request signal RE from the output side is enabled, reading is sequentially performed from the address 0 of the FiFo memory 200 'during the enable. When RE is disabled, the read counter
The data is not read until it is held at that address and is enabled again.

In this embodiment, as shown in FIG. 3- (b), at the time of writing, the reset signal invert RS is set at the head of each line.
Input TW and enable data section WE to 0
Writing is performed sequentially from the address. Further, the reading is performed from the address 0 by inputting the invert RSTW at the head of every line and setting the portion RE for inserting the black data in the disable state. Therefore, the signal DATA OUT as shown in FIG. 3B is obtained, and the empty time for black Bk is provided. The respective FiFo control signals Invert RSTW, Invert RSTR, WE, and RE correspond to the time axis conversion control signal sent from the control unit 200.

Next, in the serial / parallel converter 201, Y,
The serial color signals of M and C are converted into parallel signals. The circuit of the conversion unit 201 is shown in FIG.

In FIG. 4, reference numerals 40 to 44 are latching registers, and 45 is a latch controller. Latch controller 45
Determines the latch timing of the latching register with the mode signal 6 indicating the type of each color signal. Also, register 4
Reference numerals 0 and 41 are delay registers. Registers 42, 4
When C, M and Y are input to 3 and 44 respectively, the latch controller outputs a signal 46 and latches the registers 42, 43 and 44. Therefore, each of the latches 42, 43, 44 is Y,
Outputs of M and C are obtained.

Next, the serial / parallel converter 201
The Y, M, C serial color signals are converted into color sequential image data.
After the parallel conversion, the masking section 202 is entered. Ma
In the skiking section, as shown in FIG. 5- (a), the multiplication table
Table conversion is performed using the RAMs 220 to 222.
Have been. Only Y data using FIG. 5- (b)
Y will be input when explaining₀Pixel data of 1 cycle
The table RAMs 220 to 222 are loaded into the
By switching 4 times a₁₁Y₀, A_{twenty one}Y₀, A
₃₁Y₀, 0 are serially obtained. Same for M and C
Like a₁₂M₀, A_{twenty two}M₀, A₃₂M₀, 0 and a₁₃C₀, A_{twenty three}
C₀, A₃₃C₀, 0 in that order.

After that, addition is performed by the adder 223, whereby the following masking calculation is performed and the colors are sequentially output.

[0035]

[Outside 2]

Next, the black extraction unit 204 will be described with reference to FIG. The input image data is Y, M, C, α
Input in the order of (empty). Here, in the case of 8-bit image data, α is data-corrected so that it becomes FFH in hexadecimal display (H). Such color-sequential image data is input to the comparator 224 and the flip-flop 225. Here, when the α data (FFH) is input, the flip-flop 225 is forced to hold the data. Next, the data held in the flip-flop 225 and the image input data are sequentially compared.

Input image data <flip-flop 225
Only in the case of held data, a latch pulse is sent from the latch timing generator 227 to the flip-flop 225 by the signal from the comparator 224, and the input image data is held. When the image data (Y, M, C) for one pixel is compared, the minimum image data of Y, M, C held in the flip-flop 225 is the flip-flop 226.
Is held. In this way, the minimum value of Y, M, and C, that is, black extraction is performed with the color-sequential image data as it is, and the extracted black data is output.

Next, the UCR will be described with reference to FIG. The black data enters the coefficient multiplication table RAM 228. In addition to this, a color mode signal for color discrimination is input from the control unit 200. The color mode changes to Y, M, C, and Bk while black data for one pixel is being input. With this color information, the coefficient table is switched for each color, and the coefficient is multiplied independently for each color. The black data multiplied by the coefficient is subtracted from the image data sent in color order by the next subtractor 229 and output.

Next, the γ offset section (FIG. 8) will be described.

In the γ offset section, the RAM 160 performs the following operation as in the coefficient multiplication table RAM 228 shown in FIG. Y '= α ₁ (Y-β ₁ ) M' = α ₂ (M-β ₂ ) C '= α ₃ (C-β ₃ ) Bk = α ₄ (Bk-β ₄ ) The input data is the color mode. The table is switched for each color according to the signal, and γ and offset are calculated for each color and output.

Next, the smoothing process will be described with reference to FIG.

Next, the image data is stored in the line buffer 207 for each line while keeping the color sequence. Since the filter this time is performed in a 5 × 5 area, color-sequential image data is output in 5 lines in parallel. For example, the smoothing process will be described. Color-sequential 5-line data input as shown in FIG. 9 is added by an adder 230 and then delayed by flip-flops 231 to 234. Here, each of the flip-flops 231 to 234 has a configuration in which four pixels are delayed by serially connecting four flip-flops. As a result, even if the image data is input in color sequence, filtering can be performed for each color. This time the filter matrix is 5 × 5
However, the size is not specified. The pixel data delayed in this way is input to the adder 235 where it is added and then divided by the division R.
The table is converted to 1/25 in the AM 236 and the colors are sequentially output. A description of the edge enhancement and color conversion unit will be omitted.

The dither will be described with reference to FIG. Counters 237 to 240 are provided for each color so that the dither can be changed for each color. Four
The counter value (YD, MD, CD, BkD) for each color is
YD, MD, CD, B in the parallel-serial conversion unit 241
The data are sequentially output to the dither RAM 242 in the order of kD. In the dither RAM 242, the dither threshold for each color is independently changed by switching the upper address according to the color information. The dither threshold values thus sequentially output from the dither RAM 242 in color order are input to the comparator 243. In the comparator 243, the image data sent in color sequence and the dither threshold value sent in color sequence are compared, binarized, and then converted by the serial / parallel conversion unit 212 to Y, M, C. , Bk, 1-bit each, a total of 4-bit signal is output.

As described above, it is possible to perform black extraction, UCR, γ correction, dither processing, smoothing, edge enhancement processing, etc., except for the masking processing, using the color sequential signals as they are.

The design of the circuit for color sequential signal processing of this embodiment can be changed in various ways.

[0046]

As described above, according to the present invention,
As a method for continuously serially outputting a plurality of color component signals for one pixel input in time division and a black signal extracted from the plurality of color component signals, the extracted black signal and the plurality of By storing a memory independently for each color component signal and outputting a black signal at a predetermined time without a continuous signal for a plurality of color component signals without using a configuration for reading the signals from both memories at a timely timing, It is effective that the circuit scale can be reduced without using an expensive memory.

[Brief description of drawings]

FIG. 1 is a block diagram of a color image processing apparatus of this embodiment.

FIG. 2 is a timing chart of smoothing and edge enhancement processing.

FIG. 3 is a time axis conversion circuit diagram and a timing chart of each part of the time axis conversion circuit.

FIG. 4 is a diagram showing a detailed circuit of a serial-parallel converter.

FIG. 5 is a detailed circuit diagram of a masking section and a timing chart of each section of the masking circuit.

FIG. 6 is a detailed circuit diagram of a black extraction unit.

FIG. 7 is a detailed circuit diagram of a UCR unit.

FIG. 8 is a γ offset circuit diagram.

FIG. 9 is a detailed circuit diagram of smoothing.

FIG. 10 is a detailed circuit diagram of a dither processing unit.

Claims (1)

(57) [Claims] 1. Input means for time-divisionally inputting a plurality of color component signals constituting a pixel, and a period of time required for serially outputting the plurality of color component signals for one pixel plus a predetermined time period. Output means for serially outputting the plurality of color component signals for the one pixel input from the input means, and a black signal using the plurality of color component signals serially output for each pixel by the output means Means for outputting the extracted black signal in succession to a plurality of serial color component signals used for extracting and extracting the black signal, wherein the signal is not output from the output means. And a black signal processing means for outputting the extracted black signal at time.