JPS63151187A - Solid-state image pick up device - Google Patents

Abstract

PURPOSE:To ease the design of an amplifier, etc. and gain control, and to reduce the error of a white balance by applying dot sequential system to the signals of plural horizontal lines, alternately, and controlling a gain by one amplifier. CONSTITUTION:When horizontal drive lines V1 and V2 come to H, the signals of the line P-1n and of the line P-2n of a photoelectric converting element are read out in vertical signal lines VLA, VLB, and they are transferred onto a horizontal signal line So, when a horizontal switch transistor (TR) H-Tr comes successively to H by signals HAn, HBn. Because the TR H-Tr is made to ON-OFF in regular order by pulses HAn, HBn from a horizontal shift register 10, the signals of the line P-1n and of the line P-2n are arranged alternately by applying dot sequential system on the horizontal signal line So, and besides, the two horizontal lines to be selected are shifted successively by two lines at every completion of the reading-out of a line unit. These signals are gain- controlled by the single amplifier through an output amplifier OA. Thus, the error of the gain accompanied with plural outputs is removed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a solid-state imaging device using a photoelectric conversion element,
In particular, the present invention relates to a method characterized by a method and structure for reading out a photoelectric conversion signal.

[Prior Art] Conventionally, in a solid-state imaging device using a MOS type solid-state imaging device, it has been difficult to simplify color separation in a signal processing system and improve signal SN.
A double-wire signal readout method is used to improve the ratio.

Furthermore, in order to increase the resolution, a plurality of horizontal signal lines are read out simultaneously and vertical correlation processing is performed.

However, in the above method, the number of fixed amplifiers or AGC amplifiers inevitably increases as the double-wire output increases.

[Problems to be Solved by the Invention] In this case, if there is an error in gain between multiple amplifiers, it becomes an error in white balance and significantly deteriorates image quality. To solve this problem, conventional video cameras integrate the color difference signal error at the final stage before imaging and feed it back to the R and B amplifiers so that the integrated value becomes zero for correction.

However, in recent years, many video cameras have adopted an automatic tracking white balance system, and with this system, the imaging system and white balance control signal formation system are independent, so there is a need for extremely high amplifier precision. Ta.

This problem of gain accuracy becomes even more severe in still video cameras.

That is, since the purpose of a still video camera is instantaneous photography, there are many opportunities to switch the gain of the signal based on the AE detailed information.

In this case, feedback control using a video signal is difficult to instantaneously perform gain control, and an independent control method is preferable, so it is necessary to minimize gain errors.

An object of the present invention is to eliminate the gain error associated with the above-mentioned multiple signal readout.

[Means for Solving the Problems] The present invention includes a photoelectric conversion means in which photoelectric conversion elements are arranged in the row and column directions, and a point sequential means for alternately converting the signals of the photoelectric conversion elements in a plurality of rows into point sequential signals. has.

[Operation] According to the present invention, signals of a plurality of horizontal lines are converted into alternating dot-sequential signals within the solid-state imaging device, and read out as signals in the - column.

[Example] FIG. 1 shows a first embodiment of the invention.

In the figure, 10 is a horizontal shift register, 20 is a vertical shift register and an interlace circuit, P-mn is a photoelectric conversion element in each m rows and n column, OA is an output amplifier, H-T is a horizontal switch transistor column vI to v3 is horizontal driveline,
V.L.A.

vLll is a vertical signal line, H*s-T- is a reset transistor for resetting the horizontal signal line So, H
RS is a reset signal, a signal for reading the signal of the element in the n column of even rows of HAn, and HBn is a signal for reading the signal of the element of the n column of the odd row.

A schematic operation timing chart is shown in FIG. 2. The photoelectric conversion element P-an to be read is a horizontal shift register 10,
Selected by vertical shift register 20.

For example, as shown in the second diagram, the horizontal drive lines Vl and v2
When becomes "H", the photoelectric conversion elements of the P-1n row and the P-2n row are read out to the vertical signal lines VLA, VLB. The signals on the read vertical signal lines are transferred to the horizontal switch transistors H-T, becomes "H" sequentially by HAn and HBn, then the horizontal signal line S passes through the H-Tr.
transferred on o.

The horizontal switch transistor H-TR is turned ON-OF in order by the pulses HAn and Han from the horizontal shift register.
Since the P-Is row and the P-Is row are on the horizontal signal line,
-2n rows of signals are alternately arranged in dot sequence.

Further, the two selected horizontal rows are sequentially shifted by two rows each time reading of each row is completed.

These signals pass through the output amplifier OA and are gain controlled by at least a single amplifier, which will be described later. Therefore, gain errors associated with multiple outputs are eliminated.

In FIG. 1, the horizontal reset transistor HRS −
Tr sets the horizontal signal line to a reference potential for each bit.

[Other Examples] Other embodiments of the invention are shown in FIGS. 3 and 4.

In FIG. 3, the horizontal signal line is composed of two lines, and point adjustment processing is performed at the final stage. The same reference numerals as in FIG. 1 indicate the same elements. S Is"'2 is the horizontal signal line, S-
T, , S-'rr* is a switch transistor for point sequentialization, 5-PI, 5-P2 are control signals for turning on each switch transistor, and 5-PI is when HAn is "H". 5-P2 becomes "H" when HBn is "H". The method of reading out the signals of each element on the vertical signal lines VLA and VLB is the same as in the embodiment of FIG. When transferring a signal onto the horizontal signal line, the pulse HAn・1 (Bn of the horizontal shift register lO is in reverse phase. When the pulse HAn is “H” (i.e., ON state), the output transistor 5-PI is H ”, then pulse HB
When n is "°H", 5-P2 becomes "H" and the output S
In O, the signal for two horizontal lines is converted into point sequence. The horizontal reset transistor HRS-Tv becomes H'' and is reset immediately before the pulses 5-Pi and 5-P2 to the output transistors 5-Tri and 5-Tr2 fall, respectively.

FIG. 4 shows the third embodiment, and the difference from the first embodiment is that the photoelectric conversion signal of the vertical signal line is once stored in the storage capacitor C.
T, then sequentially transferred onto the horizontal signal line,
There is a point to be made point sequential, and a transistor array H-Tr
Each train is connected to a common horizontal signal line SO, and each source is connected to a switch T that is selectively turned on.
- Connected to a common vertical signal line via T r. A storage capacitor CT is connected to each source of each transistor H-Tr.

Therefore, the operation is to first set vl to "H" during the horizontal blanking period of the standard television signal, and then set T to "H".
Then, the signal of the first row is stored in CA, and then, v2 is set to "H" and To is set to "H", and the signal of the second row is stored in Cr. After that T 0. By setting Tt to "L" and then sequentially turning on H-T, the signals in the first and second rows can be read out in alternating dot-sequential form.

Next, an embodiment of a solid-state imaging device using the solid-state imaging device of the new readout method will be described with reference to FIG.

FIG. 5 is a system schematic diagram of a still video camera.

In the figure, 100, 170, and 180 are solid-state image sensors, drivers, clocks, and generators, 110 is an imaging optical system, 120 is an aperture, 130 is a beam splitter,
140 is a shutter, 150 is a sensor for photometry, 160 is a color temperature detection sensor, 200 is an integrator for detecting the average level of the video signal, 210 is a gain control amplifier that changes the video signal level to an appropriate level, 230 is a color separator that separates each color signal R, G, and B from the signal of the amplifier 210; 240 is a luminance signal generator that converts the R, G, and B signals into a dot sequence to form a wide-range Y signal; and 250 and 260 are Gain control amplifier 270 for R and B signals for white balance, for example,
280 is a magnetic signal processing circuit that performs modulation suitable for recording; 290 is a head 300 that is a recording medium; 31O is a motor for rotationally driving the recording medium 300; 190 is a system This is a system controller that includes a microcomputer that controls the entire system.

Next, we will explain the general operation of this system.

Light information passing through the lens 110 and the aperture 120 is input to the photometric sensor 150 via the beam splitter 130. A sensor 1 for detecting zero color density, in which a photometric calculation is performed based on a signal from a photometric sensor 150, and the aperture value of an aperture 120 and the shutter speed of a shutter 140 are determined.
At 60, the color temperature is measured, and the G
-C amplifiers 250 and 260 are controlled.

The solid-state image sensor 100 is driven by drive pulses obtained by buffering pulses from the clock generator 180 with the driver 170.

The signal from the solid-state image sensor 100 is integrated by the integrator 200, and the system controller 190 compares and determines the signal level at that time with an appropriate level to determine a gain correction value for the gain control amplifier 210. If the solid-state image sensor 100 is one that destroys and reads the photoelectric conversion signal (for example, a MOS type or a CCD type), the output of the integrator 200 is obtained after the release for photographing, a gain correction value is calculated, and the aperture is adjusted. Regarding the value and shutter speed, the image is captured again using the photometric calculation value, and the signal with the amplifier 210 controlled by the gain correction is recorded.

Further, in the case where the solid-state image sensor 100 is read out in a non-destructive mode (for example, the one shown in Japanese Patent Application Laid-open No. 12764/1983), the second imaging is unnecessary, and after controlling the amplifier 210 with the gain correction value, The signal may be read out again from the image sensor 100 in a non-destructive manner.

The color separation circuit 230 separates the dot sequential signal from the amplifier 210 into, for example, R-G-B signals necessary for subsequent video signal processing, and the Y forming circuit 240 converts the dot-sequential signal again into a dot-sequential signal to form a luminance signal. The color signals R and B are subjected to white balance control by gain control amplifiers 250 and 260, and a video signal processing circuit 270 performs processing necessary for the TV signal. In addition, the magnetic signal processing circuit 280
A high frequency signal to be recorded at 00 is formed and recorded on the medium 300 via the head 290. The medium 300 is a motor 310 controlled by the system controller 190, for example:
It is rotated at a high speed of 1600 rpm.

[Effects] As described above, by alternately converting the signals of multiple horizontal lines into point sequence and controlling the gain using one amplifier, the design of the amplifier etc. and AGC control are facilitated. I was able to reduce the white balance error.

[Brief explanation of the drawing]

Figure 1 is a first embodiment of the present invention, Figure 2 is a timing diagram thereof, Figures 3 and 4 are diagrams of second and third embodiments of the present invention, and Figure 5 is a system schematic diagram. be. 10 is a horizontal shift register, 20 is a vertical shift register/interlace circuit, 100 is a solid-state image sensor, 200 is an integrating circuit, and 21o is an AGC 1230 is a color separation circuit.

Claims (1)

[Scope of Claims] The present invention is characterized by having a photoelectric conversion means in which photoelectric conversion elements are arranged in the row and column directions, and a point sequential means for alternately converting the signals of the photoelectric conversion elements in the plurality of rows into point sequential signals. Solid-state imaging device.